JP3544427B2 - Integrated circuit with built-in test circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an integrated circuit mounted on a printed circuit board (PC board), and more particularly to an integrated circuit having a built-in test circuit for detecting an open failure of a signal terminal.
[0002]
[Prior art]
A PC board on which a plurality of integrated circuits of a lead insertion type are mounted has a plurality of through holes corresponding to a plurality of leads (external terminals) of each integrated circuit, and a pattern so as to be electrically connected to each through hole. And a plurality of printed wirings formed. The electrical connection between the individual leads and the printed wiring is achieved by inserting the leads of the individual integrated circuits into the corresponding through-holes and soldering all the insertion points. However, soldering defects such as open defects and short defects may occur on the PC board. An open defect is a defect caused by a shortage of solder supply or the like, and unexpectedly results in an electrically open state between the lead and the printed wiring. The short-circuit defect is a defect caused by an excessive supply of solder and the like, in which a plurality of printed wirings are electrically short-circuited with each other. Such a soldering defect may also occur when an integrated circuit employing another packaging technology such as a surface mounting technology is mounted on a PC board.
[0003]
Conventionally, in-circuit testers have been used to detect soldering defects in integrated circuits on PC boards. In this case, the plurality of probe pins of the in-circuit tester are respectively brought into contact with the wiring around the integrated circuit under test. Then, a test data signal is supplied from some of the probe pins to the input terminal of the integrated circuit, and a signal obtained from the output terminal of the integrated circuit is taken into the in-circuit tester as a test result signal from another probe pin, The captured signal is compared with an expected value. From the result of this comparison, the presence or absence of a soldering defect is determined. However, in a situation where a large number of integrated circuits are mounted on a single PC board at a high density or a situation where the PC board has multi-layered wiring, the probe pins may not be able to physically contact the wiring. Therefore, the use of in-circuit testers is becoming impossible.
[0004]
Therefore, it is conceivable to use a boundary scan test (BST) technique disclosed in US Pat. No. 5,084,874 or the like for detecting a soldering defect. According to the BST technology, a test circuit including a plurality of boundary scan cells (BSC) is provided in each of two integrated circuits connected to each other via a plurality of printed wirings on a PC board. Then, the test circuits built in one of the integrated circuits supply test data signals to the printed wirings via the corresponding output terminals of the integrated circuit. A signal on each printed wiring is taken in as a test result signal by a test circuit built in the other integrated circuit via a corresponding input terminal of the other integrated circuit. All BSCs are serially connected to each other in certain modes. Accordingly, the application of the test data signal and the observation of the test result signal are achieved by the scanning operation, and the presence or absence of a soldering defect is determined by comparing the test data signal with the test result signal.
[0005]
[Problems to be solved by the invention]
The above-described detection of soldering defects using the conventional BST technology is based on the premise that each of two integrated circuits connected to each other on a PC board has a built-in test circuit including a plurality of BSCs. there were. Therefore, when one integrated circuit does not include a test circuit, even if the other integrated circuit includes a test circuit, detection of a soldering defect cannot be achieved. Also, if discrete active elements such as transistors and diodes or passive elements such as transformers and capacitors are connected to the signal terminals of an integrated circuit, these elements cannot incorporate a test circuit. Even if the circuit has a built-in test circuit, it is not possible to detect a soldering defect of a signal terminal of the integrated circuit. Therefore, conventionally, a high detection rate of soldering defects in the entire PC board could not be expected.
[0006]
An object of the present invention is to detect an open failure of a signal terminal of an integrated circuit using only a test circuit built in the integrated circuit, regardless of what element the integrated circuit is connected to on a PC board. Is to do so.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a method for measuring the load capacity between a signal terminal of an integrated circuit on a PC board when the signal terminal is normally electrically connected to printed wiring and a signal terminal when the signal terminal is not electrically connected to the printed wiring. This is to detect an open failure of the signal terminal.
[0008]
The quantities representing the electrical characteristics of the wiring include resistance, inductance, and stray capacitance. Among them, it is preferable to select the stray capacitance from the viewpoint of ease of measurement. The relationship between the charging current I (t) and the charging voltage V (t) when charging the stray capacitance C of the wiring is as follows:
I (t) = C × dV (t) / dt
Is represented by Here, t is time. Therefore, the difference in stray capacitance can be detected as a difference in charging time, a difference in charging current, or a difference in charging voltage. Among them, it is preferable to select a difference in charging time from the viewpoint of simplicity of measurement. That is, the open failure of the signal terminal is detected from the difference in the time required for charging the stray capacitance.
[0009]
Specifically, a plurality of tri-state buffers for supplying a charging current to a stray capacitance of a corresponding wiring on a PC board via a corresponding signal terminal in a test mode are provided in the integrated circuit. Since the signal delay time in each of the plurality of tri-state buffers reflects a difference in stray capacitance, a logic signal having a pulse width representing a time interval between the input transition time and the output transition time of the corresponding tri-state buffer is generated. A plurality of exclusive OR gates for providing are further provided in the integrated circuit.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a specific example of an integrated circuit incorporating a test circuit according to the present invention will be described with reference to the drawings.
[0011]
FIG. 1 shows a configuration example of an integrated circuit according to the present invention. The integrated circuit 10 of FIG. 1 includes first and second input terminals IN1 and IN2, one output terminal OUT, and five test terminals TDI, TDO, TCTL, TCK1, and TCK2. When the integrated circuit 10 is mounted on a PC board, the three signal terminals IN1, IN2, and OUT are electrically connected to corresponding wirings on the PC board by soldering. C in FIG. 1 indicates the stray capacitance of each wiring. Reference numeral 11 denotes an internal logic (application logic) internally connected to three terminals IN1, IN2, and OUT so as to realize an original function of the integrated circuit 10. When the test control signal TCTL specifies a test mode (TCTL = 1), a high impedance output is held between the internal logic 11 and the output terminal OUT, and the test control signal TCTL specifies a non-test mode. In this case (TCTL = 0), a tri-state buffer 12 for transmitting a signal from the internal logic 11 to the output terminal OUT is interposed. Although the number of signal terminals is three in the example of FIG. 1 for convenience of description, the number is not limited to three.
[0012]
The test circuit built in the integrated circuit 10 of FIG. 1 includes first and second D flip-flops 21 and 26, first, second and third tri-state buffers 22a, 22b and 22c, It has second and third exclusive OR gates 23a, 23b, 23c, one AND gate 24, and one selector 25.
[0013]
First D flip-flop 21 latches test data signal TDI in synchronization with the rising transition of first test clock signal TCK1, and distributes the latched signal to three tri-state buffers 22a, 22b, 22c. Input flip-flop. A common input signal of the three tristate buffers 22a, 22b, 22c is assumed to be DI.
[0014]
The first tristate buffer 22a sends the signal DOa to the first input terminal IN1, the second tristate buffer 22b sends the signal DOb to the second input terminal IN2, and the third tristate buffer 22c sends the signal DOb to the output terminal OUT. It outputs the signal DOc. When the test control signal TCTL specifies the test mode (TCTL = 1), the first tristate buffer 22a is connected to the first input terminal IN1, and the second tristate buffer 22b is connected to the second input terminal. Via IN2, the third tri-state buffer 22c supplies a small charging current to the stray capacitance C of the corresponding wiring on the PC board via the output terminal OUT. When the test control signal TCTL specifies the non-test mode (TCTL = 0), all three tristate buffers 22a, 22b, and 22c hold high impedance outputs. The first exclusive OR gate 23a outputs a pulse representing a time interval between the rising transition time of the input signal DI of the first tristate buffer 22a and the rising transition time of the output signal DOa of the first tristate buffer 22a. A logic signal XORa having a width is supplied. The second exclusive OR gate 23b outputs a pulse representing a time interval between the rising transition time of the input signal DI of the second tristate buffer 22b and the rising transition time of the output signal DOb of the second tristate buffer 22b. A logic signal XORb having a width is provided. The third exclusive OR gate 23c is a pulse representing a time interval between the rising transition time of the input signal DI of the third tri-state buffer 22c and the rising transition time of the output signal DOc of the third tri-state buffer 22c. A logic signal XORc having a width is provided.
[0015]
The AND gate 24 supplies a logical product signal AND of the three logic signals XORa, XORb, and XORc. The selector 25 outputs the logical product signal AND when the test control signal TCTL specifies the test mode (TCTL = 1), and outputs the first signal when the test control signal TCTL specifies the non-test mode (TCTL = 0). The output signal of the D flip-flop 21 is supplied to the second D flip-flop 26 as a data signal. The second D flip-flop 26 latches the data signal supplied from the selector 25 in synchronization with the rising transition of the second test clock signal TCK2, and outputs the latched signal as a test result signal TDO. Output flip-flop.
[0016]
FIG. 2 shows a test operation (TCTL = 1) of the integrated circuit 10. Here, it is assumed that the two input terminals IN1 and IN2 have no soldering defect and the output terminal OUT has an open defect soldering defect. When the first test clock signal TCK1 rises at the time T1 after setting the logical value of the test data input signal TDI to 1, the output signal of the first D flip-flop 21 changes from the logical value 0 to the logical value 1 Transition. That is, the common input signal DI of the three tri-state buffers 22a, 22b, 22c rises and transitions. Since the two input terminals IN1 and IN2 have no soldering defect, the first and second tristate buffers 22a and 22b respectively supply a small charging current to the stray capacitance C. The signal delay time in the first tri-state buffer 22a is the sum of the buffer-specific gate delay time Tg and the wiring delay time Tw that depends on the stray capacitance C of the wiring. The same applies to the second tri-state buffer 22b. On the other hand, since the output terminal OUT has an open defect soldering defect, the third tristate buffer 22c does not supply a charging current to the stray capacitance C. Therefore, the signal delay time in the third tri-state buffer 22c matches the gate delay time Tg unique to the buffer. That is, as shown in FIG. 2, after the output signal DOc of the third tri-state buffer 22c rises and transitions at time T2, the output signals DOa and DOb of the first and second tri-state buffers 22a and 22b change to the time T3. At the rising edge. As a result, the logic signals XORa and XORb supplied from the first and second exclusive OR gates 23a and 23b have a pulse width Tg + Tw, and the logic signal XORc supplied from the third exclusive OR gate 23c. Has a pulse width Tg. That is, the logical product signal AND supplied from the AND gate 24 has the pulse width Tg.
[0017]
The wiring delay time Tw is
Tw = C × Tc
Is represented by Here, Tc is a delay time per unit capacity, and is set to, for example, 10 ns / pF. In this case, even if the stray capacitance C is 1 pF, there is a time difference of 10 ns between the rising transition time T2 of the signal DOc and the rising transition time T3 of the signals DOa and DOb. Then, at time Tm between time T2 and time T3, the second test clock signal TCK2 rises. At the time Tm, the logical value of the logical product signal AND is already 0, so that the second D flip-flop 26 latches the logical value 0, and as a result, the test result signal TDO changes to the logical value 0 indicating “there is an open defect”. It becomes. This test result signal TDO is observed at time T4. If none of the two input terminals IN1 and IN2 and the one output terminal OUT has a soldering defect, the test at time T4 is performed as shown by an imaginary line (two-dot chain line) in FIG. The result signal TDO has the logical value 1 indicating "no open failure".
[0018]
As described above, according to the integrated circuit 10 of FIG. 1, only the test circuit built in the integrated circuit 10 determines whether there is a signal terminal having an open failure among the three signal terminals IN1, IN2, and OUT. Can be detected. That is, a so-called GO / NG test relating to a soldering defect of the integrated circuit 10 on the PC board can be easily realized.
[0019]
FIG. 3 shows an example of a PC board on which a plurality of circuit elements including four integrated circuits according to the present invention are mounted. The PC board 5 of FIG. 3 includes first, second, third, and fourth integrated circuits 10a, 10b, 10c, and 10d each having a built-in test circuit obtained by expanding the configuration of FIG. A transformer 16, a transistor group 17, a digital-to-analog converter (DAC) 18, and a light-emitting diode (LED) group 19 are mounted. Each of the four integrated circuits 10a, 10b, 10c, and 10d has six signal terminals and five test terminals TDI, TDO, TCTL, TCK1, and TCK2. The PC board 5 has seven signal terminals and five test terminals TDI, TDO, TCTL, TCK1, and TCK2. The test control signal TCTL, the first test clock signal TCK1, and the second test clock signal TCK2 respectively supplied to the PC board 5 from outside are supplied in parallel to each of the four integrated circuits 10a, 10b, 10c, 10d. Is done. When the test control signal TCTL specifies the non-test mode (TCTL = 0), the selector 25 (see FIG. 1) operates to connect the test data input terminal TDI of the PC board 5 to the test result as shown in FIG. A total of eight D flip-flops 21 and 26 incorporated in the four integrated circuits 10a, 10b, 10c and 10d are serially connected to the output terminal TDO. Each of the memory 15 and the DAC 18 is an integrated circuit having no built-in test circuit. The transformer 16, the transistor group 17, and the LED group 19 are all elements that cannot incorporate a test circuit.
[0020]
According to the PC board 5 of FIG. 3, the test data signal is applied to each of the four integrated circuits 10a, 10b, 10c, and 10d, and the test result of each of the four integrated circuits 10a, 10b, 10c, and 10d is provided. Observation of a signal is achieved by a scan operation (TCTL = 0) similar to the conventional BST technique. At this time, the same clock signal is externally supplied as the first test clock signal TCK1 and the second test clock signal TCK2. When a test control signal TCTL (TCTL = 1) designating a test mode is externally supplied to the PC board 5, the test control signal TCTL is based on the stray capacitance of each signal terminal of the four integrated circuits 10a, 10b, 10c and 10d. An open failure test is performed. Specifically, two signal terminals of the first integrated circuit 10a, two signal terminals of the third integrated circuit 10c, and two signal terminals of the fourth integrated circuit 10d are respectively connected via printed wiring. Although connected to the memory 15 and the memory 15 does not have a built-in test circuit, each of these signal terminals can detect an open defect. The other two signal terminals of the first integrated circuit 10a, the one signal terminal of the second integrated circuit 10b, and the other two signal terminals of the fourth integrated circuit 10d are respectively connected via printed wiring. Although open at the signal terminals of the PC board 5, open failure detection is possible for each. The other one signal terminal of the second integrated circuit 10b is connected to the transformer 16 via the printed wiring, and the other four signal terminals of the second integrated circuit 10b are each connected to the transistor group 17 via the printed wiring. The other four signal terminals of the third integrated circuit 10c are respectively connected to the respective anodes of the LED group 19 via printed wiring, and the transformer 16, the transistor group 17 and the LED group 19 Each of these elements cannot incorporate a test circuit, but each of these signal terminals can also detect an open defect. The other two signal terminals of the first integrated circuit 10a and the other two signal terminals of the fourth integrated circuit 10d are connected to each other via the printed wiring, respectively. It is possible. Therefore, according to the configuration of FIG. 3, the detection rate of soldering defects in the entire PC board 5 is greatly improved as compared with the case of the conventional BST technology.
[0021]
FIG. 4 shows another configuration example of the integrated circuit according to the present invention. The integrated circuit 30 of FIG. 4 includes first and second input terminals IN1 and IN2, one output terminal OUT, and four test terminals TDI, TDO, TCTL, and TCLK. When this integrated circuit 30 is mounted on a PC board, the three signal terminals IN1, IN2, and OUT are electrically connected to corresponding wirings on the PC board by soldering. C in FIG. 4 indicates the stray capacitance of each wiring. Reference numeral 31 denotes an internal logic (application logic) internally connected to three signal terminals IN1, IN2, and OUT so as to realize an original function of the integrated circuit 30. When the test control signal TCTL specifies the test mode (TCTL = 1), the high impedance output is held between the internal logic 31 and the output terminal OUT, and the test control signal TCTL specifies the non-test mode. In this case (TCTL = 0), a tri-state buffer 32 for transmitting a signal from the internal logic 31 to the output terminal OUT is interposed. In the example of FIG. 4, the number of signal terminals is set to three for convenience of explanation, but the number is not limited to three.
[0022]
The test circuit built in the integrated circuit 30 of FIG. 4 includes a first exclusive OR gate 41, a delay circuit 42, a first selector 42, and second, third, and fourth selectors 44a, 44b. , 44c, fifth, sixth, and seventh selectors 45a, 45b, 45c, first, second, and third D flip-flops 46a, 46b, 46c, and first, second, and third trios. State buffers 47a, 47b and 47c and second, third and fourth exclusive OR gates 48a, 48b and 48c are provided.
[0023]
The delay circuit 42 is a circuit for delaying the test clock signal TCLK supplied from the outside by a certain time ΔT. The first exclusive OR gate 41 supplies an exclusive OR signal of the test clock signal TCLK and the output signal of the delay circuit 42 as an internal clock signal XOR. When the test control signal TCTL specifies the test mode (TCTL = 1), the first selector 43 outputs the internal clock signal XOR supplied from the first exclusive OR gate 41, and sets the test control signal TCTL to the non- When the test mode is designated (TCTL = 0), an externally supplied test clock signal TCLK is supplied to three D flip-flops 46a, 46b and 46c, respectively.
[0024]
When the logic value of the test clock signal TCLK is 0, the second selector 44a selects the inverted output signal of the first D flip-flop 46a as a self-generated test data signal, and outputs the logic of the test clock signal TCLK. If the value is 1, the logic signal XORa supplied from the second exclusive OR gate 48a is selected. The fifth selector 45a specifies the signal selected by the second selector 44a when the test control signal TCTL specifies the test mode (TCTL = 1), and specifies the non-test mode when the test control signal TCTL specifies the non-test mode (TCTL = 1). At (TCTL = 0), the non-inverted output signal of the second D flip-flop 46b is supplied to the first D flip-flop 46a as a data signal. The first D flip-flop 46a latches the data signal supplied from the fifth selector 45a in synchronization with a rising transition of the clock signal supplied from the first selector 43, and latches the latched signal to the first signal. To the tri-state buffer 47a. The non-inverted output of the first D flip-flop 46a is connected to the test result output terminal TDO.
[0025]
When the logic value of the test clock signal TCLK is 0, the third selector 44b selects the inverted output signal of the second D flip-flop 46b as a self-generated test data signal, and outputs the logic value of the test clock signal TCLK. If the value is 1, the logic signal XORb supplied from the third exclusive OR gate 48b is selected. The sixth selector 45b specifies the signal selected by the third selector 44b when the test control signal TCTL specifies the test mode (TCTL = 1), and specifies the non-test mode when the test control signal TCTL specifies the non-test mode ( In (TCTL = 0), the non-inverted output signal of the third D flip-flop 46c is supplied to the second D flip-flop 46b as a data signal. The second D flip-flop 46b latches the data signal supplied from the sixth selector 45b in synchronization with the rising transition of the clock signal supplied from the first selector 43, and converts the latched signal to the second signal. To the tri-state buffer 47b.
[0026]
When the logical value of the test clock signal TCLK is 0, the fourth selector 44c selects the inverted output signal of the third D flip-flop 46c as a self-generated test data signal, and outputs the logical value of the test clock signal TCLK. When the value is 1, the logic signal XORc supplied from the fourth exclusive OR gate 48c is selected. The seventh selector 45c specifies the signal selected by the fourth selector 44c when the test control signal TCTL specifies the test mode (TCTL = 1), and specifies the non-test mode when the test control signal TCTL specifies the non-test mode (TCTL = 1). In (TCTL = 0), a signal supplied from the outside via the test data input terminal TDI is supplied to the third D flip-flop 46c as a data signal. The third D flip-flop 46c latches the data signal supplied from the seventh selector 45c in synchronization with the rising transition of the clock signal supplied from the first selector 43, and converts the latched signal to the third signal. To the tri-state buffer 47c.
[0027]
The first tristate buffer 47a sends the signal DOa to the first input terminal IN1, the second tristate buffer 47b sends the signal DOb to the second input terminal IN2, and the third tristate buffer 47c sends the signal DOb to the output terminal OUT. It outputs the signal DOc. When the test control signal TCTL specifies the test mode (TCTL = 1), the first tristate buffer 47a is connected to the first input terminal IN1, and the second tristate buffer 47b is connected to the second input terminal. Via IN2, the third tri-state buffer 47c supplies a small charging current to the stray capacitance C of the corresponding wiring on the PC board via the output terminal OUT. When the test control signal TCTL specifies the non-test mode (TCTL = 0), all three tri-state buffers 47a, 47b, 47c hold high impedance outputs. The second exclusive OR gate 48a generates a pulse representing a time interval between the rising transition time of the input signal DIa of the first tristate buffer 47a and the rising transition time of the output signal DOa of the first tristate buffer 47a. A logic signal XORa having a width is supplied. The third exclusive OR gate 48b outputs a pulse representing a time interval between the rising transition time of the input signal DIb of the second tristate buffer 47b and the rising transition time of the output signal DOb of the second tristate buffer 47b. A logic signal XORb having a width is provided. The fourth exclusive OR gate 48c provides a pulse representing a time interval between the rising transition time of the input signal DIc of the third tristate buffer 47c and the rising transition time of the output signal DOc of the third tristate buffer 47c. A logic signal XORc having a width is provided.
[0028]
According to the integrated circuit 30 of FIG. 4, the test data signal is applied to each of the three D flip-flops 46a, 46b, and 46c, and the test data signal is latched by each of the three D flip-flops 46a, 46b, and 46c. Observation of the test result signal is achieved by the same scan operation (TCTL = 0) as in the conventional BST technique. More specifically, when the test control signal TCTL specifies the non-test mode (TCTL = 0), the seventh selector 45c, the third D flip-flop 46c, the sixth selector A scan path is formed to the test result output terminal TDO via the second D flip-flop 46b, the fifth selector 45a, and the first D flip-flop 46a. Further, an externally supplied test clock signal TCLK is supplied to each of the three D flip-flops 46a, 46b, 46c as a clock signal for data shift.
[0029]
FIG. 5 shows a test operation (TCTL = 1) of the integrated circuit 30. Here, it is assumed that the two input terminals IN1 and IN2 have no soldering defect and the output terminal OUT has an open defect soldering defect. The non-inverted output signals of each of the three D flip-flops 46a, 46b, 46c are all set to a logical value 0 in advance by a scan operation (TCTL = 0). Therefore, while the logic value of the test clock signal TCLK is 0, the inverted output signals of the three D flip-flops 46a, 46b, 46c are used as self-generated test data signals each having a logic value of 1. It is supplied to each of the three D flip-flops 46a, 46b, 46c.
[0030]
The first exclusive OR gate 41 and the delay circuit 42 generate the internal clock signal XOR from the test clock signal TCLK. As shown in FIG. 5, the generated internal clock signal XOR includes a pulse P1 having a width ΔT starting from the rising transition time of the test clock signal TCLK and a pulse P2 having a width ΔT starting from the falling transition time of the test clock signal TCLK. Have
[0031]
When the test clock signal TCLK rises at time T1, the non-inverted output signals of each of the three D flip-flops 46a, 46b, and 46c are all synchronized with the rising transition of the pulse P1 of the internal clock signal XOR. Transition from value 0 to logical value 1. That is, the input signals DIa, DIb, DIc of the three tristate buffers 47a, 47b, 47c all rise and transition. Since the two input terminals IN1 and IN2 have no soldering defect, the first and second tristate buffers 47a and 47b respectively supply a small charging current to the stray capacitance C. The signal delay time in the first tri-state buffer 47a is the sum of the gate delay time Tg unique to the buffer and the wiring delay time Tw that depends on the stray capacitance C of the wiring. The same applies to the second tri-state buffer 47b. On the other hand, since the output terminal OUT has an open defect soldering defect, the third tristate buffer 47c does not supply a charging current to the stray capacitance C. Therefore, the signal delay time in the third tri-state buffer 47c matches the buffer-specific gate delay time Tg. That is, as shown in FIG. 5, after the output signal DOc of the third tristate buffer 47c rises and transitions, the output signals DOa and DOb of the first and second tristate buffers 47a and 47b rise and transition. Become. As a result, the logic signals XORa and XORb supplied from the first and second exclusive OR gates 48a and 48b have a pulse width Tg + Tw, and the logic signal XORc supplied from the third exclusive OR gate 48c. Has a pulse width Tg.
[0032]
When the test clock signal TCLK falls after the time ΔT1 has elapsed from the time T1, the three logic signals XORa, XORb, and XORc are each D flip-flop 46a in synchronization with the rising transition of the pulse P2 of the internal clock signal XOR. , 46b, 46c. Here, Tg <ΔT1 <Tg + Tw. Therefore, the signal DIa has a logical value 1 indicating "no open defect", the signal DIb has a logical value 1 indicating "no open defect", and the signal DIc has a logical value 0 indicating "open defect". These signals DIa, DIb, DIc are observed via a test result output terminal TDO by a scan operation (TCTL = 0). As shown in FIG. 5, when the test clock signal TCLK rises again at the time T2 and further falls when the time ΔT2 elapses, the logical values of the signals DIa, DIb, and DIc become All return to 0. Here, Tg + Tw <ΔT2.
[0033]
As described above, according to the integrated circuit 30 of FIG. 4, the signal terminal having the open failure among the three signal terminals IN1, IN2, and OUT can be specified only by the test circuit built in the integrated circuit 30. Therefore, there is an advantage that repair of an open defective portion can be easily performed. Moreover, each of the three D flip-flops 46a, 46b, 46c has a function of an input flip-flop for inputting a test data signal and a function of an output flip-flop for outputting a test result signal. Therefore, the scale of the test circuit is reduced. Further, the first exclusive OR gate 41 and the delay circuit 42 generate an internal clock signal XOR having a pulse P1 for latching a test data signal and a pulse P2 for latching a test result signal. Therefore, there is an advantage that only one test clock signal TCLK needs to be supplied from outside.
[0034]
In the examples shown in FIGS. 1 and 4, the application of the test data signal and the observation of the test result signal are achieved by the same scanning operation as the conventional BST technique, but the present invention is not limited to this. Further, the present invention is applicable not only to digital integrated circuits but also to analog integrated circuits.
[0035]
【The invention's effect】
As described above, according to the present invention, the difference in load capacity between when the signal terminal of the integrated circuit is normally electrically connected to the printed wiring on the PC board and when the signal terminal is not electrically connected is determined according to the present invention. Since the open defect of the signal terminal is detected, it is possible to detect the open defect regardless of what element the integrated circuit is connected to on the PC board. Therefore, an effect of achieving a high detection rate of soldering defects in the entire PC board can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration example of an integrated circuit according to the present invention.
FIG. 2 is a timing chart illustrating a test operation of the integrated circuit of FIG. 1;
FIG. 3 is a block diagram showing an example of a PC board on which a plurality of circuit elements including four integrated circuits each including a test circuit obtained by expanding the configuration in FIG. 1 are mounted.
FIG. 4 is a circuit diagram showing another configuration example of the integrated circuit according to the present invention.
FIG. 5 is a timing chart showing a test operation of the integrated circuit of FIG. 4;
[Explanation of symbols]
5 PC board (printed circuit board)
10 Integrated circuits
10a, 10b, 10c, 10d integrated circuits
11 Internal logic (internal circuit means)
12 Tri-state buffer
21 D flip-flop (input flip-flop)
22a, 22b, 22c Tri-state buffer
23a, 23b, 23c Exclusive OR gate (logic gate)
24 AND gate
25 Selector
26 D flip-flop (output flop flop)
30 Integrated Circuit
31 Internal logic (internal circuit means)
32 tristate buffer
41 Exclusive OR Gate
42 delay circuit
43 Selector
44a, 44b, 44c Selector
45a, 45b, 45c selector
46a, 46b, 46c D flip-flop (input flip-flop, output flip-flop)
47a, 47b, 47c Tri-state buffers
48a, 48b, 48c Exclusive OR gate (logic gate)
AND AND signal
C Stray capacitance of PC board wiring
DI tristate buffer input signal
DIa, DIb, DIc Tri-state buffer input signal
DOa, DOb, DOc Tri-state buffer output signal
IN1, IN2 input terminal (signal terminal)
OUT output terminal (signal terminal)
TCK1, TCK2 test clock signal
TCLK test clock signal
TCTL test control signal
TDI test data signal
TDO test result signal
XOR internal clock signal
XORa, XORb, XORc logic signal

Claims (18)

An integrated circuit mounted on a printed circuit board,
A plurality of signal terminals for electrical connection to wiring on the printed circuit board,
First circuit means for charging stray capacitance of a corresponding wiring on the printed circuit board via each of the plurality of signal terminals;
Second circuit means for checking whether or not the plurality of signal terminals are normally electrically connected to wiring on the printed circuit board based on a difference in stray capacitance charged by the first circuit means. An integrated circuit, characterized in that: The integrated circuit according to claim 1,
When the test control signal supplied from the outside designates a test mode, the first circuit means includes a corresponding wiring on the printed circuit board via a corresponding one of the plurality of signal terminals. A plurality of tri-state buffers for supplying a charging current to a stray capacitance of the semiconductor device and for holding a high impedance output when the test control signal specifies a non-test mode. circuit. The integrated circuit according to claim 1,
Internal circuit means internally connected to the plurality of signal terminals so as to realize an original function of the integrated circuit;
Interposed between the internal circuit means and an output terminal of the plurality of signal terminals, holding a high impedance output when a test control signal supplied from the outside designates a test mode; An integrated circuit, further comprising: a tri-state buffer for transmitting a signal from the internal circuit means to the output terminal when the control signal specifies a non-test mode. The integrated circuit according to claim 1,
The second circuit means includes means for detecting a soldering defect such as an open defect in one of the plurality of signal terminals from a difference in time required for charging the stray capacitance. An integrated circuit characterized by the above. The integrated circuit according to claim 1,
The integrated circuit according to claim 2, wherein said second circuit means includes means for outputting a signal indicating whether a signal terminal having an open defect soldering defect exists in said plurality of signal terminals. . The integrated circuit according to claim 1,
The integrated circuit according to claim 2, wherein said second circuit means includes means for outputting a signal for specifying a signal terminal having an open defect soldering defect among said plurality of signal terminals. The integrated circuit according to claim 2,
An integrated circuit, further comprising: an input flip-flop for latching a test data signal and distributing the latched test data signal to each of the plurality of tri-state buffers. The integrated circuit according to claim 2,
A plurality of input flip-flops for respectively latching the test data signal and supplying the latched test data signal to a corresponding one of the plurality of tri-state buffers. Integrated circuit. The integrated circuit according to claim 2,
The second circuit means outputs a logic signal having a pulse width representing a time interval between an input transition time of a corresponding tri-state buffer of the plurality of tri-state buffers and an output transition time of the tri-state buffer. An integrated circuit comprising a plurality of logic gates for supplying. The integrated circuit according to claim 9,
The second circuit means includes:
An AND gate for supplying an AND signal of logic signals supplied from each of the plurality of logic gates;
An integrated circuit, further comprising: an output flip-flop for latching the logical product signal supplied from the AND gate and outputting the latched logical product signal to the outside. The integrated circuit according to claim 9,
The second circuit means includes a plurality of output flip-flops each for latching a logic signal supplied from a corresponding one of the plurality of logic gates, and outputting each of the latched logic signals to the outside. An integrated circuit, further comprising: An integrated circuit mounted on a printed circuit board,
A plurality of signal terminals for electrical connection to wiring on the printed circuit board,
When the test control signal supplied from the outside specifies the test mode, the charging current is supplied to the stray capacitance of the corresponding wiring on the printed circuit board via the corresponding signal terminal of each of the plurality of signal terminals. A plurality of tri-state buffers for supplying, and each holding a high impedance output when the test control signal specifies a non-test mode;
An input flip-flop for latching a test data signal in synchronization with a first test clock signal and distributing the latched test data signal to each of the plurality of tri-state buffers;
A plurality of logic gates each for supplying a logic signal having a pulse width representing a time interval between an input transition time of a corresponding one of the plurality of tri-state buffers and an output transition time of the tri-state buffer; When,
An AND gate for supplying an AND signal of logic signals supplied from each of the plurality of logic gates;
An output flip-flop for latching the AND signal supplied from the AND gate in synchronization with a second test clock signal, and outputting the latched AND signal to the outside. Integrated circuit. The integrated circuit according to claim 12,
Internal circuit means internally connected to the plurality of signal terminals so as to realize an original function of the integrated circuit;
Interposed between the internal circuit means and an output terminal of the plurality of signal terminals, retains a high impedance output when the test control signal specifies a test mode, and causes the test control signal to be non-conductive. An integrated circuit, further comprising: a tri-state buffer for transmitting a signal from the internal circuit means to the output terminal when a test mode is designated. The integrated circuit according to claim 12,
An integrated circuit, further comprising circuit means for serially connecting the input flip-flop and the output flip-flop when the test control signal specifies a non-test mode. An integrated circuit mounted on a printed circuit board,
A plurality of signal terminals for electrical connection to wiring on the printed circuit board,
When the test control signal supplied from the outside specifies the test mode, the charging current is supplied to the stray capacitance of the corresponding wiring on the printed circuit board via the corresponding signal terminal of each of the plurality of signal terminals. A plurality of tri-state buffers for supplying, and each holding a high impedance output when the test control signal specifies a non-test mode;
A plurality of logic gates each for supplying a logic signal having a pulse width representing a time interval between an input transition time of a corresponding one of the plurality of tri-state buffers and an output transition time of the tri-state buffer; When,
A delay circuit for delaying an externally supplied test clock signal;
An exclusive OR gate for supplying an exclusive OR signal of the test clock signal and the output signal of the delay circuit as an internal clock signal;
A plurality of logic signals for selecting one of a logic signal supplied from a corresponding one of the plurality of logic gates and a self-generated test data signal according to a logic value of the test clock signal. A selector,
Each of the plurality of selectors latches a signal selected by a corresponding one of the plurality of selectors in synchronization with an internal clock signal supplied from the exclusive OR gate, and latches the latched signal in the plurality of tristate buffers. An integrated circuit comprising: a plurality of flip-flops for supplying a corresponding tri-state buffer. The integrated circuit according to claim 15,
Internal circuit means internally connected to the plurality of signal terminals so as to realize an original function of the integrated circuit;
Interposed between the internal circuit means and an output terminal of the plurality of signal terminals, retains a high impedance output when the test control signal specifies a test mode, and causes the test control signal to be non-conductive. An integrated circuit, further comprising: a tri-state buffer for transmitting a signal from the internal circuit means to the output terminal when a test mode is designated. The integrated circuit according to claim 15,
The integrated circuit according to claim 1, wherein each of the plurality of flip-flops further has a function of supplying an inverted signal of the latched signal to the corresponding one of the plurality of selectors as the self-generated test data signal. . The integrated circuit according to claim 15,
An integrated circuit, further comprising circuit means for serially connecting the plurality of flip-flops to each other when the test control signal specifies a non-test mode.

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