JP3540577B2 - FM multiplex broadcast receiving device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an FM multiplex broadcast receiving apparatus for receiving an FM multiplex broadcast in which data is multiplexed on an FM broadcast, and more particularly to a frame synchronization scheme selection control.
[0002]
[Prior art]
Generally, FM multiplex broadcasting is performed in which text information and the like are multiplexed and broadcast on FM broadcasting. In this FM multiplex broadcasting, text broadcasting is encoded and multiplexed with FM stereo broadcasting. Currently, programs such as news and traffic information are broadcast.
Currently, the main broadcast (commercial broadcast) of FM multiplex broadcasting is performed in Japan. According to this FM multiplexing, the frame configuration of the multiplexed data is a frame of 288 × 272 bits as shown in FIG. 13, and basically, one block of one frame (one row in one frame) is a block identification of 16 bits. A code consisting of a 176-bit data packet and a 96-bit error correction code (14-bit CRC, 82-bit horizontal parity), a 16-bit BIC and a 272-bit error correction code (vertical parity) ). This frame configuration is defined as “method B” according to the recommendation of the International Telecommunication Union (ITU), and in addition to “method B” in the ITU recommendation, “method A” having a different frame configuration from “method B” , “Method A ′” and “method C” are defined. Therefore, in FM multiplex broadcasting, four types of frame configurations have become international standards. Currently, in the European Standard for SWIFT (System for Wireless Infotainment Forwarding and Teledistribution) (final draft), the above-mentioned “method A”, “method A ′”, “method B” and “method C” are each “method C”. A0, "method A1,""methodB," and "method C" are stations on the same network as the current receiving station, such as those used in the European Radio Data System (RDS). The data of a frequency list of a broadcasting station that broadcasts the same program as that of the receiving station (alternative frequency list, hereinafter referred to as AF list) and the data of the frame configuration of the current broadcasting station (hereinafter, frame type data FT) are converted into multiplexed data. It has also been proposed to include it.
[0003]
The frame configurations of “method A”, “method A ′”, and “method C” are as shown in FIGS. 11, 12, and 14, respectively. The frame configuration of “method A” is a 288 × 272 bit frame, and one block configuration is the same as that of “method B”. However, a block including a data packet and a block including only an error correction code are distinguished. Are located. Further, the frame configuration of “method A ′” is configured by inserting “REAL TIME INFORMATION BLOCK” of 12 blocks into a portion including only the error correction code of “method A”. Further, the frame structure of “method C” is constituted only by blocks including a 288-bit data packet.
[0004]
[Problems to be solved by the invention]
At present, FM multiplex broadcasting is performed only in Japan, but there are plans for FM multiplex broadcasting in Europe and the United States in the future. In particular, in Europe, FM multiplex broadcasting services based on the Japanese system in a broad sense will be provided in the future, but the frame configuration of FM multiplex broadcasting in Europe differs from the frame configuration used in Japan by four It is a direction in which different frame configurations are adopted. However, in Europe, even if FM multiplex broadcasting is adopted in each region and the broadcasting is performed, there is a good possibility that the frame configuration differs for each country or region. May be different. Therefore, when the receiving station is changed, it is required to quickly obtain the FM multiplex data following the change.
[0005]
Therefore, an object of the present invention is to provide an FM multiplex broadcast reception control device capable of performing quick and accurate frame synchronization when a receiving station is changed.
[0006]
[Means for Solving the Problems]
The present invention relates to an FM multiplex receiving apparatus for demodulating multiplexed data from FM multiplex broadcasting, comprising a plurality of frame synchronizing means, and performing frame synchronization of the multiplexed data by one of the plurality of frame synchronizing means. A control circuit including a frame synchronization circuit, first detection means for detecting frame type data included in the multiplexed data, and switching means for switching the plurality of frame synchronization means in accordance with an output signal of the first detection means; It is characterized by having.
[0007]
Further, the control circuit includes a second detection unit that sequentially switches the plurality of frame synchronization units, and detects that the frame synchronization is established by the switched frame synchronization unit, and the first detection unit or the second detection unit. (2) selecting the frame synchronization means based on the detection result of the detection means.
The control circuit selects the frame synchronization unit according to a result of the first and second detection units that is detected earlier.
[0008]
Further, the control circuit includes a comparing means for comparing the detection results of the first and second detection means, and when both the detection results match, selects the frame synchronization means based on the matching detection result. I do.
The control circuit operates the first detection unit and / or the second detection unit again when the two detection results do not match.
[0009]
Furthermore, the control circuit is characterized in that when the two detection results do not match, the control circuit selects a detection result with a higher priority from both the detection results.
7. The FM multiplex broadcast receiving apparatus according to claim 6, wherein the priority of the detection result of the second detecting means is made higher.
In addition, priorities are assigned to the plurality of frame synchronization units, and one of the plurality of frame synchronization units is selected by a frame synchronization unit having a higher priority among the detection results of the first and second detection units. The receiving device for FM multiplex broadcasting according to claim 6, wherein:
[0010]
According to the present invention, the frame configuration of the current broadcasting station is detected based on the frame type data included in the multiplexed data, and one of the plurality of frame synchronization units in the frame synchronization circuit is sent to the frame synchronization unit in accordance with the detection result. Switch. Further, a plurality of frame synchronization means are sequentially switched, and each time the switching is performed, it is detected whether the frame synchronization means has synchronized with the frame configuration in the received FM multiplex broadcast. A plurality of frame synchronization units are switched based on the synchronization unit.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit showing an embodiment of the present invention. 101 is a front end for FM tuning that outputs an IF signal, 102 is an FM demodulation circuit that demodulates the IF signal into an FM composite signal, 103 is an MPX (multiplex) circuit that demodulates the composite signal into a stereo signal, and 104 is a stereo signal. An AF amplifier circuit for amplifying the signal and outputting it to the speaker 105; 106, a PLL frequency synthesizer circuit for determining the tuning frequency of the FM tuning front-end circuit 101; 107, a block for demodulating FM multiplexed data; , 109 is an L-MSK demodulation circuit for demodulating multiplexed data, 110 is a block synchronization circuit for performing block synchronization of demodulated multiplexed data, and 111 is a frame of block data having four frame synchronization methods. Frame synchronization circuit for synchronizing, 11 Is an error correction circuit that performs error correction on the reconstructed data of the frame, and 113 is the data data1 that has been corrected in the horizontal direction by one block of data and the data of one frame, according to the output of the error correction circuit 112. This is a data output circuit that selectively outputs data data2 that has also been subjected to vertical error correction.
[0012]
Reference numeral 114 denotes a means for controlling the PLL frequency synthesizer circuit 106 with the operation keys 117 to change the tuning frequency, a means for decoding multiplexed data and displaying the decoding result on the display 116, and a means 114 for controlling the frame synchronization circuit 111. The control circuit includes a frame selection circuit 115 that outputs a switching signal Fmethod for switching a frame synchronization method.
[0013]
In FIG. 1, a received RF signal is frequency-converted into an IF signal of a predetermined frequency by a local oscillation signal generated in an FM front end 101, and the IF signal is demodulated by an FM demodulation circuit 102 into a composite signal. The audio signal component of the composite signal is stereo-demodulated by the MPX circuit 103 into left and right stereo signals. The left and right stereo signals are amplified by the AF amplifier circuit 104 and then transmitted to the speaker 105.
[0014]
The FM multiplex component in the composite signal passes through the BPF 108 and is demodulated into multiplexed data by the L-MSK demodulation circuit 109. After the multiplexed data is synchronized for each block by the block synchronization circuit 110, the multiplexed data is synchronized for each frame by the frame synchronization circuit 111, and the multiplexed data for which the block and frame are synchronized is corrected by the error correction circuit 112. The error is corrected. The error corrected data DATA is decoded by the control circuit 113, and character information and graphic information are displayed on the display 116 based on the decoded data.
[0015]
The FM front end 101 includes a local oscillation circuit (not shown). The frequency of the local oscillation signal is changed by a frequency control signal from the PLL synthesizer 106, and the local oscillation signal is output to the PLL frequency synthesizer 106. The local oscillation circuit forms a PLL together with the PLL frequency synthesizer 106. The PLL synthesizer 106 includes a reference oscillation circuit that generates a reference signal, a reference divider that divides the reference signal, and a variable frequency divider that divides the local oscillation signal. , A phase divider that compares the outputs of the two dividers, and a loop filter that outputs a frequency control signal according to the output of the phase comparator. Since the PLL is a well-known technique, the description of the operation is omitted.
[0016]
When a broadcast station set by the operation key 117 is to be received, first, frequency-divided data Ndata corresponding to the reception frequency of this broadcast station is output from the control circuit 114. The variable frequency division number of the programmable divider is set according to the frequency division data Ndata, and the frequency of the local oscillation signal is a frequency corresponding to the broadcast station. As a result, the received RF signal of the broadcast station is converted into an IF signal of a predetermined frequency, and audio demodulation and multiplex demodulation of the broadcast station are performed. Thus, the control circuit 114 controls the tuning operation of the front end 101.
[0017]
Incidentally, the frame selection circuit 115 is configured as shown in FIG. After capturing the lock signal Block indicating that the block synchronization circuit 110 has performed block synchronization, the first frame detection means 301 detects the frame type data FT1 included in the data data1 as shown in FIG. Outputs flag FG1 when detection is completed. The frame type data FT is composed of 2 bits, and the type of frame configuration can be detected by the combination of data. Therefore, the first frame detecting means 301 detects the combination of data and generates the frame type data FT2 according to the combination. appear. Further, the second frame detecting means 302 outputs the switching signal Fmethod for changing the frame synchronizing means of the frame synchronizing circuit 111 while changing the 2-bit frame type so as to sequentially change the frame switching means. A lock signal Flock indicating that synchronization has been detected is detected, and a 2-bit frame type FT2 as shown in FIG. 5 and a flag FG2 indicating detection completion are output according to the output of the lock signal Flock. The frame setting means comprises frame setting means 303 for outputting a switching signal Fmethod in accordance with the data FT1 and FT2 and the flags FG1 and FG2.
[0018]
Next, the automatic switching operation of the frame synchronization system of the radio receiver of FIG. 1 will be described based on the flowchart of FIG.
First, the operation key 117 is operated so as to be a desired receiving station, the frequency division data Ndata is changed and output from the control circuit 114, and the local oscillation signal of the front end 101 is changed, thereby changing the receiving station. Is performed (S1). Then, the frame setting means 303 detects whether or not the flags FG1 and FG2 from the first and second frame selecting means 301 and 302 are present (S2). However, since the demodulation of the multiplexed data and the detection of the frame data are not completed immediately after the change of the receiving station, the flags FG1 and FG2 are not output. Therefore, the operation shifts to the operation for detecting the changed frame type of the receiving station.
[0019]
The detection of the frame type (S3 and S4) is performed simultaneously and in parallel by the first and second frame detection means 301 and 302. First, the frame detection by the first frame detecting means 301 in S3 will be described with reference to the flowchart of FIG. The first frame detection means 301 detects whether or not the lock signal Block of the block synchronization circuit 110 has been input. That is, it is confirmed whether or not the block synchronization of the block synchronization circuit 110 has been achieved (S21). Until block synchronization is confirmed, the first frame detection means 301 is in a standby state. When the block synchronization is confirmed, the first frame detecting means 301 decodes the data data1 output from the data output circuit 113, and further detects the frame type data FT included in the data data1 (S22). Subsequently, it is confirmed whether or not there is data FT (S23). If the data FT1 cannot be confirmed, the process returns to S22, where the block data data1 is decoded again to confirm the existence of the data FT1. If there is data FT1, the flowchart of FIG. 4 ends. Then, returning to FIG. 3, the first frame detecting means 301 sets the flag FG1 to a state "1" indicating that the detection of the frame type data has been completed (S5).
[0020]
On the other hand, the frame detection by the second frame detecting means 302 will be described with reference to the flowchart of FIG. The second frame detecting means 302 sets the frame type FT2, and the Fmethod corresponding thereto is output from the frame setting means 303. The frame synchronization means of the frame synchronization circuit 111 is switched by Fmethod. The change of the frame type is performed in the order of, for example, “method A0” → “method A1” → “method B” → “method C” → “method A0”. Therefore, first, the frame synchronization means of the frame synchronization circuit 111 is set to "method A0" (S24). After that, the second frame detecting means 302 checks whether or not frame synchronization has been achieved by the set frame synchronizing means. This confirmation is confirmed by the lock signal Flock output when the frame synchronization circuit 111 enters the frame synchronization (S25).
[0021]
If the frame synchronization circuit 111 cannot synchronize with “method A0” in S25, the second frame detection unit 302 changes the frame type FT2 and changes the frame synchronization unit to “method A1” (S26). If the set frame synchronization means does not achieve frame synchronization, the second frame detection means 302 sequentially changes the frame synchronization means of "method A0" to "method C". In step S25, if there is a frame synchronization method that achieves frame synchronization, the frame type FT2 that can perform frame synchronization is stored in an internal memory (not shown) in the second frame detection means 302. Thereafter, the flowchart of FIG. 5 ends, and the process returns to FIG. 3, and the second frame detecting means 302 sets the flag FG2 to a state "1" indicating that the detection of the frame type FT2 has been completed (S6).
[0022]
When the state of “1” indicating detection completion is set in the flag FG1 or the flag FG2, the frame setting unit 303 determines that the flag is present (S2), and further determines whether the flag FG1 is in the state of “1”. (S7). When the flag FG1 is “1”, the frame setting means 303 outputs a signal Fmethod based on the frame type data FT1 of the first frame detecting means 301. In accordance with Fmethod, the synchronization detecting means of the frame synchronization circuit 111 switches to the frame synchronization means based on the frame type data included in the multiplexed data (S8). If the flag FG1 is not “1”, the frame setting means 303 outputs the signal Fmethod based on the frame type FT2 of the second frame detecting means 302 because the flag FG2 is “1”. In accordance with Fmethod, the frame synchronization unit of the frame synchronization circuit 111 switches to a frame synchronization unit that can actually synchronize.
[0023]
Therefore, in the flowchart of FIG. 3, the frame synchronization unit switches according to the result of early detection of the first and second frame detection units.
FIG. 6 is a flowchart for explaining another embodiment of the present invention. After the change of the receiving station (S1), the frame type is detected by the first and second frame detecting means 301 and 202 according to the flowcharts of FIGS. 4 and 5, respectively (S3, S4). When the detection is completed, the flags FG1 and FG2 are set. It is set to a state indicating that (S5, S6).
[0024]
Thereafter, when the flag FG1 becomes "1" in S5, the frame setting means 303 determines that the flag FG2 becomes "1" (S31), and the flag FG2 becomes "1" in S6. Then, it is determined that the flag FG1 becomes "1" (S32). When it is confirmed that both the flags FG1 and FG2 are "1", the frame setting means 303 determines whether or not the frame type FT1 and the frame type FT2 match (S33). If the frame types FT1 and FT2 do not match, the process returns to S3 and S4 to detect the frame type again. If they match, the frame setting means 303 outputs a switching signal Fmethod based on the matched frame type, and the frame synchronization means of the frame synchronization circuit 111 switches according to Fmethod (S35).
[0025]
FIG. 7 is a flowchart for explaining another embodiment. The operation when the detected frame types FT1 and FT2 do not match differs from the flowchart of FIG. If the frame types FT1 and FT2 detected by the first and second frame detection units 301 and 302 do not match, the frame setting unit 303 gives priority to the frame type FT2 and outputs a switching signal Fmethod based on the frame type FT2. In accordance with Fmethod, the frame synchronization unit of the frame synchronization circuit 111 switches to a frame synchronization unit that can actually synchronize (S35).
[0026]
In the flowchart of FIG. 7, the frame type FT2 is prioritized when the detected frame types do not match. However, the frame type FT1 may be prioritized and the frame synchronization means may be switched. In addition, when the detected frame types do not match, one of the frame types FT1 and FT2 is prioritized. However, each frame type “method A0” to “method C” is prioritized, and the detected frame type itself is used. And the frame synchronization means can be switched according to the frame type having the higher priority.
[0027]
FIG. 8 shows another configuration example of the frame selection circuit 115, which includes only the first frame detection means 301. The operation of FIG. 8 will be described with reference to the flowchart of FIG. When the receiving station is changed (S1), the frame type data FT1 is detected from the multiplexed data according to the flowchart of FIG. 4 (S3). The frame setting means 303 outputs the switching signal Fmethod based on the frame type FT1, and the frame synchronization means of the frame synchronization circuit 111 switches to the frame synchronization means according to the frame type data according to Fmethod.
[0028]
FIG. 10 is a block diagram illustrating a specific circuit example of the block synchronization circuit 110, the frame synchronization circuit 111, the error correction circuit 112, and the data output circuit 113 of FIG. Reference numeral 201 denotes a BIC detection circuit that detects a BIC included in the multiplexed data, 202 denotes a change point detection circuit that detects a change point of the detected BIC, and 203 denotes the number of data of the multiplexed data is 288, which is the number of data in one block. A data counter that counts and outputs a completion signal when the counting is completed, 204 is a block counter that counts the number of blocks by counting the completion signal, 205 detects a predetermined change point in the frame configuration, and The frame synchronization detecting circuit 206 detects frame synchronization by detecting the number of blocks between predetermined change points based on the count value of the frame, and resets the block counter 204 when the last block synchronized with the frame is detected. Data counter 203 completes at 288 count cycle. Signal detecting or BIC is input each time is input, if it finds a predetermined number blocks fraction BIC, a block synchronous circuit for outputting a block synchronization detection signal Block indicating that the block synchronization.
[0029]
A frame memory 207 includes a write / read address generation circuit for writing and reading multiplexed data at a specified write / read address, and a frame memory 208 sets a head flag at the head of a frame according to a frame synchronization detection signal Flock. 209 is a timing circuit for storing multiplexed data in the memory 207, 209 is a block data buffer for temporarily storing the multiplexed data in the frame memory 207, and 210 is a block data buffer for temporarily storing one block of data in the data buffer 209. An error correction circuit that corrects an error by parity and corrects one frame of data in the memory 207 by vertical parity. 211 selectively outputs the output data d1 of the block data buffer 209 and the output data d2 of the frame memory 207. It is a data output unit that performs
[0030]
For example, when the frame configuration of the multiplexed data is the frame configuration “method B” in FIG. 11, the frame detection circuit 205 determines predetermined detection points, that is, “BIC1 → BIC3”, “BIC4 → BIC2”, “BIC2 → BIC3”, “ It detects that the change points of "BIC4 → BIC1" and "BIC1 → BIC3" are repeated in order, and detects that the number of blocks between the respective change points becomes 123, 13, 123 and 13 Then, the frame synchronization is detected, and when the frame synchronization is detected, the frame synchronization detection signal Flock is output. Further, Fmethod is applied to the frame synchronization detecting circuit 205, and the frame synchronization means is switched by this Fmethod. Specifically, by changing Fmethod according to the frame configuration, the configuration of the frame detection circuit changes, as a result, a predetermined change point to be detected is changed, and the order of the repeated change points is changed. . Furthermore, the number to be counted between transition points is changed.
[0031]
That is, when the frame configuration is “method A0”, the frame detection circuit 205 determines the changing points of “BIC3 → BIC2”, “BIC2 → BIC1”, “BIC1 → BIC4”, “BIC4 → BIC3”, and “BIC3 → BIC2”. Upon detection, the number of blocks between them is changed to 70, 60, 82, and 60. When the frame configuration is `` method A1, '' the frame detection circuit 205 determines the changing points of `` BIC3 → BIC2, '' `` BIC2 → BIC1, '' `` BIC1 → BIC4, '' `` BIC4 → BIC3, '' and `` BIC3 → BIC2. '' At the same time, it is changed to detect that the number of blocks between them is 70, 60, 94, and 60. Further, in the case of “method C”, the value is changed so that “BIC3 → BIC3” is detected for each block. As described above, by changing the F method, it becomes possible to change the frame synchronization means corresponding to the frame configuration of the multiplexed data.
[0032]
The block-synchronized multiplexed data is temporarily stored in the data buffer 209 at the timing when the detection signal Block is output, and error correction is performed for each block by the horizontal parity included in the data as shown in FIG. When the error in the multiplexed data can be corrected by the error correction of the horizontal parity, the error corrected data d1 is output from the data buffer 209 and transmitted to the control circuit 114 via the data output unit 211. Therefore, if block synchronization of multiplexed data is established, correct data can be sent to the control circuit 114 for each block. Therefore, in FIG. 1, it is possible to decode and detect the frame type data FT1 based on the data d1 even if the frame synchronization means of the frame synchronization circuit 111 is not set correctly.
[0033]
If the block data cannot be corrected, the data for one frame including the block is stored in the frame memory 207, and the error is corrected by the vertical parity included in the data as shown in FIG. If the error in the multiplexed data that could not be corrected by the horizontal parity can be corrected by the error correction of the vertical parity, the error corrected data d2 is transmitted from the frame memory 207 to the control circuit 114 via the data output unit 211. You. In this case, error correction cannot be performed unless the frame synchronization of the multiplexed data is established.
[0034]
【The invention's effect】
According to the present invention, the frame type of the current broadcasting station is detected based on the frame type data included in the multiplexed data, the plurality of frame synchronization units are sequentially switched, and a frame type capable of performing frame synchronization is detected. Since the frame synchronization means is switched based on the two frame types, quick and accurate frame synchronization can be achieved.
[0035]
Further, by switching the frame synchronization means according to the earlier detected frame type among the detected frame types, frame synchronization can be achieved more quickly.
Further, when the detected frame types match, the frame synchronization means is switched, so that more accurate frame synchronization can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a specific example of a frame selection circuit 115 in FIG. 1;
FIG. 3 is a flowchart showing the operation of FIGS. 1 and 2;
FIG. 4 is a flowchart of a subroutine for explaining detection of frame type data.
FIG. 5 is a flowchart of a subroutine for explaining frame type detection.
FIG. 6 is another flowchart showing the operation of FIG. 1;
FIG. 7 is another flowchart showing the operation of FIG. 1;
8 is another block diagram showing a specific example of the frame selection circuit 115 in FIG.
FIG. 9 is a flowchart showing the operation of FIGS. 1 and 8;
FIG. 10 is a block diagram showing a specific example of a frame synchronization circuit 111, an error correction circuit 112, and a data output circuit 113 of FIG.
FIG. 11 is a configuration diagram illustrating a frame configuration “method B”.
FIG. 12 is a configuration diagram illustrating a frame configuration “method A0”.
FIG. 13 is a configuration diagram illustrating a frame configuration “method A1”.
FIG. 14 is a configuration diagram illustrating a frame configuration “method C”.
FIG. 15 is a relationship diagram showing a combination of two bits of frame type data.
[Explanation of symbols]
Reference Signs List 101 FM front end 102 FM demodulation circuit 103 MPX circuit 104 AF amplification circuit 105 Speaker 106 PLL frequency synthesizer 107 FM multiplexed data demodulation block 108 BPF
109 L-MSK demodulation circuit 110 Block synchronization circuit 111 Frame synchronization circuit 112 Error correction circuit 113 Data output circuit 114 Control circuit 115 Frame selection circuit 116 Operation key 117 Display 201 BIC detection circuit 202 Change point detection circuit 203 Data counter 204 Block counter 205 Frame synchronization detection circuit 206 Block synchronization detection circuit 207 Memory 208 Timing circuit 209 Data buffer 210 Error correction unit 211 Data output unit 301 First frame detection unit 302 Second frame detection unit 303 Frame setting unit

Claims (8)

In an FM multiplex receiving apparatus for demodulating multiplex data from FM multiplex broadcasting,
A frame synchronization circuit having a plurality of frame synchronization units, and performing frame synchronization of the multiplexed data by one of the plurality of frame synchronization units;
A control circuit including: first detection means for detecting frame type data included in the multiplexed data; and switching means for switching the plurality of frame synchronization means in accordance with an output signal of the first detection means;
A receiving device for FM multiplex broadcasting, comprising: The control circuit further includes a second detection unit that sequentially switches the plurality of frame synchronization units, and detects that the frame synchronization is established by the switched frame synchronization unit, and the first detection unit or the second detection unit. 2. The FM multiplex broadcast receiving apparatus according to claim 1, wherein a frame synchronization unit is selected based on a detection result of the second detection unit. 3. The FM multiplex broadcast receiving apparatus according to claim 2, wherein the control circuit selects the frame synchronizing means according to a detection result of the first and second detection means which is detected earlier. The control circuit further comprises: comparing means for comparing the detection results of the first and second detection means, and when both the detection results match, selects the frame synchronization means based on the detection results. 3. The FM multiplex broadcast receiving apparatus according to 2. 5. The FM multiplex broadcast receiving apparatus according to claim 4, wherein the control circuit operates the first detection unit and / or the second detection unit again when the two detection results do not match. 5. The FM multiplex broadcast receiving apparatus according to claim 4 , wherein when the two detection results do not match, the control circuit selects a detection result with a higher priority from the two detection results. 7. The FM multiplex broadcast receiving apparatus according to claim 6, wherein the priority of the detection result of the second detecting means is increased. Priorities are assigned to the plurality of frame synchronization units, and one of the plurality of frame synchronization units is selected by a frame synchronization unit having a higher priority among the detection results of the first and second detection units. The receiving device for FM multiplex broadcasting according to claim 6, wherein

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