JP3540388B2 - Computer system - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a computer system such as a personal computer, and more particularly to a computer system including an improved memory control logic for efficiently accessing a plurality of DRAM banks.
[0002]
[Prior art]
In recent years, various notebook-type or laptop-type portable personal computers which are easy to carry and can be operated by a battery have been developed. In this type of personal computer, it is desired to increase the operation speed, and recently, a high-performance microprocessor having a large-scale cache is being used as a CPU.
[0003]
When a microprocessor with a built-in cache is used as the CPU, the number of accesses to the main memory can be reduced, and the system operation performance can be improved to some extent.
[0004]
However, even if the CPU has a built-in cache, access to the main memory is not lost, and when a cache miss occurs, the CPU needs to execute a memory read / write cycle for the main memory. Therefore, in practice, it is essential to increase the execution speed of the memory read / memory write cycle by the CPU in order to improve the system performance.
[0005]
Generally, a dynamic RAM (DRAM) memory is used as a main memory of a personal computer. The DRAM has a feature that the access speed is slow, while the cost is lower than that of the static RAM (SRAM). In order to solve this problem, recently, in addition to improvements at the semiconductor technology level such as improvement of the DRAM chip itself, improvements at the memory architecture level by adopting interleave control and the like have been advanced.
[0006]
However, when constructing a memory architecture in a personal computer, it is necessary to consider not only the control of the internal memory mounted on the system board as standard, but also the control of various additional memories mounted as needed by the user.
[0007]
For this reason, the conventional memory control logic provided in the personal computer requires a very complicated hardware configuration. In particular, the complexity of the hardware logic for performing the memory address control is a direct cause of reducing the memory access speed.
[0008]
Hereinafter, the principle of DRAM address control using the conventional memory control logic will be described.
[0009]
Usually, a personal computer is provided with a plurality of extension memory connectors for mounting an additional memory such as a DRAM card. An additional memory such as a DRAM card is composed of one or more DRAM banks. All DRAM banks in the internal memory and the additional memory are connected to different row address strobe signal lines (RAS lines). In memory access control, one of the RAS lines is energized, and a DRAM bank connected to the RAS line is selected as an access target bank.
[0010]
The activation control of the RAS line is performed by an address decoder in the memory control logic. The address decoder activates a RAS line having a decoding condition that is satisfied by a memory address value from the CPU among a plurality of RAS lines. The decoding condition of each RAS line is determined as follows.
[0011]
That is, all the DRAM banks in the internal memory and the additional memory are arranged in the order of their physical mounting positions, that is, in the order of the system board, the extended memory connector 1, the extended memory connector 2,. It is arranged in order from the side. According to this memory arrangement, address ranges to be assigned to the DRAM banks are defined, and decoding conditions for each RAS line are determined according to the address ranges.
[0012]
In this case, the decoding condition of each RAS line is set as a head indicating the upper limit of the address range assigned to the corresponding DRAM bank so that the DRAM bank having any memory size may be connected to which RAS line. Both the address and the last address indicating the lower limit are used.
[0013]
Therefore, the address decoder needs to include two comparators for each RAS line in order to detect which RAS line the memory address from the CPU satisfies the decoding condition. One comparator compares the magnitude of the memory address value from the CPU with the top address value of the address range assigned to the corresponding RAS line, and the other comparator assigns the memory address value from the CPU to the RAS line. Compares with the last address value of the address range. If the memory address value is greater than or equal to the first address value and less than the last address value, the corresponding RAS line is activated.
[0014]
As described above, in the conventional memory control logic, it is necessary to provide many comparators in the address decoder, which has a disadvantage that a relatively large delay occurs inside the address decoder. This delay increases the time required for the RAS line to be energized, causing a reduction in memory access speed.
[0015]
In addition, such a delay related to the activation of the RAS line also becomes a factor limiting the memory access performance using the interleave architecture.
[0016]
That is, the interleaving is a technique of sequentially accessing different DRAM banks by switching the RAS line to be activated for each page, for example. When accessing the same DRAM bank continuously, it is necessary to wait for the time (precharge delay) after the completion of the previous memory cycle until the recharging of the memory cells of the DRAM bank is completed (precharge delay), and wait for the execution of the next memory cycle. There is. If interleaving is adopted, another DRAM bank can be accessed during a recharging period of a certain DRAM bank, and a time loss due to a precharge delay required when accessing the same bank continuously can be eliminated.
[0017]
However, the above-mentioned delay related to the RAS line activation slows down the switching speed of the RAS line itself, so that the high-speed interleaving access performance cannot be sufficiently exhibited. Actually, in order to realize interleaving, it is necessary to add, for example, a dedicated hardware logic for switching the RAS line in units of a page in addition to the address decoder. Will be further reduced.
[0018]
Also, in order to make effective use of interleaving, adjacent address ranges may be assigned to memory banks having relatively equal memory sizes in order to facilitate grouping for creating a combination of banks that can be interleaved. desirable. By doing so, it is possible to reduce the number of DRAM banks out of the combination of interleaving and to control the interleaving of more DRAM banks.
[0019]
However, as described above, conventionally, the memory arrangement of the DRAM banks in the system is determined only by the physical mounting positions of the DRAM banks. It will be placed in space. This limits the combinations of DRAM banks that can be interleaved, and causes an increase in the number of DRAM banks that fall outside the interleaving combinations.
[0020]
[Problems to be solved by the invention]
Conventionally, the arrangement of the DRAM banks in the memory address space in the system is determined only by the physical mounting position irrespective of the size of the memo size. For this reason, the hardware configuration of the address decoder is complicated, and the delay in the address decoder is increased.
[0021]
Further, the memory arrangement of the DRAM banks as described above is a factor that restricts combinations of DRAM bank groups that can be interleaved, and there is a disadvantage that high-speed access performance by interleaving cannot be sufficiently and effectively used.
[0022]
The present invention has been made in view of such a point, and simplifies decoding conditions of an address decoder by arranging DRAM banks in a system optimally in a memory address space according to their memory sizes, and realizes an interleave architecture. It is an object of the present invention to provide a computer system capable of effectively utilizing and realizing a high memory access speed.
[0023]
Means and action for solving the problem
In the computer system of the present invention, a plurality of access control signals are respectively assigned, a plurality of memory banks which can be accessed independently of each other, a plurality of decoding conditions respectively corresponding to the plurality of access control signals are set, An address decoder for detecting presence / absence of a condition and a memory address from a CPU, and energizing an access control signal line corresponding to the matched decode condition to select a memory bank; and a memory size of each of the plurality of memory banks. Means for relocating the plurality of memory banks in the memory address space in the order of the memory size so that the larger the memory size of the bank, the smaller the memory address space of the CPU. Memory to be assigned to each memory bank Memory relocation means for determining the address range,Means for determining a combination of two or more memory banks that can be page-interleaved according to the memory arrangement of the plurality of memory banks; and a memory belonging to the combination so that the memory banks belonging to the combination are alternately accessed in page units. The decoding condition of the access control signal line corresponding to each bank is defined by a bit string commonly present in binary data indicating all memory address values belonging to the address range of the entire memory bank belonging to the combination, and a page of each memory bank. Means for determining in accordance with a predetermined bit string between the internal address and the page designation address and setting the address in the address decoderAnd characterized in that:
[0024]
In this computer system, the memory size of each of the plurality of memory banks is detected, and the arrangement order of the memory banks in the memory address space is determined according to the size relationship of the memory sizes regardless of the physical mounting positions of the memory banks. It is determined. In this case, the plurality of memory banks are arranged in descending order of the memory address space of the CPU in descending order of the memory size.
[0025]
Under such a memory arrangement, the address range assigned to each of the plurality of memory banks matches well with the address boundary divided by the memory address value represented by the binary data. Therefore, all memory address values belonging to any address range always have a bit string having a common value only in that address range.Further, a combination of two or more memory banks that can be page-interleaved is determined according to the memory arrangement of the plurality of memory banks, and belonging to the combination so that the memory banks belonging to the combination are alternately accessed in page units. The decoding condition of the access control signal line corresponding to each memory bank is such that a bit string commonly present in binary data indicating all memory address values belonging to the address range of the entire memory bank belonging to the combination, It is determined according to a predetermined bit string between the intra-page address and the page designation address, and is set in the address decoder.
[0026]
Therefore, it is not necessary to use both the first address value and the last address value of each address range as decoding conditions, and the decoding conditions for each access control signal can be simplified. Thus, the address decoder only needs to detect a match / mismatch between the memory address value from the CPU and the decode condition for each access control signal. Therefore, the hardware configuration of the address decoder can be greatly simplified as compared with the related art, so that the delay in the address decoder is reduced and the memory access speed can be increased.Further, by setting the decoding condition, a page interleave for accessing a different bank for each page is performed by using an address decoder configuration in which a match / mismatch between the memory address value from the CPU and the decoding condition is detected for each access control signal. Architecture is realized.
[0030]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a computer system according to an embodiment of the present invention.
[0031]
This system is for realizing a notebook-type or laptop-type portable personal computer. On a system board 10, as shown, a CPU 11, a system controller 12, a system memory 13, a BIOS ROM 14, a real-time clock (RTC) 15, an interrupt controller (PIC) 16, a keyboard controller (KBC) 17, a display controller 18, and the like.
[0032]
On the system board 10, a CPU local bus (sometimes referred to as a processor bus) 31, a system bus 32 having specifications such as ISA / EISA / PCI, and a memory address bus 33 are provided.
[0033]
Further, this system is provided with two expansion memory connectors 21 and 22 for connecting an additional memory. FIG. 1 shows a state in which additional memories 41 and 42 are connected to the extended memory connectors 21 and 22, respectively.
[0034]
The additional memories 41 and 42 are optional memories that are mounted as needed by the user in order to expand the system memory size, and include, for example, a DRAM card and a SIMM memory module. These additional memories are usually composed of one or more DRAM banks.
[0035]
The CPU 11 is a microprocessor including a large-scale cache memory, and for example, an Intel 486 CPU manufactured by Intel Corporation of the United States is used. The CPU 11 is connected to the system controller 12 via a CPU local bus 31. The CPU local bus 31 is a group of signals directly connected to input / output pins of a microprocessor constituting the CPU 11. This includes a 32-bit data bus, a 32-bit address bus, various status signal lines, and the like.
[0036]
The system controller 12 is connected between the CPU local bus 31 and the system bus 32, and controls all memories and I / O devices in the system in response to a request from the CPU 11. The system controller 12 is realized by one LSI constituted by a gate array, in which a memory control logic lock for controlling the DRAM of the system memory 13 and the additional memories 41 and 42 is incorporated. .
[0037]
The system memory 13 is used as a main memory of the system, and usually includes one or more DRAM banks. The system memory 13 stores an operating system, an application program to be executed, various types of processing data, and the like.
[0038]
The system memory 13 is mounted on the system board 10 via a predetermined connector or directly. The system memory 13 is a 32-bit memory device, and its data port is connected to a 32-bit data bus of the CPU local bus 31, and an address input port is connected to a memory address bus 33. The memory address bus 33 is an address bus dedicated to the DRAM, and a physical address (row address / column address) of the DRAM is output from the system controller 12 to the memory address bus 33.
[0039]
Similarly, the extension memories 41 and 42 are also 32-bit memory devices, the data ports of which are connected to the 32-bit data bus of the CPU local bus 31 via the corresponding connectors 21 and 22, and the address input port is the memory address. It is connected to the bus 33.
[0040]
Further, two row address strobe signal lines (RAS lines: RAS0, RAS1) are connected to the system memory 13. Similarly, another two row address strobe signal lines (RAS lines: RAS2 and RAS3) are connected to the extended memory connector 21, and another two row address strobe signal lines (RAS) are also connected to the extended memory connector 22. (RAS: RAS4, RAS5) are connected.
[0041]
Further, a column address strobe signal line (CAS line) and other various control signal lines (write enable signal line WE, output enable signal line OE, etc.) are commonly connected to the system memory 13 and the additional memories 41 and 42, respectively. Have been.
[0042]
All the DRAM banks in the system memory 13 and the additional memories 41 and 42 are arranged in the DRAM memory address space of the CPU 11. In this system, in order to simplify the decoding conditions of each RAS line and to make the most of the interleave architecture, the DRAM banks are arranged at lower addresses as the memory size increases.
[0043]
In the read / write access control of the system memory 13 and the additional memories 41 and 42, one of the RAS lines (RAS0 to RAS5) is set to the active state, and the DRAM bank connected to the active RAS line is to be accessed. Selected as DRAM bank. Such activation control of the RAS line is executed by the memory control logic of the system controller 12.
[0044]
FIG. 2 shows the configuration of the memory control logic.
[0045]
Memory controllogicReference numeral 120 denotes hardware logic that supports page mode access and page interleaving of the DRAM, and includes an address conversion circuit 121, a RAS decoder 122, a row address / column address multiplexer 123, a CAS generation circuit 124, a timing control circuit 125, and a page hit. It has a judgment circuit 126.
[0046]
The address conversion circuit 121 converts the CPU address (A31: 02) into a DRAM logical address (MA31: 02). This conversion is performed to continuously allocate a plurality of DRAM memory areas distributed in the memory address space of the CPU 11 to a logical address space dedicated to DRAM access. FIG. 3 shows an example of this address conversion operation.
[0047]
That is, as shown in FIG. 3A, the memory address space of the CPU 11 usually includes a video RAM, a BIOS ROM, and various options in addition to a DRAM area such as a system memory area and a PM memory area. A reserved area (0A0000H to 0C0000H) for arranging a ROM or the like is secured. The address conversion circuit 121 performs the address conversion according to such a CPU memory map so that the addresses of the DRAM area immediately before and immediately after the reserved area are continuous.
[0048]
Further, when a VGA BIOS or a system BIOS stored in the BIOS ROM is copied to the DRAM and used, as shown in FIG. 3B, the VGA BIOS area and the system BIOS area of the reserved area are used. The assigned CPU address is also converted to a DRAM logical address. Further, in the case of a CPU having a system management mode (SMM), the CPU address assigned to the SMRAM area used only in the SMM is also converted to a DRAM logical address.
[0049]
Such conversion from the CPU address to the DRAM logical address is performed, for example, in units of 16 Kbytes. For this reason, the lower bit part (MA13: 02) of the DRAM logical address is equal to the lower bit part (A13: 02) of the CPU address even after the address conversion.
[0050]
The DRAM logical address (MA31: 02) obtained by the address conversion circuit 121 is used for addressing a DRAM bank in the system.
[0051]
The RAS decoder 122 decodes the DRAM logical address (MA31: 02) according to the respective decode conditions of RAS0 to RAS5 set in its internal register, and RAS having a decode condition satisfying the DRAM logical address among the RAS0 to RAS5 lines. Select a line and make it active. The timing at which the RAS line is activated is controlled by a timing control signal CONT1 from the timing control circuit 125.
[0052]
The decoding operation of the RAS decoder 122 can be performed only by detecting the match / mismatch between the decode condition of each RAS line and the DRAM logical address. How the decoding conditions for each of the RAS0 to RAS5 lines are determined will be described in detail with reference to FIG.
[0053]
The row address / column address multiplexer 123 divides the DRAM logical address (MA31: 02) into a row address (RA) and a column address (CA) for addressing the DRAM bank to be accessed. In an internal register of the row address / column address multiplexer 123, a control parameter indicating a start bit position of a row address (RA) of each DRAM bank is set in advance. The operation of decomposing into a row address (RA) and a column address (CA) is performed according to a control parameter corresponding to a DRAM bank to be accessed.
[0054]
The row address (RA) and the column address (CA) are output on the memory bus 33 in a time-division manner. This output timing is controlled by a timing control signal CONT2 from the timing control circuit 125.
[0055]
The CAS generation circuit 124 controls the energization of the CAS line according to the timing control signal CONT3 from the timing control circuit 125.
[0056]
The timing control circuit 125 controls the operations of the RAS decoder 122, the row address / column address multiplexer 123, and the CAS generation circuit 124 by generating the above-described timing control signals CONT1 to CONT3. The operation of generating the timing control signal is controlled by a page hit signal HIT from the page hit determination circuit 126 or the like.
[0057]
The page hit determination circuit 126 holds the CPU address at the time of the previous DRAM access as a CPU address for page heat determination, and compares the CPU address with the CPU address at the next DRAM access to determine the page hit. Determine the presence or absence. Here, a page hit means that the next DRAM access accesses the same page in the same DRAM bank as the previous DRAM access. When it is determined that a page hit has occurred, this is notified to the timing control circuit 125 by a page hit signal HIT.
[0058]
As described above, the page hit determination operation is performed based on the value of the CPU address instead of the DRAM logical address. Thus, the address conversion operation and the page hit determination operation can be performed in parallel. The CPU address can be used for the page hit determination because the unit (16 Kbytes) of the address conversion from the CPU address to the DRAM logical address is set to a value larger than the page size (up to about 4 Kbytes) of the DRAM bank. Because it is.
[0059]
To determine a page hit, a bit string higher than the column address in the CPU address (A31: 02) is used. The number of bits of the column address, that is, the page size differs for each DRAM bank to be accessed. For this reason, a control parameter for designating a bit to be used for the page hit determination for each RAS line is also set in the internal register of the page hit determination circuit 126 in advance, and the page hit is determined according to the control parameter corresponding to the DRAM bank to be accessed. A determination is made.
[0060]
The DRAM control timing by the memory control logic 120 is classified into cycle timings corresponding to the following three states.
[0061]
(1) Page hit
This means that the next DRAM access accesses the same page in the same DRAM bank as the previous DRAM access. In this case, the access of the DRAM bank is controlled in the page mode. That is, only the column address and the activation timing of the CAS line are controlled, and the RAS decoder 122 does not switch the RAS line. Also, the RAS line is kept in the active state even after the previous memory cycle is completed.
[0062]
(2) Bank mistake
This means that the next DRAM access accesses a different DRAM bank from the previous one. In this case, RAS decoder 122 switches the RAS line, and the DRAM bank is accessed in a normal DRAM access cycle. Also, the page hit determination CPU address stored in the page hit determination circuit 126 is updated.
[0063]
(3) Page mistake
This means that the next DRAM access accesses a different page in the same DRAM bank as the previous DRAM access. In this case, RAS decoder 122 resets the same RAS line to the active state again, and the DRAM bank is accessed in a normal DRAM access cycle. Also, the page hit determination CPU address stored in the page hit determination circuit 126 is updated.
[0064]
Next, the decoding conditions of each RAS line set in the RAS decoder 122 will be described with reference to FIGS.
[0065]
FIG. 4 shows an example of a DRAM memory map in the system. In this DRAM memory map, as shown in FIG. 1, two 2-Mbyte DRAM banks are mounted on the system board 10 as the system memory 13 and the additional memory 41 of the This corresponds to the case where the expansion memory 42 of the extended memory connector 22 is composed of two 4 Mbyte DRAM banks.
[0066]
In this case, these DRAM banks are arranged in the order of the memory size, that is, as shown in FIG. 4, an 8 Mbyte DRAM bank, two 4 Mbyte DRAM banks, and two 2 Mbyte DRAM banks in total in order of 20 Mbytes. Are arranged in a DRAM logical address space.
[0067]
In this memory arrangement, an address range of 0 to 8 Mbytes is assigned to the RAS2 line corresponding to an 8 Mbyte DRAM bank. The RAS4 line corresponding to the first 4 Mbyte DRAM bank is assigned an address range of 8 to 12 Mbytes, and the RAS5 line corresponding to the next 4 Mbyte DRAM bank is assigned an address range of 12 to 16 Mbytes. Further, an address range of 16-18 Mbytes is allocated to the RAS0 line corresponding to the first 2 Mbyte DRAM bank, and an address range of 18-20 Mbytes is allocated to the RAS1 line corresponding to the next 2 Mbyte DRAM bank. Since the RAS3 line is not used, no address range is assigned to this RAS3 line.
[0068]
At this time, the decoding conditions for the RAS0 to RAS5 lines are determined as shown in FIG.
[0069]
As a decoding condition for each of the RAS0 to RAS5 lines, a bit string that is commonly present only in all DRAM logical address values (MA31: 02) belonging to the address range assigned to each RAS line is used.
[0070]
That is, the decoding condition of the RAS2 line is such that the upper 9 bits (MA31 to 23) of the DRAM logical address value (MA31: 02) = "000000000". The lower 21 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of an 8 Mbyte DRAM bank connected to the RAS2 line.
[0071]
The decoding condition of the RAS4 line is that the upper 10 bits (MA31 to 22) of the DRAM logical address value (MA31: 02) = “0000 0000 10”. The lower 20 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 4 Mbyte DRAM bank connected to the RAS4 line.
[0072]
The decoding condition of the RAS5 line is that the upper 10 bits (MA31 to 22) of the DRAM logical address value (MA31: 02) = “0000 0000 11”. The lower 20 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 4 Mbyte DRAM bank connected to the RAS5 line.
[0073]
The decoding condition of the RAS0 line is that the upper 11 bits (MA31 to 21) of the DRAM logical address value (MA31: 02) = "00000001000". The lower 19 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 2 Mbyte DRAM bank connected to the RAS0 line.
[0074]
The decoding condition of the RAS1 line is that the upper 11 bits (MA31 to 21) of the DRAM logical address value (MA31: 02) = "00000001000". The lower 19 bits of the DRAM logical address value (MA31: 02) are used as a row address and a column address of a 2 Mbyte DRAM bank connected to the RAS0 line.
[0075]
As described above, a common bit string belonging to an address range corresponding to each RAS line is used as a decoding condition for each RAS line. Therefore, the above-mentioned RAS decoder 122 only needs to detect the match / mismatch between the DRAM logical address value and the decode condition for each RAS line, and can greatly simplify the hardware configuration as compared with the related art. It becomes possible.
[0076]
Next, the decoding conditions of each RAS line when the page interleave architecture is adopted will be described.
[0077]
When performing page interleaving, the five DRAM banks mapped as shown in FIG. 4 are classified into bank groups capable of page interleaving. Each bank group includes a combination of banks having adjacent memory address ranges and matching total memory sizes. Such grouping is performed in ascending order of DRAM logical address.
[0078]
That is, in the example of FIG. 4, the total memory size of the two 4 Mbyte DRAM banks allocated to the address range (0 to 8 Mbytes) following the address range of the 8 Mbyte DRAM bank of RAS2 is 8 Mbytes. One page interleave group is configured by three banks corresponding to RAS2, RAS4, and RAS5.
[0079]
Further, since the 2 Mbyte DRAM bank of RAS1 is allocated to the address range following the address range (16 to 8 Mbytes) of the 2 Mbyte DRAM bank of RAS0, another page interleave is performed by the two banks corresponding to RAS0 and RAS1. A group is formed.
[0080]
In this case, the decoding condition of each RAS line is changed as shown in FIGS.
[0081]
That is, the decoding conditions of RAS2, RAS4, and RAS5 of group 1 are common to all DRAM logical address values (MA31: 02) belonging to a total address range of 16 Mbytes (0 to 16 Mbytes) assigned to group 1. An existing bit string and a bit string between a column address (in-page address) and a row address (page address) of a DRAM bank corresponding to each of RAS2, RAS4, and RAS5 are used.
[0082]
That is, as shown in FIG. 6, in the address range of a total of 16 Mbytes allocated to RAS2, RAS4, and RAS5, the upper 8 bits (MA31 to 24) of the DRAM logical address value (MA31: 02) = “0000 0000”. Commonly present, which is not present in Group 2. Therefore, (MA31 to 24) = "0000 0000" is used as a common decoding condition for RAS2, RAS4, and RAS5.
[0083]
As for RAS2, the start position of the row address in the DRAM logical address is shifted left by one bit, and one bit (MA12) = "0" between the row address and the column address of the 8 Mbyte DRAM bank corresponding to RAS2 is decoded. Added as a condition.
[0084]
For each of RAS4 and RAS5, the starting position of the row address in the DRAM logical address is shifted left by 2 bits, and the 2 bits (MA13, 12) between the row address and the column address of the corresponding 4 Mbyte DRAM bank are shifted. The value is added as an address condition. Two bits are used because the memory size of each of RAS4 and RAS5 is half the memory size of RAS2.
[0085]
That is, for RAS4, 2 bits (MA13, 12) = "01" between the row address and the column address of the 4M byte DRAM bank corresponding to RAS4 are added as decoding conditions, and for RAS5, RAS5 corresponds to RAS5. 2 bits (MA13, 12) = "11" between the row address and the column address of the 4M byte DRAM bank to be added are added as address conditions.
[0086]
When the decoding conditions for RAS2, RAS4, and RAS5 are determined in this manner, even-numbered pages (0, 2, 4, 6,...) Within the address range of 0 to 16 Mbytes are allocated to the 8 Mbyte DRAM bank of RAS2. , RAS4, a part of an odd page (1, 5, 9,...) Within an address range of 0 to 16 Mbytes is allocated to the 4 Mbyte DRAM bank, and a 4 Mbyte DRAM bank of RAS5 has 0 to 16 Mbytes. , The remaining odd pages (3, 7, 11,...) In the address range are assigned.
[0087]
Therefore, when continuous access is performed in the range of 0 to 16 Mbytes, three DRAM banks are alternately accessed in page units in the order of RAS2, RAS4, RAS2, RAS5, RAS2,.
[0088]
On the other hand, the decoding conditions of RAS0 and RAS1 of group 2 are as follows.
[0089]
That is, the decoding conditions for RAS0 and RAS1 include a bit string that is common to all DRAM logical address values (MA31: 02) belonging to a total address range of 4 Mbytes (16 to 20 Mbytes) allocated to group 2; A bit string between a column address and a row address of a DRAM bank corresponding to each of RAS0 and RAS1 is used.
[0090]
In the address range of a total of 4 Mbytes allocated to RAS0 and RAS1, the upper 10 bits (MA31 to 22) = “0000 0001 00” of the DRAM logical address value (MA31: 02) are present in common, which is group 1 Does not exist. Therefore, (MA31-22) = "00000001 00" is used as a common decoding condition for RAS0 and RAS1.
[0091]
Regarding RAS0, the start position of the row address in the DRAM logical address is shifted left by one bit, and one bit (MA11) between the row address and the column address of the 2 Mbyte DRAM bank corresponding to RAS0 = "0". Is added as a decoding condition.
[0092]
As for RAS1, the start position of the row address in the DRAM logical address is shifted one bit to the left, and one bit (MA11) = "1" between the row address and the column address of the corresponding 2-Mbyte DRAM bank is set as the decoding condition. Added.
[0093]
When the decoding conditions for RAS0 and RAS1 are determined in this manner, even-numbered pages (0, 2, 4, 6,...) In a 4 Mbyte address range of 16 to 20 Mbytes are allocated to the 2 Mbyte DRAM bank of RAS0. Odd pages (1, 3, 5, 7,...) Are allocated to the 2-Mbyte DRAM bank of RAS1. Therefore, when continuous access is performed in the range of 16 to 20 Mbytes, two DRAM banks are alternately accessed in page units in the order of RAS0, RAS1, RAS0, RAS1,....
[0094]
As described above, the page interleaving determines the decoding condition of each RAS based on the bit string commonly existing in the address range of the interleave group and the predetermined bit string between the row address and the column address, and determines the decoding condition for each RAS. Can be realized simply by setting
[0095]
Initial setting processing for the memory control logic 120 such as setting of decoding conditions for the RAS decoder 122 is executed by the IRT routine of the BIOS ROM 14.
[0096]
FIG. 7 shows a procedure of an initialization operation for the memory control logic 120 executed by the IRT routine.
[0097]
When the system is powered on, the IRT routine first checks the memory type (bit width of each of the column address and the row address) of each DRAM bank, and detects the memory size according to the memory bank type (step S11). The bit width of each of the column address and the row address can be detected by executing a write / read compare test for a specific memory address of the DRAM bank to be tested.
[0098]
Details of the memory size detection processing operation performed in step S11 will be described later with reference to FIG.
[0099]
Next, the IRT routine performs memory relocation of the DRAM banks in the system (step S12). In this memory rearrangement, as described with reference to FIG. 4, the memory banks are arranged in ascending order of the memory address space from the DRAM bank having the largest memory size, and the address range to be allocated to each DRAM bank is determined according to the arrangement.
[0100]
Next, as described with reference to FIG. 5, the IRT routine detects, for each address range assigned to each DRAM bank, a bit string that exists only in the DRAM logical address value belonging to that range, and converts the common bit string to the RAS line. Each decoding condition is determined (step S13).
[0101]
When the page interleave architecture is not used, the IRT routine sets the decoding condition of each RAS line determined in step S13 as it is in the internal register of the RAS decoder 122 (step S17). Next, the IRT routine sets a control parameter for designating the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and uses the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for designating the position of the CPU address to be executed for each RAS line is set (step S18). The values of these control parameters are determined according to the memory bank type detected in step S11.
[0102]
On the other hand, when the page interleave architecture is adopted, the IRT routine determines a group that can be page-interleaved according to the DRAM map arranged in the order of the memory size in step S12 (step S15). Next, the IRT routine changes the decoding condition of each RAS based on the bit string commonly existing in the address range of the page interleave group and the predetermined bit string between the row address and the column address (step S16).
[0103]
Thereafter, the IRT routine sets the decoding condition of each RAS line determined in step S16 in an internal register of the RAS decoder 122 (step S17). Next, the IRT routine sets a control parameter for designating the row address start position for each RAS line in the internal register of the row address / column address multiplexer 123, and uses the internal register of the page hit determination circuit 126 for page hit determination. A control parameter for designating the position of the CPU address to be executed for each RAS line is set (step S18). The row address start position is determined based on the memory bank type detected in step S11 and the number of bits between the row address and the column address used as a decoding condition for page interleaving. The position of the CPU address used for page hit determination is determined according to the memory bank type detected in step S11.
[0104]
Next, the principle of the process of detecting the memory size of the DRAM bank will be described with reference to FIGS.
[0105]
First, with reference to FIG. 8, the types of DRAM banks that can be controlled by one RAS will be described. The DRAM banks are roughly divided into four banks of type 1 to type 4 as shown in the figure.
[0106]
Type 1 DRAM banks have a memory size of 2 Mbytes. This type 1 DRAM bank includes four 4M bit DRAM chips of 512K (1K rows × 512 columns) × 8 bits, and the bit width of the row address is 10 bits and the bit width of the column address is 9 bits. is there.
[0107]
Type 2 DRAM banks have a memory size of 4 Mbytes. This type 2 DRAM bank includes eight 4M bit DRAM chips each having a 1M (1K row × 1K column) × 4 bit configuration. The bit width of a row address is 10 bits and the bit width of a column address is 10 bits. is there.
[0108]
Type 3 DRAM banks have a memory size of 8 Mbytes. This type 3 DRAM bank includes four 16M bit DRAM chips of 2M (2K rows × 1K columns) × 8 bits configuration, and the bit width of the row address is 11 bits and the bit width of the column address is 10 bits. is there.
[0109]
Type 4 DRAM banks have a memory size of 16 Mbytes. This type 4 DRAM bank includes eight 16M bit DRAM chips of 4M (2K rows × 2K columns) × 4 bits, and the bit width of the row address is 11 bits and the bit width of the column address is 11 bits. is there.
[0110]
FIGS. 9, 10, and 11 show the memory configurations of the system memory 13, the extension memory 41, and the extension memory 42 of FIG. 1, respectively.
[0111]
When the system memory 13 is constituted by two 2 Mbyte DRAM banks of type 1, as shown in FIG. 9, four DRAM chips of one 2 Mbyte DRAM bank have RAS0 line and CAS line. , And the other four DRAM chips of the 2 Mbyte DRAM bank are commonly connected to the RAS1 line and the CAS line. All the chips in these two 2 Mbyte DRAM banks are connected in parallel to both the memory address bus 33 and the data bus 322.
[0112]
Which of these two 2 Mbyte DRAM banks is addressed is determined by which of RAS0 and RAS1 is activated.
[0113]
When the RAS0 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken in as the row address by the four chips connected to the RAS0 line. Thereafter, the four chips connected to the RAS0 line take in the lower 9 bits of the address value output on the memory address bus 33 as the column address when the CAS line is activated. The same address of each of the four chips connected to the RAS0 line is simultaneously addressed by the 10-bit row address and the 9-bit column address, and a DRAM corresponding to the RAS0 line in a total of 32 bits of 8 bits per chip. The bank is read / write accessed.
[0114]
Similarly, when the RAS1 line is activated, the low-order 10-bit row address of the address value output on the memory address bus 33 at that time is taken into each of the four chips connected to the RAS1 line. It is. Thereafter, the four chips connected to the RAS1 line take in the lower 9-bit column address of the address value output on the memory address bus 33 when the CAS line is activated. With these 10-bit row address and 9-bit column address, the same storage location of each of the four chips connected to the RAS1 line is simultaneously addressed, and 8 bits per chip correspond to the RAS1 line in a total of 32 bits. The read / write access is made to the DRAM bank to be executed.
[0115]
When the additional memory 41 is configured by one type 3 8M byte DRAM bank, as shown in FIG. 10, the four DRAM chips of the 8M byte DRAM bank are connected to the RAS2 line and the CAS line. Commonly connected. All chips in the 8 Mbyte DRAM bank are connected in parallel to both the memory address bus 33 and the data bus 322.
[0116]
When the RAS2 line is activated, the lower 11 bits of the address value output on the memory address bus 33 at that time are taken into four chips connected to the RAS2 line as a row address. Thereafter, the four chips connected to the RAS2 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is activated. With the 11-bit row address and the 10-bit column address, the corresponding storage locations of each of the four chips connected to the RAS0 line are simultaneously addressed, and RAS2 in 8 bits per chip in a total of 32 bits. The DRAM bank corresponding to the line is read / write accessed.
[0117]
When the additional memory 42 is constituted by two 4 Mbyte DRAM banks of type 2, as shown in FIG. 11, eight DRAM chips of one 4 Mbyte DRAM bank have RAS4 line and CAS line. , And the other eight DRAM chips of the 4 Mbyte DRAM bank are commonly connected to the RAS5 line and the CAS line. All chips in the 4 Mbyte DRAM bank are connected in parallel to both the memory address bus 33 and the data bus 322.
[0118]
Which of these two 4 Mbyte DRAM banks is addressed is determined by which of RAS4 and RAS5 is activated.
[0119]
When the RAS4 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken in as the row address by the eight chips connected to the RAS4 line. Thereafter, the eight chips connected to the RAS4 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is activated. With the 10-bit row address and the 10-bit column address, the same storage location of each of the eight chips connected to the RAS4 line is simultaneously addressed. The corresponding DRAM bank is read / write accessed.
[0120]
Similarly, when the RAS5 line is activated, the lower 10 bits of the address value output on the memory address bus 33 at that time are taken into the eight chips connected to the RAS5 line as row addresses. It is. Thereafter, the eight chips connected to the RAS5 line take in the lower 10 bits of the address value output on the memory address bus 33 as the column address when the CAS line is activated. With these 10-bit row address and 10-bit column address, the same storage location of each of the eight chips connected to the RAS5 line is simultaneously addressed. The corresponding DRAM bank is read / write accessed.
[0121]
As described above, the relationship between the number of bits used as a row address and the number of bits used as a column address differs for each type of DRAM bank. The memory size of the DRAM bank connected to each RAS line is detected using the difference in the number of bits used as a row address and a column address.
[0122]
Hereinafter, the procedure of the memory size detection process executed in step S11 of the IRT routine will be described with reference to the flowchart of FIG.
[0123]
The IRT routine performs a memory size detection process of the DRAM bank connected to the RAS line in the order of RAS0, RAS1, RAS2,. First, the IRT routine sets a predetermined decoding condition in the RAS decoder 122 so that only the energization of the RAS line to be inspected is permitted (step S21). In this case, as a decoding condition of the RAS line to be inspected, a bit string common to memory address values used in several times of memory accesses performed for detecting a memory size is used. All the other RAS lines except for the RAS line to be inspected are different from the RAS line to be inspected so that the RAS lines are not energized in several memory accesses performed for detecting the memory size. A predetermined bit string is set as each decoding condition.
[0124]
Next, in the IRT routine, the type 4 DRAM bank (column address CA = 11 bits, row address RA = 11 bits) having the largest column address bit number among the type 1 to type 4 DRAM banks is used as the RAS line to be inspected. And a write / read compare test is performed on the DRAM bank (step S22). In this case, a control parameter corresponding to the type 4 DRAM bank is set in the row address / column address multiplexer 123. In the write / read compare test, a write access of a write address 00001000H (H indicates hexadecimal notation) and a read access of a read address 00000000H are performed, and it is checked whether or not the write data and the read data match at that time. (Step S23).
[0125]
If the DRAM bank actually connected to the RAS line to be inspected is a type 4 DRAM bank as expected, data can be normally written to the address 00001000H, so that the values of the write data and the read data are Will not match. On the other hand, if the DRAM bank actually connected to the RAS line to be inspected is a bank of type 1, type 2, or type 3 whose column address number is 10 bits or less, the value of write data and read data Matches. This is for the following reason.
[0126]
That is, since the setting corresponding to the type 4 DRAM bank is made in step S22, the 11-bit row address RA (MA23,..., MA13) output at the time of the write access of the address 00001000H is 0000000000000, The bit column address CA (MA12,..., MA02) = 1000000000000. In a DRAM bank in which the number of column addresses is 10 bits or less, the value "1" of the most significant bit MA12 of the 11-bit column address CA is ignored. Therefore, when a bank of type 1, type 2, or type 3 is connected, the write access of the write address 00001000H causes the address designated by the column address CA = 00000000H in the first row, that is, the address 00000000H. Data is written. As a result, the read data read by the read access of the read address 00000000H matches the write data.
[0127]
Therefore, when the mismatch between the write data and the read data is detected in step S23, the DRAM bank connected to the RAS line to be inspected is a type 4 DRAM bank as expected (CA = 11 bits, RA = 11 bits). , Memory size = 16 Mbytes) (step S 24). On the other hand, if a match between the write data and the read data is detected, the DRAM bank connected to the RAS line to be tested has the number of column address bits. Is a DRAM bank of another type (Type 1, Type 2, or Type 3) of 10 bits or less. In this case, the following processing from step S25 is performed.
[0128]
That is, this time, the IRT routine uses the memory configuration (column address CA = 10 bits, row address RA = 11 bits) of the type 3 (or type 2) memory having the next largest number of column address bits after type 4 And a write / read compare test is performed on the DRAM bank (step S25). In the write / read compare test, a write access of the write address 00000800H and a read access of the read address 00000000H are performed, and it is checked whether or not the write data and the read data at that time coincide with each other (step S26).
[0129]
If the DRAM bank actually connected to the RAS line to be inspected is a type 1 DRAM bank having a column address of 9 bits or less, the most significant bit "1" of the column address as described above. Is ignored, data is written to the address specified by the address 00000000H of the type 1 DRAM bank. As a result, the values of the write data and the read data match. Therefore, when a match between the write data and the read data is detected, the DRAM bank connected to the RAS line to be inspected is a type 1 DRAM bank (CA = 9 bits, RA = 10 bits, memory size = 2 Mbytes) ) Is determined (step S27).
[0130]
On the other hand, if the DRAM bank actually connected to the RAS line to be inspected is a type 2 or type 3 DRAM bank having the expected 10-bit column address bit number, data can be normally written to the address 00010000H. Therefore, the values of the write data and the read data do not match. Therefore, when the mismatch between the write data and the read data is detected, the following processing from step S28 is performed to detect which type 2 or type 3 DRAM bank is connected. .
[0131]
That is, the IRT routine assumes that type 3 DRAM banks (column address CA = 10 bits, row address RA = 11 bits) having a larger number of row address bits are connected. Then, a write / read compare test is performed on the DRAM bank (step S28).
[0132]
In this write / read compare test, a write access of the write address 00400000H and a read access of the read address 00000000H are performed, and it is checked whether or not the write data and the read data match at that time (step S29).
[0133]
If the DRAM bank actually connected to the inspection target RAS line is a type 3 DRAM bank as expected, data can be normally written to the address 00400000H, so that the values of the write data and the read data are Will not match. On the other hand, when the DRAM bank actually connected to the RAS line to be inspected is a type 2 bank whose row address is 10 bits, the values of the write data and the read data match. This is for the following reason.
[0134]
That is, since the setting corresponding to the type 3 DRAM bank is made in step S28, the 11-bit row address output at the time of the write access of the address 00400000H is RA (MA22,..., MA12) = 1000000000000, and The bit column address CA (MA11,..., MA02) = 000000000. In a type 2 DRAM bank having 10-bit row addresses, the value “1” of the most significant bit MA22 of the 11-bit row address RA is ignored. Therefore, when a type 2 bank is connected, data is written to the address specified by the column address CA = 00000000000 in the first row, that is, the address 00000000H by the write access of the write address 00400000H. As a result, the read data read by the read access of the read address 00000000H matches the write data.
[0135]
Therefore, when a mismatch between the write data and the read data is detected in step S29, the DRAM bank connected to the RAS line to be inspected is a type 3 DRAM bank as expected (CA = 10 bits, RA = 11 bits). , Memory size = 8 Mbytes) (step S30). On the other hand, if a match between the write data and the read data is detected, the DRAM bank connected to the RAS line to be inspected has the number of row address bits. Is a 10-bit type 2 DRAM bank (CA = 10 bits, RA = 10 bits, memory size = 4 Mbytes) (step S31).
[0136]
Next, specific circuit configurations of the RAS decoder 122, the row address / column address multiplexer 123, and the page hit determination circuit 126 described with reference to FIG. 2 will be described.
[0137]
FIG. 13 shows a specific circuit configuration of the RAS decoder 122. As shown, the RAS decoder 13 includes six RAS decode circuits 51 to 56 corresponding to the RAS0 to RAS5 lines, respectively. Each of the RAS decode circuits 51 to 56 checks whether or not the DRAM logical address (MA31: 02) matches the corresponding decode condition, and when they match, controls the energization of the corresponding RAS line at a predetermined timing. In this case, actually, it is not necessary to see all the bit values of the 30-bit DRAM logical address (MA31: 02), and the conditions of MA26, MA25, MA24, MA24, MA24, MA23, MA22, MA21, skipping, only 9 bits of MA13, MA12, MA11 are used for decoding.
[0138]
Since the RAS decode circuits 51 to 56 have the same circuit configuration, the circuit configuration of the RAS decode circuit 51 will be described as a representative here.
[0139]
The RAS decode circuit 51 includes a RAS set register 61, a RAS mask register 62, nine match / mismatch detection circuits 71 to 79, nine mask circuits 71 to 79, and an AND circuit 91.
[0140]
The RAS set register 61 is an I / O register that is readable / writable by the CPU 11, and sets a bit string indicating the decoding condition of the RAS0 line. For example, when the decoding condition of the RAS0 line is determined as shown in FIG. 5, “00100XXX1” is set in the RAS set register 61 as the decoding condition of the RAS0 line. Here, X means an indefinite bit value (Don't Care) not related to the decoding condition.
[0141]
The RAS mask register 62 is an I / O register that can be read / written by the CPU 11, and determines whether the result of determining whether the decoding condition of the RAS0 line matches the DRAM logical address is masked bit by bit or not. Is set ("0" = mask, "1" = no mask). Here, masking means that the determination result of that bit always matches, regardless of the determination result of the corresponding one bit of the bit string of the decoding condition. Therefore, when “00100XXX1” is set as the decoding condition in the RAS set register 61 as described above, the mask data “111110 001” is set in the RAS mask register 62. Thereby, the bit of “X” in the decoding condition “00100XXX1” can be excluded from the decoding condition.
[0142]
The match / mismatch detection circuits 71 to 79 detect match / mismatch between bits corresponding to the DRAM logical address and the decoding condition, respectively. Each of the match / mismatch detection circuits 71 to 79 can be realized by an exclusive OR gate. The nine mask circuits 71 to 79 mask the detection result outputs of the corresponding match / mismatch detection circuits 71 to 79, respectively.
[0143]
As described above, the RAS decoder 122 can be realized only with logic for matching / mismatching data corresponding to a data size of 9 bits per RAS line.
[0144]
Next, a specific circuit configuration of the row address / column address multiplexer 123 will be described with reference to FIG.
[0145]
As shown, the row address / column address multiplexer 123 includes a register file 201, a pattern decoder 202, a row address selector 203, row address start position switching circuits 204 to 207, and a row address / column address selector 208. .
[0146]
The register file 201 is a group of I / O registers that can be read / written by the CPU 11, and sets six control parameters corresponding to each of the RAS0 to RAS5 lines. Each control parameter specifies the row address start position of the DRAM bank connected to the corresponding RAS line, that is, which bit of the DRAM logical address is to be the LSB of the row address.
[0147]
The four bits of the DRAM logical address MA11, MA12, MA13, and MA14 may be used as the row address start position, depending on the type of DRAM to be supported and page interleaving conditions. Each control parameter is composed of 4-bit data specifying one of these four types of row address start positions. The control parameter “0001” specifies MA11, “0010” specifies MA12, “0011” specifies MA13, and “0100” specifies MA14.
[0148]
One of the six control parameters set in the register file 201 is read by the pattern decoder 202. Which control parameter is read is determined by the decoding result output of the RAS decoder 122. For example, when the RAS decoder 122 activates the RAS line, the control parameters corresponding to the RAS line are read from the register file 201.
[0149]
The pattern decoder 202 decodes the control parameters read from the register file 201, and generates a selection signal for causing the selector 203 to select one of four types of row addresses according to the decoding result.
[0150]
The row address start position switching circuit 204 sets a total of 11 bits (MA21,..., MA11) having the MA11 as the row address start position (LSB) from the DRAM logical addresses MA31: 02 as the row address (RA10: 0). Take out. Similarly, the row address start position switching circuit 205 extracts a total of 11 bits (MA22,..., MA12) having MA12 as the LSB, and the row address start position switching circuit 206 has a total of 11 bits (MA23,. , MA13), and the row address start position switching circuit 207 fetches a total of 11 bits (MA24,..., MA14) with MA14 as the LSB as a row address.
[0151]
These row address start position switching circuits 204 to 207 are constituted by, for example, barrel shifters.
[0152]
The row address selector 203 selects and outputs one of four types of row addresses output from the row address start position switching circuits 204 to 207 according to a selection signal from the pattern decoder 202. The row address selected by the row address selector 203 is supplied to a row address / column address selector 208. The row address / column address selector 208 is also supplied with a column address. The lower 11 bits (MA12,..., MA02) of the DRAM logical address are always used as the column address.
[0153]
The row address / column address selector 208 selectively outputs a row address and a column address onto the memory address bus 33 at a timing designated by a control signal from the timing control circuit 125 in FIG.
[0154]
In the row address / column address multiplexer 123, a row address cutout operation by each of the row address start position switching circuits 204 to 207 is performed in parallel with the decoding operation of the RAS decoder 122. When the decoding result of the RAS decoder 122 is determined, one control parameter corresponding to the RAS line to be energized specified by the determined decoding result is read from the register file 201 and sent to the pattern decoder 202. . Then, the decoding operation by the pattern decoder 202 and the row address selecting operation of the row address selector 203 are executed according to the control parameters, whereby the row address to be used for DRAM access is determined.
[0155]
Here, it has been described that all the 11 bits of the row address (RA10: 0) are switched by the row address start position switching circuits 204 to 207 and the row address selector 203 in accordance with the RAS line. There is no need to switch bits.
[0156]
That is, in any case where the row address start position is MA11, MA12, MA13, and MA14, the six bits of MA14 to MA19 are used in common, and these bits can be excluded from the switching target. FIG. 15 shows an example of the correspondence between the CPU address and the row address in this case.
[0157]
In FIG. 15, only the lower 3 bits (RA2 to RA0) and the upper 2 bits (RA10, RA9) of the row address are to be switched. By doing so, the 6 bits of the CPU address MA14 to MA19 can be sent directly to the row address / column address selector 208 as the middle 6 bits (RA8 to RA3) of the row address, so that the row address start position switching circuit Each of 204 to 207 and the row address selector 203 can be realized only by a hardware configuration for 5 bits to be switched.
[0158]
As described above, the circuit configuration of the row address / column address multiplexer 123 in FIG. 14 can greatly reduce the required number of circuits. However, from the time when the decoding result of the RAS decoder 122 is determined to the time when the row address to be used for DRAM access is determined, the operation of the three circuit blocks (the operation of selecting and reading the control parameters to be used from the register file 201). , The decoding operation by the pattern decoder and the row address selecting operation by the row address selector 203). Therefore, there is a problem that a relatively large delay occurs in the row address / column address multiplexer 123.
[0159]
FIG. 16 shows a second circuit configuration example of the row address / column address multiplexer 123. The configuration shown in FIG. 16 is improved as follows to reduce the delay in the row address / column address multiplexer 123.
[0160]
That is, in the row address / column address multiplexer 123 of FIG. 16, instead of the pattern decoder 202 and the row address selector 203 of FIG. 14, six pattern decoders 202-1 to 202- corresponding to the RAS0 to RAS5 lines, respectively. 6, and six row address selectors 203-1 to 203-6 are provided. The pattern decoders 202-1 to 202-6 control the row address selection operations of the row address selectors 203-1 to 203-6 according to the RAS0 control parameters to the RAS5 control parameters of the register file 201, respectively.
[0161]
The row of the row address selectors 203-1 to 203-6 has one of the six types of row addresses (RAS0 row address to RAS5 row address) obtained by the row address selectors 203-1 to 203-6. There is provided a row address selector 209 for selecting one according to the decoding result of the RAS decoder 122.
[0162]
In this circuit configuration, in parallel with the decoding operation of the RAS decoder 122, the row address cutout operation by each of the row address start position switching circuits 204 to 207, the pattern decoders 202-1 to 202-6 and the row address selector 203-1 203-6 to the row address selection operation. Thus, six types of row addresses (RAS0 row address to RAS5 row address) corresponding to the RAS0 to RAS5 lines can be generated without waiting for the determination of the decoding result of the RAS decoder 122.
[0163]
When the decoding result of the RAS decoder 122 is determined, the row address corresponding to the RAS line to be energized specified by the determined decoding result is selected by the row address selector 209.
[0164]
Therefore, the circuit operation required from the determination of the decoding result of the RAS decoder 122 to the determination of the row address to be used for DRAM access is only the address selection operation by the final-stage address selector 209, and the internal delay is reduced. It is greatly reduced.
[0165]
In the configuration of FIG. 16, it is not necessary to switch all the bits of the row address, as in the case of FIG.
[0166]
FIG. 17 shows a specific circuit configuration of the page hit determination circuit 126 of FIG.
[0167]
As shown, the page hit determination circuit 126 includes a register file 301, a page hit determination CPU address register 302, a match determination circuit 303, a mask circuit 304, and a match determination mask position register 305.
[0168]
The register file 301 is an I / O register readable / writable by the CPU 11, and includes mask data (for specifying whether or not to match a condition for matching with a CPU address used for a page hit determination). “0” = mask, “1” = no mask) are set as control parameters corresponding to each of the RAS0-RAS5 lines.
[0169]
That is, in the page hit determination, the row address (page address) and the RAS decoding address other than the remaining addresses excluding the intra-page address in the CPU address (A31: 02), that is, the portion corresponding to the column address are removed. Address is targeted. Since the portion corresponding to the column address is not involved in the page hit determination, the determination result of each bit used as the column address needs to be masked with mask data. Here, masking means that the determination result of the corresponding bit is always matched.
[0170]
Actually, the mask data corresponding to each RAS line is not composed of all the bits of the column address, but is composed of 3-bit data indicating whether or not to mask each of A12, A11, and A10. This is because the match determination circuit 303 excludes bits lower than A10, which is always used as a column address, from the match determination regardless of the type of the DRAM bank, and determines only bits higher than A10 as targets of the match determination. This is because whether or not each of the three bits A12, A11, and A10 is used as a part of the column address differs depending on the type of the DRAM bank.
[0171]
For example, when a type 1 DRAM bank (the number of column address bits = 9 bits) is connected to the RAS0 line, of the three bits A12, A11, and A10, only A10 is used as a part of the column address. You. At this time, mask data “110” corresponding to the RAS0 line is set in the register file 301.
[0172]
One of the six mask data set in the register file 301 is read from the register file 301 and set in the coincidence determination mask position register 305. Which mask data is read is determined by the decoding result output of the RAS decoder 122. For example, when the RAS decoder 122 activates the RAS line, the mask data corresponding to the RAS line is read from the register file 301.
[0173]
The page hit determination CPU address register 302 holds 17 bits A26 to A11 of the CPU address (A31: 02) at the time of the previous memory access as the page hit determination CPU address. The contents of the page hit determination CPU address register 302 are updated according to the CPU address (A31: 02) used for the memory access at the time when a bank miss or a page miss occurs without a page hit. That is, when a bank miss or a page miss occurs, the timing control circuit 125 generates a register update signal. In response to this register update signal, the CPU address (A26 to A11) output on the CPU address bus at that time is latched by the page hit determination CPU address register 302. As a result, the contents of the page hit determination CPU address register 302 are changed to the CPU address at the time of the memory cycle in which the bank miss or the page miss has occurred.
[0174]
The match determination circuit 303 detects, for each bit, a match / mismatch between the CPU address (A26 to A11) at the time of the current memory access and the CPU address (A26 to A11) held in the page hit determination CPU address register 302. Then, 17-bit data indicating the detection results of A26 to A11 is output.
[0175]
The mask circuit 304 masks the detection result outputs of A12, A11, and A10 among the detection results of A26 to A11 in accordance with the mask data of the coincidence determination mask position register 305, and the detection result outputs after masking indicate all coincidence. Sometimes a page hit signal HIT is generated.
[0176]
In the coincidence determination mask position register 305, mask data corresponding to the RAS line to be energized is set. The contents of the match determination mask position register 305 are updated to mask data corresponding to the RAS line activated by the RAS decoder 122 when a bank miss or a page miss occurs without a page hit. That is, when a bank miss or a page miss occurs, the timing control circuit 125 generates a register update signal. In response to the register update signal, the mask data in the register file 301 selected by the RAS decoder 122 at that time is latched by the coincidence determination mask position register 305. As a result, the contents of the match determination mask position register 305 are changed to mask data corresponding to the RAS line activated at the time of the memory cycle in which the bank miss or page miss has occurred.
[0177]
As described above, in the system of this embodiment, the memory size of each of the plurality of DRAM banks is detected by the read / write compare test, and the size of the memory size is determined regardless of the physical mounting position of the DRAM banks. The arrangement order of the DRAM banks in the memory address space is determined according to the relationship. Therefore, no matter what type of additional memory is installed in any order, the optimal memory arrangement is automatically reset again, and the DRAM banks in the system are always arranged in the order of their memory size. Allocated from the youngest in the logical address space.
[0178]
Under such a memory arrangement, the RAS decoder 122 only needs to detect a match / mismatch between the memory address value from the CPU and the decoding condition for each RAS. Therefore, the hardware configuration of the RAS decoder 122 can be greatly simplified as compared with the related art, so that the delay in the RAS decoder is reduced and the memory access speed can be increased. Further, in this configuration, if the decoding conditions of the two different RAS lines are set to the same value, the two RAS lines can be simultaneously activated, so that application such as switching the access data width to twice is also possible.
[0179]
If a part of the address in the page is used as a decoding condition, word interleaving can be realized.
[0180]
【The invention's effect】
As described above, according to the present invention, decoding conditions of the RAS decoder can be simplified by optimally arranging DRAM banks in a system in a memory address space according to their memory sizes. Therefore, the RAS decoder only needs to detect the coincidence / mismatch between the memory address value from the CPU and the decoding condition for each RAS line, and the hardware configuration can be greatly simplified as compared with the related art.
[0181]
When such a configuration of the RAS decoder is employed, the page interleave architecture can be easily realized only by changing the decoding conditions set in the RAS decoder.
[0182]
Therefore, simplification of the RAS decoder and effective use of the interleave architecture can be achieved, and higher memory access speed can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a memory control logic in a system controller provided in the system of the embodiment.
FIG. 3 is a diagram showing a conversion operation from a CPU memory address space to a DRAM logical address space performed by an address conversion circuit included in the memory control logic of FIG. 2;
FIG. 4 is a diagram showing a DRAM memory map showing a state in which a plurality of DRAM banks provided in the system of the embodiment are rearranged in a DRAM logical address space in order of memory size.
FIG. 5 is an exemplary view showing decoding conditions of RAS lines connected to a plurality of DRAM banks provided in the system of the embodiment.
FIG. 6 is an exemplary view showing decoding conditions of each RAS line employed when implementing the page interleave architecture in the system of the embodiment.
FIG. 7 is an exemplary flowchart showing the procedure of an initialization process for memory control logic executed by an IRT routine when the system of the embodiment is turned on.
FIG. 8 is a view showing an example of the types of DRAM banks supported by the system of the embodiment.
FIG. 9 is an exemplary view showing an example of a memory configuration of a system memory mounted as standard on a system board of the system of the embodiment.
FIG. 10 is an exemplary view showing an example of a memory configuration of an additional memory installed in an extended memory slot provided in the system of the embodiment.
FIG. 11 is an exemplary view showing an example of another memory configuration of the additional memory mounted on the extended memory slot provided in the system of the embodiment.
FIG. 12 is a flowchart showing a procedure of a memory size detection process of each DRAM bank executed in the initialization process of the memory control logic of FIG. 7;
FIG. 13 is a circuit diagram showing an example of a specific configuration of a RAS decoder included in the memory control logic of FIG. 2;
FIG. 14 is a circuit diagram showing an example of a specific configuration of a row address / column address multiplexer included in the memory control logic of FIG. 2;
FIG. 15 is a diagram for explaining a row address switching operation of the row address / column address multiplexer of FIG. 14;
FIG. 16 is a circuit diagram showing another example of a specific configuration of the row address / column address multiplexer included in the memory control logic of FIG. 2;
FIG. 17 is a circuit diagram showing an example of a specific configuration of a page hit determination circuit included in the memory control logic of FIG. 2;
[Explanation of symbols]
11: CPU, 12: System controller, 13: System memory, 21, 22: Extended memory slot, 31: CPU local bus, 33: Memory address bus, 41, 42: Additional memory, 120: Memory control logic, 121: Address Conversion circuit, 122 RAS decoder, 123 row / column address multiplexer, 124 CAS generation circuit, 125 timing control circuit, 126 page hit determination circuit, 51 to 56 RAS decode circuit, 71 to 79 match detection Circuits, 81 to 89: mask circuit, 91: AND circuit, 201, 301: register file, 202: pattern decoder, 203: row address selector, 204 to 207: row address start position switching circuit, 208: row address / column address SEREC , 302 ... page hit determination CPU address register, 303 ... match determining circuit, 304 ... masking circuit, 305 ... matching determination mask location register.

Claims (8)

A plurality of memory banks to which a plurality of access control signals are respectively assigned and which can be accessed independently of each other;
A plurality of decoding conditions respectively corresponding to the plurality of access control signals are set, the presence or absence of a match between the decoding conditions and a memory address from the CPU is detected, and an access control signal line corresponding to the matched decoding condition is activated. An address decoder for selecting a memory bank
Means for detecting a memory size of each of the plurality of memory banks;
The plurality of memory banks are rearranged in the memory address space in the order of the memory size such that the larger the memory size is, the lower the memory address space of the CPU is. Memory relocation means for determining a memory address range to be
Means for determining a combination of two or more memory banks that can be page-interleaved according to the memory arrangement of the plurality of memory banks;
The decoding conditions of the access control signal lines corresponding to the memory banks belonging to the combination are changed so that the memory banks belonging to the combination belong to the entire address range of the entire memory banks so that the memory banks belonging to the combination are alternately accessed in page units. Means for determining in accordance with a bit string commonly existing in binary data indicating each memory address value and a predetermined bit string between an in-page address and a page designation address of each memory bank, and setting the address in the address decoder. A computer system, comprising: The address decoder,
A register group in which a plurality of bit strings indicating a plurality of decoding conditions respectively corresponding to the plurality of access control signal lines are set;
A plurality of decoding circuits respectively provided corresponding to the plurality of access control signal lines,
Each decoding circuit detects whether a bit string indicating a decoding condition of an access control signal line corresponding to the decoding circuit matches a memory address from the CPU, and activates the access control signal line when they match. The computer system of claim 1, wherein Each of the memory banks is a DRAM bank composed of a plurality of DRAM chips,
2. The computer system according to claim 1, wherein each of the access control signal lines is a row address strobe signal line commonly connected to a DRAM chip of the DRAM bank. The memory size detection means,
4. An address size detecting means for detecting at least one of a column address size and a row address size for each DRAM bank, and determining a memory size of each DRAM bank based on the detected address size. Computer system as described. Address output means for decomposing a memory address from the CPU into a row address and a column address corresponding to a DRAM bank to be accessed and outputting the same;
This address output means,
A register group in which a plurality of parameter values for specifying a cutout start position for cutting out a row address from the memory address for each of the RAS signal lines;
Means for selecting one parameter value from the register group in accordance with a row address strobe signal line activated by the address decoder, and cutting out a row address from the memory address in accordance with the selected parameter value. The computer system according to claim 3, wherein Address output means for decomposing a memory address from the CPU into a row address and a column address corresponding to a DRAM bank to be accessed and outputting the same; Prepared for
This address output means,
A register group in which a plurality of parameter values for specifying a cutout start position for cutting out a row address from the memory address for each of the RAS signal lines;
A plurality of row address extracting means for extracting a row address from the memory address according to a plurality of parameter values set in the register group;
Means for selecting one of the outputs of the plurality of row address extraction means in accordance with a row address strobe signal line energized by the address decoder, which is connected to a stage subsequent to the plurality of row address extraction means. The computer system according to claim 3, wherein: A reserved area for allocating a memory other than the plurality of DRAM banks is reserved in a memory address space of the CPU,
A memory address from the CPU is provided in accordance with a memory map of the CPU so that memory addresses allocated to the DRAM bank immediately before and immediately after the reserved area are provided in a preceding stage of the address decoder. Address conversion means for converting to a DRAM logical address dedicated to the DRAM bank;
4. The computer system according to claim 3, wherein the address decoder detects whether or not the DRAM logical address converted by the address conversion unit matches each of the decoding conditions. A page hit that holds the memory address from the CPU at the time of the previous memory access, compares the memory address with the memory address from the CPU at the next memory access, and determines whether there is a page hit according to the comparison result. 4. The computer system according to claim 3, further comprising a determination unit.

Images