JP3531762B2 - Transmitter and receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmitting apparatus and a receiving apparatus suitable for use in transmitting an MPEG transport stream via a transmission line conforming to IEEE-P1394.

[0002]

2. Description of the Related Art MPEG (Moving Picture Experts Gro)
up), which is often used, for example, MPEG
1 and MPEG2. In the MPEG1 system, although there is an upper limit, an arbitrary number of individual coded streams such as video and audio are multiplexed to form a program stream as a stream integrated into one set of programs. There is.

The MPEG2 system includes a system that forms a program stream as in the above-described MPEG1 system and a system that uses a plurality of programs as a transport stream as one stream.

By the way, on the transmission side of the MPEG2 system, PCR (Program Clock Reference) is inserted into the transport stream at regular intervals. In this PCR, in the receiving side, that is, in the MPEG system decoder including the video and audio decoders, the value of STC (System Time Clock) (reference synchronization information) which is the time reference is transmitted on the transmission side (encoder side). Set to the intended value,
Since this is information for calibration, the playback timing of each PCR in the transport stream on the receiving side is
It must correspond to the insertion timing of each PCR on the transmission side.

That is, for example, on the transmitting side, the PCR
Is inserted at times t1, t2, t3, ..., On the receiving side, when the first PCR is reproduced at time t1 + α, subsequent PCRs are time t2 + α,
It is necessary to reproduce at t3 + α, ....

[0006]

However, MPEG (MPEG2) is provided via a transmission line in which jitter cannot be predicted or a transmission line in which jitter cannot be absorbed, for example, a transmission line conforming to IEEE-P1394. In the case of transmitting the transport stream of the above, it is difficult for the receiving side to reproduce the PCR at the timing at which the above-described PCR should be reproduced, so that it is also difficult to accurately transmit the transport stream. .

The present invention has been made in view of such a situation, and enables PCR to be reproduced at a timing at which it should be originally reproduced.
The MPEG transport stream can be accurately transmitted via a transmission path conforming to P1394.

[0008]

The transmitting apparatus of the present invention is I
MPE via a transmission line compliant with EEE-P1394
A transmitting device for transmitting a G (Moving Picture Experts Group) transport stream, which comprises packetizing means for converting the transport stream into packets and outputting the packets to a transmission path (for example, the P1394 interface 4 shown in FIG. 1), PCR from Portstream
First PCR to detect (Program Clock Reference)
Detection means (for example, PCR detection circuit 5 shown in FIG. 1)
, A clock means for measuring absolute time (for example, the cycle timer 7 shown in FIG. 1), and a PC by the PCR detection means.
It is characterized by including an adding unit (for example, the sync time adding circuit 3 shown in FIG. 1) for adding the absolute time at the timing when R is detected to the packet.

The time counting means may be an IEEE-P1394 cycle timer. Further, the packetizing means can make the transport stream input during 125 μs specified by IEEE-P1394 into one packet. Furthermore, the adding means includes
During 125 μs specified by IEEE-P1394,
When there are a plurality of PCRs in the transport stream input to the packetizing means, the absolute time corresponding to each PCR can be added to the packet.

A receiving device according to the present invention is a receiving device for receiving a packet transmitted from the transmitting device according to any one of claims 1 to 4 through a transmission line conforming to IEEE-P1394. A converting means for converting the packet into a transport stream (for example, P1 shown in FIG. 3).
394 interface 11), second PCR detection means for detecting PCR from the transport stream output from the conversion means (for example, PCR detection circuit 20 shown in FIG. 3), and second PCR detection means. Based on the generated PCR, a generation unit that generates a clock (for example, the PLL circuit 23 illustrated in FIG. 3) and an absolute time detection unit that detects an absolute time from the transport stream output from the conversion unit (for example, The sync time detection circuit 14 shown in FIG. 3) and the supply means for supplying the PCR detected by the second PCR detection means to the generation means at the timing corresponding to the absolute time detected by the absolute time detection means. For example, the comparison circuit 1 shown in FIG.
7 and a latch circuit 19).

[0011]

In the transmitting apparatus of the present invention, the transport stream is packetized and output to the transmission line conforming to IEEE-P1394. On the other hand, PCR is detected from the MPEG transport stream, and the absolute time at the time when it is detected is added to the packet. Therefore, on the receiving side, by referring to the absolute time added to the packet, the PCR can be reproduced at the timing when it should be reproduced.
A transport stream conforming to 394 can be used to accurately transmit the transport stream.

In the receiving apparatus of the present invention, the IEEE-
A packet transmitted via a transmission path compliant with P1394 is converted into a transport stream, and PCR is detected from the transport stream. PL
The L circuit 23 generates a clock based on the detected PCR. Further, the absolute time is detected from the transport stream, and the detected PCR is supplied to the PLL circuit 23 at the timing corresponding to the absolute time. Therefore, since the PCR is regenerated at the timing when it should be regenerated, the clock generated by the PLL circuit 23 is locked to the clock on the transmission side. As a result, via a transmission line compliant with IEEE-P1394,
It becomes possible to accurately receive the transport stream.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the transmitting apparatus of the present invention. A 4 Mbps MPEG transport stream encoded by an encoder (not shown) is supplied to the serial / parallel converter 1 and the PCR detection circuit 5. The serial / parallel converter 1 and the PCR detection circuit 5 are also supplied with a 4 MHz clock. In addition, this 4
The MHz clock is supplied to the counter 8 as well as the serial / parallel converter 1 and the PCR detection circuit 5.

The serial / parallel converter 1 has a frequency of 4 MHz.
In synchronism with the clock of, the transport stream as serial data is converted into a transport stream as, for example, 32-bit parallel data, and FI
FO (First In First Out) memory 2 is supplied. The FIFO memory 2 temporarily stores the transport stream from the serial / parallel converter 1, and when a read request signal is supplied from the sync time giving circuit 3, the stored transport stream is sent to the sync time giving circuit 3. It is designed to output.

The sync time giving circuit 3 responds to the read request signal from the P1394 interface 4 in response to the read request signal.
The transport stream is read from the FIFO memory 2 and supplied to the P1394 interface 4. 32 for P1394 interface 4
The transport stream in the form of bit parallel data is referred to as IEEE-P1394 (hereinafter, referred to as P139
(Abbreviated as “4”) is made into packets in 125 μs unit defined by the clock, that is, the transport stream input thereto is defined as 1 packet during 125 μs, and P139 is set.
The data is output to a transmission line compliant with No. 4 (hereinafter, appropriately referred to as P1394 transmission line).

The PCR detection circuit 5 inputs 4 to it.
It operates in synchronization with the clock of MHz and detects PCR from the transport stream. P
When the PCR is detected, the CR detection circuit 5 detects the latch circuit 6
The detection signal is output to. Upon receiving the detection signal from the PCR detection circuit 5, the latch circuit 6 latches the absolute time output by the cycle timer 7 as a sync time (Sync Time) and outputs it to the sync time giving circuit 3. There is. When the sync time giving circuit 3 receives the sync time from the latch circuit 6, the sync time giving circuit 3 outputs the sync time to the P1394 interface 4 to thereby obtain the absolute time (sync time) at the timing when the PCR is detected from the transport stream. It is designed to be added (added) to a packet.

The cycle timer 7 is adapted to start measuring the absolute time when the power of the apparatus is turned on. The absolute time measured by the cycle timer 7 is output to the latch circuit 6. The cycle timer 7 is adapted to measure an absolute time in synchronization with a clock of 24.576 MHz, for example.

Here, the device connected to the transmitter of FIG. 1 through the P1394 transmission line is the cycle timer 7
Each has a block corresponding to, and when any of the power supplies is turned on, the absolute time measurement is started. When establishing a link with another device, each device decides a parent, and when the parent is decided, it synchronizes the absolute time measured by the parent with the absolute time measured by the parent. Has been done. That is, P1
A cycle master (Cycle Master) that is a node that regulates the cycle timer of the entire network defined in 394
Master) broadcasts a cycle start packet in which the value of the cycle timer inside the cycle master is described every 125 μs, and each node receives this, and the respective cycle timers are sent to the cycle timer inside the cycle master. It is designed to be updated to the value of. Therefore, the cycle timer 7 constituting the transmitting apparatus of FIG. 1 and the cycle timer 18 constituting the receiving apparatus shown in FIG. 3 which will be described later measure the same absolute time.

The counter 8 has a clock of 4 MHz.
When the clock is input, the count value is incremented by 1 and output to the P1394 interface 4. When the P1394 interface 4 creates one packet every 125 μs, it outputs a reset signal to the counter 8 and outputs the count value output by the counter 8 as the packet length to the P1394 transmission line. It is designed to be added to the beginning of. In addition, the counter 8 is P1
When a reset signal is received from the 394 interface 4, the count value is reset to 0. The count value is incremented by 1 when a 4 MHz clock is input for 8 clocks, and therefore represents the packet length in bytes.

Next, the operation will be described with reference to the timing chart of FIG. When a transport stream which is serial data is input to the serial / parallel converter 1, the serial / parallel converter 1 converts the serial / parallel transport data into 32-bit parallel data and writes the data into the FIFO memory 2. FI
The transport stream written in the FO memory 2 is supplied to the P1394 interface 4 via the sync time giving circuit 3. In the P1394 interface 4, the transport stream that is made into 32-bit parallel data is packetized in 125 μs units. Then, the packet length output by the counter 8 is added to the packet, and the packet is output to the P1394 transmission line.

That is, as shown in FIG.
The transport stream written in the IFO memory 2 is transmitted as a packet P1 in the next cycle T2,
The transport stream written in the FIFO memory 2 in the cycle T2 is transmitted as the packet P2 in the next cycle T3.

Here, in the transport stream,
As described above, PCR is inserted regularly. The 32-bit data that is considered to be parallel data is called 1 quadlet, but the PCR is described over 2 quadlets.

Also, during 125 μs, the transport stream of 4 Mbps is input to the P1394 interface 500 by 500 bits, so that one packet is composed of 15 or 16 quadlets.

The PCR detection circuit 5 detects PCR from the transport stream and outputs a detection signal to the latch circuit 6. Upon receiving the detection signal, the latch circuit 6 latches the absolute time output by the cycle timer circuit 7. Therefore, the absolute time defined by P1394 at the timing of the beginning of the PCR is latched in the latch circuit 7. This absolute time is output as a sync time from the latch circuit 6 to the sync time giving circuit 3 and added to the packet output by the P1394 interface 4.

That is, for example, as shown in FIG.
The absolute time corresponding to the beginning (start) position of the PCR (the hatched portion in the drawing) inserted between the two is included in the packet P1 as the sync time.

Therefore, even if the jitter on the P1394 transmission line is unpredictable or the jitter cannot be absorbed, the receiving side (receiving device) is based on the time indicated by the sync time. Then, by reproducing the PCR, it becomes possible to generate a clock synchronized with the transmitting device.

As described above, the transport stream is a stream of a plurality of programs. Therefore, PCRs of a plurality of programs are inserted in a cycle of 125 μs instead of one program. It may have been. In such a case, the absolute time indicating all the head positions is added to the packet as the sync time.

Next, FIG. 3 shows an example of the configuration of a receiving device for receiving a packet transmitted from the transmitting device shown in FIG. 1 through the P1394 transmission path. P1394
The interface 11 is adapted to convert a packet received via the P1394 transmission line into 32-bit parallel data. This data is supplied to the FIFO memory 12, the sync time detection circuit 14, and the PCR detection circuit 20 together with the write signal.

When the FIFO memory 12 receives data together with a write signal from the P1394 interface 11, the FIFO memory 12 temporarily stores the data. Then, the FIFO memory 12 outputs the stored data to the parallel / serial converter 13 when receiving the read signal from the parallel / serial converter 13.

The parallel / serial converter 13 is a PLL
In synchronization with the 4 MHz clock output from the circuit 23, F
The transport stream as 32-bit parallel data, which is the data read from the IFO memory 12, is converted into a transport stream as serial data, and is output to an MPEG decoder (not shown).

The sync time detection circuit 14 uses P1394.
The interface 11 detects the sync time from the data supplied together with the write signal, and the adder circuit 15
It is designed to output to. The adder circuit 15 is supplied with the sync time from the sync time detection circuit 14 and also with the delay time (delay) stored in the delay storage circuit 16.
Compares the sync time with the delay time, and compares the result with the comparison circuit 17
It is designed to output to.

The delay time stored in the delay memory circuit 16 is a little longer than the sum of the delay in the P1394 transmission line and the delay due to the processing in the receiving device, for example, about several hundred ms. ing.

The cycle timer 18 is associated with the cycle timer 7 of the transmitter shown in FIG. 1, and therefore outputs the absolute time. The comparison circuit 17 compares the output of the addition circuit 15 with the output of the cycle timer 18,
When the two match, a match signal is output to the latch circuit 19. The latch circuit 19 latches the output of the PCR detection circuit 20, and when receiving the coincidence signal from the comparison circuit 17, outputs the latched value to the subtraction circuit 21.

The PCR detection circuit 20 detects the PCR from the data supplied together with the write signal from the P1394 interface 11 and outputs it to the latch circuit 19. Therefore, the latch circuit 19 outputs the PCR to the subtraction circuit 21 when the time obtained by adding the delay time to the sync time matches the absolute time measured by the cycle timer 18.

The subtraction circuit 21 has a latch circuit 19 to P
In addition to the CR being supplied, the count value is supplied from the counter 22. The counter 22 is a PLL
The count value is incremented by 1 at the timing of the clock output from the circuit 23. The subtraction circuit 21 receives the P supplied from the latch circuit 19.
The count value of the counter 22 is subtracted from CR, and the subtraction result is supplied to the PLL circuit 23. The PLL circuit 23 advances the phase of the output clock when a positive value is input, and delays the phase of the output clock when a negative value is input. That is, the PLL circuit 23 advances the phase of the output clock when the PCR is larger than the count value of the counter 22, and advances the phase of the output clock when the PCR is smaller than the count value of the counter 22. It is designed to delay the phase.

Next, the operation will be described with reference to the timing chart of FIG. The packet transmitted through the P1394 transmission line is received by the P1394 interface 11, and the data portion (a portion other than the packet length) of the packet is taken out to form a transport stream as 32-bit parallel data. Is output. The data output from the P1394 interface 11 is supplied to the FIFO memory 12, the sync time detection circuit 14, and the PCR detection circuit 20. The data from the P1394 interface 11 is temporarily stored in the FIFO memory 12 and output to the parallel / serial converter 13. The parallel / serial converter 13 converts the transport stream as 32-bit parallel data from the FIFO memory 12 into serial data in synchronization with the 4 MHz clock supplied from the PLL circuit 23, and outputs the serial data.

On the other hand, in the sync time detection circuit 14, P
The sync time is detected from the output of the 1394 interface 11 and output to the adder circuit 15. Adder circuit 15
Then, a predetermined delay time is added to the sync time and output to the comparison circuit 17. The comparison circuit 17 includes an addition circuit 15
And the output of the cycle timer 18 are compared with each other, and if they match each other, a match signal is output to the latch circuit 19.

Further, in the PCR detection circuit 20, P139
4 PCR is detected from the output of interface 11,
It is output to the latch circuit 19 and latched. When the latch circuit 19 receives the coincidence signal, it latches the PCR.
Is output to the subtraction circuit 21. That is, as shown in FIG.
PCR is output to the subtraction circuit 21 at a time delayed by a predetermined time from the time indicated by the sync time.

The subtraction circuit 21 converts the PCR to the counter 22.
The count value of is subtracted, and the subtracted value is output to the PLL circuit 23. The PLL circuit 23 changes the phase of the clock to be output according to the value from the subtraction circuit 21, so that the clock on the receiving side is locked to the clock on the transmitting side. This clock is supplied to the parallel / serial conversion circuit 13 and the counter 22.

As described above, the transmitting side and the receiving side have the same absolute time. Further, when the receiving side receives a packet including the sync time, a predetermined delay time from the sync time is received. Since the PCR is played back at a time delayed by only, the receiving side can play back the transport stream at the same speed as the sending side. That is,
An MPEG transport stream can be accurately transmitted via the P1394 transmission path.

[0041]

As described above, according to the present invention, the IEEE
-It becomes possible to accurately transmit and receive a transport stream using a transmission path compliant with P1394.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a transmission apparatus of the present invention.

FIG. 2 is a timing chart explaining the operation of the transmission device of FIG.

FIG. 3 is a block diagram showing a configuration of an embodiment of a receiving apparatus of the present invention.

FIG. 4 is a timing chart explaining the operation of the receiving apparatus of FIG.

[Explanation of symbols]

1 Serial / parallel converter 2 FIFO memory 3 Sync time giving circuit 4 P1394 interface 5 PCR detection circuit 6 Latch circuit 7 cycle timer 8 counter 11 P1394 interface 12 FIFO memory 13 Parallel / serial converter 14 Sync time detection circuit 15 Adder circuit 16 delay memory circuit 17 Comparison circuit 18 cycle timer 19 Latch circuit 20 PCR detection circuit 21 Subtraction circuit 22 counter 23 PLL circuit

Continuation of the front page (56) Reference JP-A-6-97927 (JP, A) JP-A-6-303254 (JP, A) JP-A-8-79744 (JP, A) JP-A-7-46592 (JP , A) JP 7-321849 (JP, A) JP 7-326127 (JP, A) JP 8-97807 (JP, A) JP 8-97837 (JP, A) JP 8-195723 (JP, A) International Publication 95/27977 (WO, A1) International Publication 95/19670 (WO, A1) Scott Smyers, with isochronous transfer function for multimedia data, Nikkei Electronics, Japan, Nikkei BP, July 4, 1994, No. 612, p. 152-163 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N ^7/ 00-7/088 H04N 7/12 H04N ^7/ 24-7/68 H04L ^7/ 00-7/10 JSTPlus file ( JOIS) IEEE XPlore

Claims (5)

(57) [Claims] 1. An MPEG (Moving Picture Experts Group) is provided via a transmission line compliant with IEEE-P1394.
And a packetizing means for converting the transport stream into packets and outputting the packets to the transmission path, and a PCR (Program Cl) from the transport stream.
lock detection), a first PCR detecting means, a time measuring means for measuring an absolute time, and an adding means for adding the absolute time to the packet at the timing when the PCR is detected by the PCR detecting means. A transmitting device characterized by the above. 2. The timekeeping means is IEEE-P1394.
2. The transmitter according to claim 1, wherein the transmitter is a cycle timer. 3. The packetizing means is IEEE-P1.
The transmission device according to claim 1, wherein the transport stream input during 125 μs defined by 394 is made into one packet. 4. The adding means is IEEE-P1394.
When a plurality of the PCRs are present in the transport stream input to the packetizing means within 125 μs defined by, the absolute time corresponding to each PCR is added to the packet. The transmitter according to claim 3, wherein the transmitter is a transmitter. 5. A receiving device for receiving a packet transmitted from the transmitting device according to claim 1 through a transmission line conforming to IEEE-P1394, wherein the packet is Converting means for converting into a transport stream, second PCR detecting means for detecting PCR from the transport stream output from the converting means, and the PCR detected by the second PCR detecting means
Based on the generation means for generating a clock, the transport stream output from the conversion means, the absolute time detection means for detecting the absolute time, the absolute time detected by the absolute time detection means A receiving device comprising: a supply unit configured to supply the PCR detected by the second PCR detection unit to the generation unit at a corresponding timing.