JP3529324B2 - Tag conversion device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tag conversion device, and more particularly to a method for combining input cells to generate a packet, converting the tags of the generated packets as needed, and then decomposing the cells again. The present invention relates to a tag conversion device that outputs the output.

[0002]

2. Description of the Related Art For example, a LAN (Local Area Network)
In the trunk system (backbone) of networks such as A, due to the increasing demand for higher communication speed, in recent years A
An ATM-LAN using an ATM (Asynchronous Transfer Mode) switch is in the spotlight.

In the ATM-LAN, a virtual channel (V
C: Virtual Channel) is set and communication is performed. Here, with the virtual channel, for example, data is transferred (through cut) without executing a process that causes a transmission delay such as checking a destination address of data, which is performed by a router. High-speed transmission is possible.

[0004]

Such an ATM-L
In the AN, packets transmitted on the LAN are decomposed into cells having a short data length and then transmitted. Therefore, at the time of routing, the cells are combined and packetized, and after the routing processing, the tag exchanging device is decomposed again into cells. Need to be used.

By the way, the ATM switch may be duplicated in order to improve the reliability of the system. In the past, however, the tag switch was not designed in such a case, so that the system switching is performed. However, there is a problem that packet loss and inversion of the order of cells in the same connection may occur.

Further, when connection merging in which the input-to-output relationship is plural to singular, cells having different destinations are mixed and the system switching operation may not operate reliably. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide a tag conversion device which does not cause cell loss or sequence inversion even when the system is switched. .

Another object of the present invention is to provide a tag conversion device that operates reliably even when the system is switched while connection merging is being performed.

[0009]

In order to solve the above problems, the present invention combines the input cells shown in FIG. 1 to generate a packet, and converts the tag of the generated packet as necessary. Then, in the tag conversion device that decomposes again into cells and outputs the cells, the first packet combining unit 1 that combines the input cells to generate the first packet and the second packet that combines the input cells Second packet synthesizing means 2 for generating the first packet and selection information indicating which of the first and second packets is selected when switching between the active system and the standby system is requested. A selection information generating means 3, a first packet decomposing means 4 for decomposing the first packet to generate a first cell, and a second packet decomposing the second packet for generating a second cell. Packet decomposing means 5 and the first First and cell storage unit 6, a second cell storing means for storing separately the second cell for each type of the cell to separate storage cell for each type of the cells 7
A first cell reading means 8 for sequentially reading and outputting the first cells stored in the first cell storage means 6 for each type, and a first cell reading means 8 for storing the first cells in the second cell storage means 7. When the selection information is generated by the second cell reading means 9 for sequentially reading out and outputting the second cells for each type, and the first information if the selection information is generated by the selection information generating means 3.
And a timing adjusting means 10 for adjusting the read timing of the second cell reading means 8 and 9, and a tag conversion device is provided.

Here, the first packet synthesizing means 1 synthesizes the input cells to generate a first packet. The second packet synthesizing means 2 synthesizes the input cells to generate a second packet. The selection information generation means 3 generates selection information indicating which of the first packet and the second packet is selected when switching between the active system and the standby system is requested. The first packet decomposing unit 4 decomposes the first packet to generate a first cell. The second packet decomposing means 5 decomposes the second packet to generate a second cell. The first cell storage unit 6 stores the first cells by classifying them into cell types. Second cell storage means 7
Stores the second cell by dividing it by the type of the cell.
The first cell reading unit 8 sequentially reads out and outputs the first cells stored in the first cell storage unit 6 for each type. The second cell reading means 9 sequentially reads out and outputs the second cells stored in the second cell storage means 7 for each type. The timing adjusting means 10
When the selection information is generated by the selection information generating means 3, the read timings of the first and second cell reading means 8 and 9 are adjusted.

In addition, in a tag conversion device that combines input cells to generate a packet, converts the tags of the generated packets as necessary, and then decomposes them into cells and outputs the cells. A first packet synthesizing means for synthesizing the input cells, a second packet synthesizing means for synthesizing the input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which of the first and second packets is to be selected, and the first packet is stored separately for each type of the packet. A first packet storage means, a second packet storage means for storing the second packet separately for each packet type, and a first packet stored in the first packet storage means. First packet reading means for sequentially reading each type, second packet reading means for sequentially reading the second packet stored in the second packet storing means for each type, and selection by the information selecting means When information is generated, timing adjusting means for adjusting the read timing of the first and second packet reading means, and a first cell for decomposing the first packet to generate and outputting a first cell There is provided a tag conversion device comprising: a first packet decomposing unit and a second packet decomposing unit that decomposes the second packet to generate and output a second cell.

Here, the first packet synthesizing means synthesizes the input cells to generate a first packet. Second
Packet synthesizing means for synthesizing the input cells
Packet is generated. The selection information generation means generates selection information indicating which of the first packet and the second packet is selected when switching between the active system and the standby system is requested. The first packet storage means stores the first packet for each type of the packet. The second packet storage means stores the second packet by classifying the type of the packet. The first packet reading means is the first
The first packet stored in the packet storage means is sequentially read for each type. The second packet reading means sequentially reads the second packets stored in the second packet storage means for each type. The timing adjusting means adjusts the read timing of the first and second packet reading means when the selection information is generated by the information selecting means. The first packet decomposing means is
The first packet is disassembled to generate and output the first cell. The second packet disassembling unit disassembles the second packet to generate and output a second cell.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a principle diagram for explaining the operation principle of the present invention. In this figure, the first packet synthesizing means 1 synthesizes the input cells to generate a first packet.

The second packet synthesizing means 2 synthesizes the input cells to generate a second packet. When the switching between the active system and the standby system is requested, the selection information generating means 3 generates the selection information indicating which of the first packet and the second packet is selected, and the first packet synthesizing means 1 And the generated selection information is supplied to the second packet combining means 2.

The first packet disassembling means 4 disassembles the first packet output from the first packet synthesizing means 1 to generate a first cell. Second packet decomposing means 5
Generates a second cell by decomposing the second packet output from the second packet synthesizing means 2.

The first cell storing means 6 stores the first cells supplied from the first packet disassembling means 4 by classifying them. The second cell storage unit 7 stores the second cells supplied from the second packet decomposing unit 5 for each type.

The first cell reading means 8 sequentially reads the first cells stored in the first cell storage means 6 for each type and outputs them. Second cell reading means 9
Reads out the second cells stored in the second cell storage means 7 in sequence for each type and outputs them.

The timing adjusting means 10 adjusts the read timings of the first cell reading means 8 and the second cell reading means 9 when the selection information is generated by the selection information generating means 3.

In the following, the first packet synthesizing means 1, the first packet disassembling means 4, the first cell storing means 6, and the first cell reading means 8 will be referred to as system 0,
Further, the second packet synthesizing means 2, the second packet disassembling means 5, the second cell storing means 7, and the second cell reading means 9 are referred to as 1 system.

Next, the operation of the above principle diagram will be described. Now, for example, there are three types of packets, A, B, and C, which have the same IP address, and the cells forming these are a1, a2, a3, b1, b2, b3, and c1, c2, c3. And And the first or second
C1, a1, b for the packet synthesizing means 1, 2 of
It is assumed that cells are input in the order of 1, c2, b2, a2, a3, c3, and b3, and switching from the 0 system to the 1 system is requested in the cell b1. When system switching is requested, a predetermined bit added to the header of each cell changes. Therefore, in this example, b1
Bits will be changed in the subsequent cells.

The first packet synthesizing means 1 and the second packet synthesizing means 2 synthesize cells by referring to the header added to the input cells and packetize them. In the present example, the combined packet is output in the order of A, C and B.

At this time, the selection information generating means 3 refers to the above-mentioned bit of the head cell forming the packet and generates and adds the selection information for the packet. For example, in the present example, the request is made in the cell b1, and this is the head cell of the packet B, so the packet B is provided with information for selecting the 1-system.

The first packet decomposing means 4 and the second packet decomposing means 5 receive the first and second packets, respectively, and decompose them into cells. At this time, if the selection information is added to the packet, the selection information is inherited to each cell after disassembly. In the present example, cells b1 and b output from the second packet combining means 2
Selection information is added to 2 and b3.

The first cell storing means 6 and the second cell storing means 7 classify the first and second cells output from the first packet disassembling means 4 and the third packet disassembling means 5, respectively. (For example, VC of the packet) is divided and sequentially stored in different areas. In this example, a1, a
2, a3, b1, b2, b3 and c1, c2, c
3 are stored in different areas in this order.

The first cell reading means 8 and the second cell reading means 9 are composed of the first cell storage means 6 and the second cell reading means 9, respectively.
The cells stored in the cell storage means 7 according to the type are sequentially read and output. At that time, when the state of addition of the selection information changes in comparison with the immediately preceding cell, the timing adjustment means 10 suspends the reading of the cell and adds the selection information to another type of cell. Prioritize reading of cells whose status has not changed.

In the present example, first, cells a1, a2, a
3 is read, and when the cell b1 is read next, the selection information of the cell b1 is changed (added).
Therefore, the cells c1, c2 and c3 are preferentially read.

When the selection information changes, the timing adjusting means 10 starts the output of the changed cell after a certain time has elapsed after the output of the cell before the change ends. Therefore, in this example, cells b1, b2, b3 are
It will be read and output after a certain period of time has elapsed. As a result, cell loss can be prevented even when the processing speeds of the 0-system and 1-system do not match.
That is, when the cells b1, b2, b3 are read without waiting for a certain period of time and the output of the cells of the 1-system is ahead of that of the 0-system, the cells near the beginning (for example, the cells Since it is assumed that b1) has already been output, such a situation can be avoided.

Next, an embodiment of the present invention will be described. FIG. 2 is a diagram showing an overview of the entire network system including the tag conversion device of the present invention. In this figure, the terminal devices 20-1 to 20-3 and the terminal device 21-
Each of 1 to 21-3 is composed of, for example, a personal computer or the like, and exchanges information according to the operation of each user.

The switches 22 and 23 are used for the terminal device 20-1.
20-3 and 21-1 to 21-3 are grouped so that information can be exchanged between the terminal devices belonging to the group. The switches 22 and 23 are
ATM by converting the packets transmitted from each terminal device into cells
The packet is supplied to the switch 24, the cells supplied from the ATM switch 24 are combined into a packet, and the packet is supplied to the corresponding terminal device.

The ATM switch 24 is composed of the switches 22 and 2
The process of selecting the corresponding switch is performed by referring to the header added to the cell supplied from No. 3. The ATM switch 24 is assumed to be duplicated to ensure reliability.

The tag conversion device 25 includes an ATM switch 24.
The cells received by are combined to generate a packet, the tag of the obtained packet is converted as necessary, and then the packet is re-cellized and output.

Next, referring to FIG. 3, the tag conversion device 25
A detailed configuration example of the above will be described. FIG. 3 is a diagram showing a detailed configuration example of the tag conversion device 25. As shown in this figure, the tag conversion device 25 includes conversion units 40, 41, and
It is configured by the control unit 42. In addition, switch 4
3, 44 are arranged on the ATM switch 24 side.
Further, since the conversion units 40 and 41 and the switches 43 and 44 have the same configuration, only the conversion unit 40 and the switch 43 will be described as an example.

The conversion unit 40 includes a selector 40a, an ACT addition unit 40b, a packetization unit 40c, and an ACT addition unit 40.
d, a packet buffer 40e, an IP switch 40f, a cell assembling unit 40g, an ACT adding unit 40h, and a cell buffer 40i.

Here, the selector 40a includes a switch 43.
Alternatively, one of the cells supplied from the switch 44 is selected and input. The ACT addition unit 40b sets the ACT bit of the cell to the state of "1" when the self is the active system, and sets the ACT bit of the cell to the state of "0" when the self is the standby system.

The packetizing section 40c has an ACT adding section 40.
The cells output from b are combined to generate a packet.
The ACT addition unit 40d acquires the ACT bit of a predetermined cell forming the packet, and the AC of the packet itself.
Add as T bits.

The packet buffer 40e stores the packet to which the ACT bit is added. IP switch 40f
Executes IP switching processing and packet protocol conversion processing.

The cell conversion section 40g decomposes the packet supplied from the IP switch 40f to generate a cell. AC
The T addition unit 40h adds the ACT bit added to the packet to each cell included in the packet.

The cell buffer 40i has an ACT addition unit 40.
The cells input from h are stored separately for each cell type, read in a fixed order, and output. Switch 43
Is composed of a selector 43a, and the conversion unit 4
A cell output from either 0 or 41 is selected and output.

The control unit 42 controls each unit of the conversion units 40 and 41. Next, the operation of the above embodiment will be described. In the following, the operation of the 0-system will be mainly described and the operation of the 1-system will be supplemented as appropriate.

The selector 40a selects the cell input from either the switch 43 or the switch 44 and supplies it to the ACT addition section 40b. ACT addition section 40b
Sets the ACT bit of the input cell under the control of the control unit 42. The ACT addition unit 40b and the ACT
The adding unit 41b adds the contradictory ACT bits. That is, when one sets the ACT bit to "1", the other sets the ACT bit to "0".

For example, the cells Aa1, Aa2, Ba1, ... Shown in FIGS.
b and the ACT addition unit 41b, and the active system is switched from the conversion unit 40 to the conversion unit 41 in the cell Bb1, the ACT addition unit 40b sets the ACT bits of the cells Aa1 to Ab4 to "1". Then
Subsequent cells are set to the state of "0". Also, AC
The T addition unit 41b sets the ACT bits of the cells Aa1 to Ab4 to the state of "0", and sets the subsequent cells to the state of "1". Here, the cell in which the ACT bit is "1" is surrounded by an ellipse, and the ACT bit is "0".
The cells of are surrounded by a rectangle. Further, the type of packet is determined by the IP address added to the packet.

The packetizing unit 40c combines the input cells into packets by referring to the headers thereof. In the example of FIG. 4, the packet A is combined from the cells Aa1, Aa2 and Aa3, and the packet B is combined from the packets Ba1 and Ba2.

The ACT adding section 40d acquires the ACT bit added to a predetermined cell (for example, the head or end cell) forming the combined packet, and adds it as the ACT bit of the packet itself. Since different ACT bits are added to the same cell in the conversion unit 40 and the conversion unit 41, different ACT bits are similarly added to the same packet.

The packet buffer 40e stores the packet to which the ACT bit is added, and reads and supplies the packet at a predetermined timing in response to a request from the IP switch 40f.

In the packetizing section 40c, for example,
Since the synthesizing process is executed from the packet which the first cell arrives first, the packets stored in the packet buffer 40e have the ACT bit of "1" and the packet of "0" as shown in FIG. Some things will be mixed.

The IP switch 40f executes an IP switching process or a packet protocol conversion process and supplies it to the cell assembling unit 40g. The cell conversion unit 40g decomposes the packet into cells again. That is, as shown in FIG. 4A, for example, the packet Aa is decomposed into cells Aa1, Aa2, Aa3.

The ACT adding section 40h acquires the ACT bit added in packet units and adds it to each cell forming the packet. As a result, the ACT bits of all the cells forming the packet whose ACT bit is "1" are "1".

The cell buffer 40i classifies the input cells according to their types and stores them in the corresponding area. For example, as shown in FIG. 5, the input cell is VC (Virtua
l Channel) and stored in different areas. Here, when connection merging is not performed, the IP address added to the packet and the VC match, so that the cells stored in each area of the cell buffer 40i are from the packet of the same IP address. It is a generated cell.

The cells thus stored for each VC are read and output in a fixed order. For example, in the example of FIG. 5, the cell whose VC is A (cells Aa1, Aa2
Etc.) is read first, and then the cells (cells Bb1, Bb2, etc.) whose VC is B are read. Here, when the state of the ACT bit of the cell to be read changes compared with the state of the cell immediately before that, the reading of the cell is stopped and the cell related to the next VC is read. That is,
In the example of FIG. 5, since the ACT bit of the cell Ac1 next to the cell Aa6 has changed, the reading of that cell is stopped and the cell Ba1 whose VC is B is read.

When all the cells before the change of the ACT bit are read, the reading is stopped. Then, the cell buffer that has stopped reading notifies the control unit 42 of that fact. The control unit 42 uses the cell buffer 40i
When a predetermined time has elapsed after receiving the read stop notifications from both the cell buffer 41i and the cell buffer 41i, the cell readings of both cell buffers 40i and 41i are simultaneously started.

It should be noted that the cell reading is restarted after a lapse of a certain time (a time expected to finish the reading of the cell buffer 40i and the cell buffer 41i) after the active system switching request is made. May be.

Cell buffer 40i and cell buffer 4
The cell output from 1i is A by the selector 43a.
Only those whose CT bit is "1" are selected and output.

FIG. 6 is a diagram showing an example of the operation of the selector 43a. As shown in this figure, the selector 43a is
Of the cells input from the cell buffer 40i and the cell buffer 41i, the one having the ACT bit of "1" is selected and output.

According to the above embodiment, the ACT of the predetermined cell forming the packet in the ACT adding section 40d.
Since the bit is inherited as the ACT bit of the entire packet, the information added to the packet can be uniquely and easily determined.

Further, when reading cells in the cell buffer 40i and the cell buffer 41i, after reading all the cells before the ACT bit is changed, the changed cells are read after a lapse of a certain time. It is possible to prevent cell loss. This state is shown in FIG.
Will be described in detail. As shown in FIGS. 7A and 7B,
When the switching of the ACT bit occurs, the cell buffer 4
All cells before the ACT bit stored in 0i and 41i change are discharged, and the cells after the ACT bit change are read after a predetermined time has elapsed. Further, the switches 43 and 44 are, as shown in FIG.
Before the ACT bit is changed, the cell from the old active system is selected, and after the buffer is completely discharged, both systems are deselected, and when the output of a new cell is started, the new active system is selected. Will be selected.

In the above embodiment, in the cell buffer 40i and the cell buffer 41i, the cell A
Although the ejection process is performed according to the change of the CT bit, the same process can be performed in the packet buffers 40e and 41e. The operation in such a case will be described with reference to FIGS.

The cell input from the selector 40a is A
The ACT bit is added in the CT adding unit 40b and supplied to the packetizing unit 40c. Packetizing unit 40c
Composes a packet by referring to the header added to the cell.

The ACT adding unit 40d is a packetizing unit 40d.
The ACT bit of a predetermined cell forming the packet is acquired from the packet supplied from c, and this is added as the ACT bit of the packet itself.

The packet buffer 40e stores the packet in V
It is classified for each C or PDP and stored in the corresponding area.
FIG. 8 is a diagram showing an example of packets stored in the packet buffer 40e. In the example in this figure, the packet is
It is classified and stored according to the VC.

The packet stored in the packet buffer 40e is read in VC units. If the ACT bit of a packet changes during reading, the reading of the packet associated with that VC is stopped and the packet associated with the next VC is read. And ACT
When the reading of all the packets before the bit change is completed in both packet buffers 40e and 41e, the reading of the next packet (the packet after the change of the ACT bit) is stopped after the reading is stopped for a certain time τ. Resume reading.

In the example of FIG. 8, the reading of the packet AC is started after a predetermined time τ has elapsed since the reading of the packet Ba from the packet buffer 40e.
The time τ is determined in consideration of the delay expected to occur in the processing after the IP switch 40f.
For example, when the delay occurring after the IP switch 40f is d, τ is set so that τ> d. By setting in this way, it is possible to prevent cell loss even if cell (or packet) delay occurs due to subsequent processing.

The IP switch 40f executes the IP switching process and the packet protocol conversion process, and outputs the packet for which the process is completed. The cell conversion unit 40g is
The packet output from the IP switch 40f is decomposed to generate a cell. This state is shown in FIG. That is, the packet input to the cell assembling unit 40g is decomposed into cells constituting the packet and output.

The ACT adder 40h uses the ACT of the packet.
The bit is acquired and added to each cell forming the packet. The cell buffer 40i includes the ACT addition unit 40
After temporarily storing the cell output from h, the switch 43
And 44.

The selector 43a of the switch 43 is shown in FIG.
As shown in (4), one of the cells supplied from the conversion unit 40 and the conversion unit 41 whose ACT bit is in the state of "1" is selected and output.

According to the above-described embodiment, as in the case described above, the ACT bit of the predetermined cell forming the packet is taken over as the ACT bit of the entire packet in the ACT adding section 40d, so that it is added to the packet. It is possible to determine the information to be given uniquely and easily.

In the packet buffer 40e,
Prevents cell loss because read control is performed for each VC or packet queue, and after reading all cells before the ACT bit has changed, the cells after the change have been read after a certain time has elapsed. Is possible.

Further, when so-called connection merging in which the input and output relationships to the device are plural-to-single, the same VC is added to packets to which different IP addresses are added. Become. In that case,
In the above-described embodiment, the cell having the ACT bit of “1” in the connection queue of the cell buffer and the ACT
There may be a case where cells having bits "0" are alternately arranged. However, in the case of the above-described embodiment, such a situation can be avoided because the discharge process by the ACT bit is executed at the packet level.

Next, another embodiment of the present invention will be described. FIG. 11 is a diagram showing another configuration example of a system including the tag conversion device of the present invention. In this figure,
Since the same reference numerals are given to the portions corresponding to the case of 1, the description thereof will be omitted.

In this embodiment, the places where the tag conversion devices 30 and 31 are inserted are different from those in the case of FIG. Other configurations are similar to those in the case of FIG.
FIG. 12 is a diagram showing a detailed configuration example of the tag conversion devices 30 and 31 shown in FIG. As shown in this figure, the tag conversion device includes conversion units 50 and 51, a control unit 52, and a switch 5.
3,55. Switches 54, 56
Are included in the ATM switch 24 side.

Since the conversion unit 50 and the conversion unit 51 and the switches 53 and 54 and the switches 55 and 56 have the same structure, the conversion unit 50 and the switch 5 will be described below.
Description will be given by taking 3, 54 as an example.

The conversion unit 50 is composed of parts for uplink and downlink, and parts for uplink are selector 50a, ACT addition part 50b, and packetization part 50.
c, ACT addition unit 50d, packet buffer 50e, I
P switch 50f, cell conversion unit 50g, ACT addition unit 50
h and a cell buffer 50i. On the other hand, the part for the downlink is the selector 50j, AC.
T addition unit 50k, packetization unit 50m, ACT addition unit 5
0n, packet buffer 50o, IP switch 50p,
It is composed of a cell conversion unit 50q, an ACT addition unit 50r, and a cell buffer 50s. It should be noted that the uplink and the downlink have the same configuration, and the operation of each part is basically the same as the case of FIG. 3, so only the operation of the part for the uplink will be described below. Will be briefly described.

The selector 50a selects and outputs either the cell of the uplink line supplied via the switch 53 or the switch 55. The ACT addition unit 50b sets the ACT bit of the input cell under the control of the control unit 52. The ACT addition unit 50b and the ACT addition unit 51b
Sets the ACT bit so that they have mutually opposite values.

The packetizing section 50c synthesizes cells in which the ACT bit is set to generate a packet. The ACT addition unit 50d acquires the ACT bit of a predetermined cell (for example, the head cell) forming the packet, and sets this as the ACT bit of the packet itself.

The packet buffer 50e temporarily stores the packet supplied from the ACT adding section 50d,
Output. The IP switch 50f performs IP switching processing and packet protocol conversion processing on the packet.

The cell conversion unit 50g decomposes the packet output from the IP switch 50f into cells. The ACT adding unit 50h acquires the ACT bit added to the packet and adds the ACT bit to each of the cells forming the packet.

As shown in FIG. 5, the cell buffer 50i classifies cells into VCs and stores the cells in the corresponding areas, and also reads and outputs the cells in sequence for each VC.
The selector 54a of the switch 54 uses the cell buffer 50i.
Alternatively, the cell output from any one of the cell buffers 51i is selected and output.

The operation of the other parts is similar to the above-mentioned case, and the input cells are packetized and subjected to the switching process, and then re-celled and output.

According to the above embodiment, it is possible to prevent the cell loss even when both the uplink and the downlink are duplicated and the active system and the standby system are switched. Become.

In the above embodiments, the ACT bit indicates the system to be selected. However, for example, a signal running in parallel with a cell or packet is provided, and this signal indicates the side to be selected. You may

In the above embodiments, the IP packet has been described as an example, but it goes without saying that the present invention is not limited to such a case.

Furthermore, although the ATM switch and the tag conversion device have different structures in the above-described embodiments, it is also possible to add the ATM switch to the tag conversion device.

[0082]

As described above, according to the present invention, the input cells are combined to generate a packet, the tag of the generated packet is converted if necessary, and then the packet is decomposed again and output. In the tag conversion device, a first packet synthesizing unit that synthesizes the input cells to generate a first packet, and a second packet synthesizing unit that synthesizes the input cells to generate a second packet. When switching between the active system and the standby system is requested, selection information generating means for generating selection information indicating which of the first and second packets is to be selected, and the first packet is decomposed. First packet disassembling means for generating a first cell, second packet disassembling means for disassembling a second packet to generate a second cell, and the first cell for each cell type. First cell storing means for storing A second cell storage means for storing the second cells separately for each type of the cell and a first cell stored in the first cell storage means for sequentially reading and outputting for each type The selection information is generated by the first cell reading unit, the second cell reading unit that sequentially reads and outputs the second cells stored in the second cell storage unit for each type, and the selection information generation unit. In this case, since the timing adjusting means for adjusting the read timing of the first and second cell reading means is provided, even if the active system and the standby system are switched, cell loss and sequence Reverse rotation can be prevented.

In addition, in the tag conversion device which synthesizes the input cells to generate a packet, converts the tag of the generated packet as necessary, and decomposes it again into a cell and outputs it. A first packet synthesizing means for synthesizing the input cells, a second packet synthesizing means for synthesizing the input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which one of the first packet and the second packet is to be selected, and the first packet which stores the first packet separately for each type of the packet. First packet storage means, second packet storage means for storing the second packet separately for each packet type, and first packet storage means
First packet reading means for sequentially reading the first packets stored in the packet storing means of each type, and second packet reading means for sequentially reading the second packets stored in the second packet storing means of each type When the second packet read means and the selection information by the information selection means are generated, the timing adjustment means for adjusting the read timing of the first and second packet read means and the first packet are decomposed. Since the first packet decomposing means for generating and outputting the first cell and the second packet decomposing means for decomposing the second packet and generating and outputting the second cell are provided. In the case where connection merging is performed, cell loss and reversal of order can be prevented even when the active system and the standby system are switched.

[Brief description of drawings]

FIG. 1 is a principle diagram illustrating an operation principle of the present invention.

FIG. 2 is a diagram illustrating an outline of a system including a tag conversion device of the present invention.

FIG. 3 is a block diagram showing a detailed configuration example of the tag conversion device shown in FIG.

FIG. 4 is a diagram for explaining operations of a packet buffer and a cell assembling unit shown in FIG.

5 is a diagram for explaining the operation of the cell buffer shown in FIG.

FIG. 6 is a diagram for explaining the operation of the selector shown in FIG.

FIG. 7 is a diagram for explaining the outline of the operation of the embodiment shown in FIG.

FIG. 8 is a diagram for explaining another operation of the packet buffer and the cell assembling unit shown in FIG.

FIG. 9 is a diagram for explaining another operation of the cell buffer shown in FIG.

10 is a diagram for explaining another operation of the selector shown in FIG.

FIG. 11 is a diagram illustrating an outline of another system including the tag conversion device of the present invention.

12 is a block diagram showing a detailed configuration example of the tag conversion device shown in FIG.

[Explanation of symbols]

1 First packet combining means 2 Second packet combining means 3 Selection information generation means 4 First packet combining means 5 Second packet combining means 6 First cell storage means 7 Second cell storage means 8 First cell reading means 9 Second cell reading means 10 Timing adjustment means 20-1 to 20-3 Terminal device 21-1 to 21-3 Terminal device 22,23 switch 24 ATM switch 25,30,31 Tag Converter 40, 41 tag converter 40a, 41a selector 40b, 41b ACT addition part 40c, 41c Packetization unit 40d, 41d ACT addition part 40e, 41e packet buffer 40f, 41f IP switch 40g, 41g Cell part 40h, 41h ACT addition part 40i, 41i cell buffer 42 Control unit 43,44 switch 43a, 44a selector 50,51 tag converter 50a, 51a, 50j, 51j selector 50b, 51b, 50k, 51k ACT adder 50c, 51c, 50m, 51m Packetization unit 50d, 51d, 50n, 51n ACT addition unit 50e, 51e, 50o, 51o packet buffer 50f, 51f, 50p, 51p IP switch 50g, 51g, 50q, 51q Cellularization unit 50h, 51h, 50r, 51r ACT adder 50i, 51i, 50s, 51s cell buffer 52 control unit 53,54,55,56 switch 53a, 54a, 55a, 56a Selector

Front page continued (72) Inventor Masaaki Shigetani 2-3-1 Otemachi, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Inventor Takeshi Chimaru 2-3-1 Otemachi, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (56) Reference JP 2000-31971 (JP, A) JP 9-135244 (JP, A) JP 7-15463 (JP, A) (58) Fields investigated ( Int.Cl. ⁷ , DB name) H04L 12/28

Claims (10)

(57) [Claims] 1. A tag conversion device that combines input cells to generate a packet, converts the tags of the generated packets as necessary, and then decomposes them again into cells and outputs the cells. A first packet synthesizing means for synthesizing the cells to generate a first packet, a second packet synthesizing means for synthesizing the input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which one of the first packet and the second packet is selected, and disassembling the first packet to generate a first cell. First packet disassembling means, second packet disassembling means for disassembling the second packet to generate a second cell, and first storing the first cell separately for each type of the cell Cell storage means, and Second cell storing means for storing the cells of the above type separately for each type of the cells, and a first cell for sequentially reading and outputting the first cells stored in the first cell storing means for each type thereof. Cell reading means, second cell reading means for sequentially reading and outputting the second cells stored in the second cell storing means for each type, and selection information is generated by the selection information generating means. In this case, the tag conversion device further comprises: timing adjusting means for adjusting the read timing of the first and second cell reading means. 2. The tag conversion device according to claim 1, wherein the timing adjusting means suspends the reading for a predetermined time when the selection information is generated by the selection information generating means. 3. The timing adjusting means, when the selection information is generated by the selection information generating means, determines the cells before the selection information is generated in both the first and second cell storage means. 2. The tag conversion device according to claim 1, wherein the reading of the cell after the selection information is generated is started after waiting until all the information is read. 4. The cell has a bit indicating that switching between the active system and the standby system has been requested, and the selection information generating means includes one or more of one or more included in the combined packet. Referring to the bit in the cell,
Generating selection information indicating which of the first and second packets is selected and adding the selection information to the first and second packets, respectively, and the timing adjusting means is added to the first and second packets. The tag conversion device according to claim 1, wherein the read timing of the first and second cell read means is adjusted with reference to the selection information. 5. The cell is transmitted in parallel with information indicating that switching between the active system and the standby system has been requested, and the selection information generation means includes 1 or 1 included in the combined packet. Referring to said signal corresponding to two or more cells, transmitted in parallel with the first and second packets,
Generating selection information indicating which of the first or second packet is to be selected, the timing adjusting means refers to the selection information transmitted in parallel with the first and second packets, The tag conversion device according to claim 1, wherein the read timings of the first and second cell read means are adjusted. 6. A tag conversion device that combines input cells to generate a packet, converts the tags of the generated packets as necessary, and then decomposes them into cells and outputs the cells. A first packet synthesizing means for synthesizing the input cells, a second packet synthesizing means for synthesizing the input cells to generate a second packet, and switching between the active system and the standby system. When requested, selection information generating means for generating selection information indicating which of the first and second packets is to be selected, and the first packet is stored separately for each packet type. A first packet storage means; a second packet storage means for storing the second packet separately for each packet type; and a first packet stored in the first packet storage means First packet reading means for sequentially reading out by type, second packet reading means for sequentially reading out second packets stored in the second packet storing means for each type, and selection by the information selecting means When information is generated, timing adjusting means for adjusting the read timings of the first and second packet reading means, and a first cell for decomposing the first packet to generate and outputting a first cell 1. A tag conversion device comprising: 1 packet decomposing unit; and 2nd packet decomposing unit that decomposes the second packet to generate and output a second cell. 7. The tag conversion device according to claim 6, wherein the timing adjusting means suspends the reading for a predetermined time when the selection information is generated by the selection information generating means. 8. The timing adjusting means, when the selection information is generated by the selection information generating means, determines that a packet before the selection information is generated in both the first and second packet storing means. 7. The tag conversion device according to claim 6, wherein after reading all the packets, waiting for a predetermined period of time to start reading the packet after the selection information is generated. 9. The cell has a bit indicating that switching between the active system and the standby system has been requested, and the selection information generating means includes one or more of one or more included in the combined packet. Referring to the bit in the cell,
Generating selection information indicating which of the first and second packets is selected and adding the selection information to the first and second packets, respectively, and the timing adjusting means is added to the first and second packets. 7. The tag conversion device according to claim 6, wherein read timings of the first and second packet read means are adjusted with reference to the selection information. 10. The cell is transmitted in parallel with information indicating that switching between the active system and the standby system has been requested, and the selection information generation means includes 1 or 1 included in the combined packet. Referring to said signal corresponding to two or more cells, transmitted in parallel with the first and second packets,
Generating selection information indicating which of the first or second packet is to be selected, the timing adjusting means refers to the selection information transmitted in parallel with the first and second packets, 7. The tag conversion device according to claim 6, wherein read timings of the first and second packet read means are adjusted.