JP3528334B2 - Data select circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data select circuit which enables a signed operation with an arbitrary number of bits.

[0002]

2. Description of the Related Art Conventionally, a predetermined number (n bits) of signed data whose most significant bit is a sign bit is input, and a predetermined number of signed data whose most significant bit is a sign bit is output as an operation result. In addition, there is an arithmetic unit that outputs data in the form of multiplying the signed data by a predetermined constant when the data obtained by multiplying the signed data by the predetermined constant is input.

[0003]

However, the signed operation cannot be performed on data having an arbitrary number of bits smaller than n bits by sharing the arithmetic unit and the data bus. The present invention has been made in view of the above points, and an object of the present invention is to provide a data select circuit that enables an operation even with signed data having an arbitrary number of bits smaller than a predetermined bit. To provide.

It is an object of the present invention to provide a data select circuit for dividing signed data having a predetermined number of bits and signed data having a half bit number thereof.
It is an object of the invention of claim 3 to provide a data select circuit according to the invention of claim 2, which enables division of 32-bit signed data and 16-bit signed data.

It is an object of the present invention to provide a data select circuit capable of adding signed data having a predetermined number of bits and signed data having an arbitrary number of bits smaller than the predetermined number of bits. . It is an object of the present invention to provide a data select circuit capable of subtracting signed data having a predetermined number of bits and signed data having an arbitrary number of bits smaller than the predetermined number of bits.

[0006]

In order to achieve the above object, according to the invention of claim 1, a predetermined number of bits of signed data in which the most significant bit is a sign bit is input, and the most significant bit is the sign as an operation result. outputs signed data of a predetermined number of bits is the bit, and constant the signed data to the multiplied data when input arithmetic unit for outputting the data obtained by multiplying the constant to signed data and a predetermined number of bits When the data bus is shared and signed data with an arbitrary number of bits smaller than the specified number of bits is to be calculated, the most significant bit of the data input to the arithmetic unit at the input side of the arithmetic unit is the most significant bit of the data bus. Data is selected so that it matches with, and on the output side of the operation unit, the data is output so that the least significant bit of the data output from the operation unit matches the least significant bit of the data bus. A function of recto, is characterized in that a function of inserting the bit data of "0" in the empty bit data bus.

According to the second aspect of the present invention, the divisor and dividend of a predetermined number of bits of signed data whose most significant bit is a sign bit are input, and the quotient of the signed data whose most significant bit is a sign bit as an operation result, A data bus of a predetermined number of bits is shared with a divider that outputs a remainder, and when the data of the number of half the predetermined number of bits is input, the most significant bit of the data is input to the input side of the divider. When the data is selected so that it matches the most significant bit of the bus and the data output from the divider at the output side of the divider is 1/2 the predetermined number of bits, the least significant bit of the data is the least significant bit of the data bus. It is characterized by having a function of selecting data so as to match the lower bit and a function of inserting bit data of "0" into an empty bit of the data bus.

The invention of claim 3 is characterized in that, in the invention of claim 2, the predetermined number of bits is 32 bits. According to the invention of claim 4, the first and second signed data having a predetermined number of bits whose most significant bit is a sign bit is input, and the signed data whose most significant bit is a sign bit is added as a result of addition of both data. When the output adder shares the data bus of a predetermined number of bits and the signed data of an arbitrary number of bits smaller than the predetermined number of bits is added, the highest order of the data input to the adder at the input side of the adder Select the data so that the bit matches the most significant bit of the data bus, and at the output side of the adder, select the data so that the least significant bit of the data output from the adder matches the least significant bit of the data bus. It has a function of selecting and a function of inserting bit data of "0" into an empty bit of the data bus.

According to the fifth aspect of the present invention, a predetermined number of bits of the first and second signed data whose most significant bit is a sign bit is input, and the most significant bit is a sign bit as a subtraction result of both data. When the subtractor that outputs the attached data shares the data bus with a predetermined number of bits and subtracts signed data with an arbitrary number of bits smaller than the predetermined number of bits, the data input to the subtractor on the input side of the subtractor Select the data so that the most significant bit of the data matches the most significant bit of the data bus, and at the output side of the adder, make sure that the least significant bit of the data output from the subtractor matches the least significant bit of the data bus. Is provided with a function of selecting data and a function of inserting "0" bit data into an empty bit of the data bus.

[0010]

According to the invention of claim 1, it is possible to operate even signed data having an arbitrary number of bits smaller than a predetermined number of bits. In particular, according to the invention of claim 2, it is possible to divide the signed data having a predetermined number of bits and the signed data having a half bit number thereof.

According to the invention of claim 3, in the invention of claim 2, division of 32-bit signed data and 16-bit signed data is enabled. According to the invention of claim 4, it is possible to add signed data having a predetermined number of bits and signed data having an arbitrary number of bits smaller than the predetermined number of bits. According to the invention of claim 5, it is possible to subtract the signed data having a predetermined number of bits and the signed data having an arbitrary number of bits smaller than the predetermined number of bits.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a multi-input multi-output type arithmetic unit 1 in which n-bit signed data is used as input data. 2 shows an arithmetic circuit in which the data select circuits 2 ₀ ... 30 ₀ shown in FIGS.

Since the most significant bit of the data input to the arithmetic unit 1 is the sign bit of the sign determination, the input side data select circuit 2 ₀ ... Is the data of an arbitrary number of bits (here, m bits). This is for selecting data so as to match the most significant bit and the most significant bit of the n-bit data bus, and the data is selected by a select signal. The output side data select circuit 3 ₀ ... Is for selecting the data so that the least significant bit of the data output from the arithmetic unit 1 matches the least significant bit of the data bus. Use signal.

The input-side data select circuit 2 of the number of bits of the data bus as shown in FIG. 2, i.e. comprises n multiplexers 4 ₀ to 4 _n-1 so as to correspond to the n bits, the multiplexer 4 ₀ Only the least significant bit A ₀ can be selected, and thereafter, more bits can be sequentially selected one by one, and the multiplexer 4 _n-1 can select from all the bits A _{0 to} A _n-1. Selection is controlled according to the number of bits of input data.

That is, when the data A has n bits, the select signal is set to "0" indicating that the number of bits of the data bus is the same. In this case each of the multiplexers 4 ₀ ~
The most significant bit among the 4 _{n- 1} selectable bits is selected and output as data B.
That is, as shown in FIG. 3A, the data A (A _0-
Outputs A _n-1 a) as the intact data _{B (B 0 ~B n-1} ).

If the data A has n-1 bits,
In the data selection circuit 2 so as to match the most significant bits of the data bus, providing a select signal "1" to the multiplexer 4 ₀ to 4 _n-1 to shift to a higher bit by bit as shown in FIG. 3 (b) . By providing a select signal indicating the difference between the number of bits of the data A to be inputted In this way the number of bits of the data bus and to the multiplexer 4 ₀ ~4 _n-1, any smaller than the number of bits of the data bus the number of bits of The most significant bit of signed data and the most significant bit of the data bus can be matched. FIG. 3C shows the case where n-2 bit data A is input, and FIG.
FIG. 3D shows a case where 2-bit data A is input, and FIG. 3E shows a case where 1-bit data A is input.

In this way, even if signed data having an arbitrary number of bits smaller than the number of bits of the data bus is input, the data select circuit 2 on the input side causes the data (data B in the above) to be input to the arithmetic unit 1 to be changed. The most significant bit can match the most significant bit of the data bus. While the output side data selector circuit 3, the number of bits of the data bus, as shown in FIG. 4, i.e. comprises n multiplexers 5 ₀ to 5 _n-1 so as to correspond to the n bits, the multiplexer 5 ₀ All The bits that can be selected from the bits C _{0 to} C _n-1 and the bits that can be sequentially selected one bit at a time are reduced, and the multiplexer 5 _n-1 can select only the most significant bit C _n-1. Is controlled according to the bit of the input data.

That is, when the data C output from the arithmetic unit 1 is n bits, the select signal is set to "0" indicating that the bit of the data bus is the same. In this case, the least significant bit of the bits that can be selected by each of the multiplexers 5 _{0 to} 5 _n-1 is selected and output as data D. That is, as shown in FIG. 5A, the data C (C _{0 to} C _n-1 ) is directly changed to the data D (D _{0 to} D _n ).
_n-1 ).

If the data C is n-1 bits,
In the data select circuit 2 so as to coincide with the least significant bit of the data bus, the select signal "1" is given to the multiplexers 5 _{0 to} 5 _n-1 so as to shift to the lower bit by bit as shown in FIG. 5B. . By providing a select signal indicating the difference between the number of bits of data C to be inputted In this way the number of bits of the data bus and to the multiplexer 5 ₀ ~5 _n-1, any smaller than the number of bits of the data bus the number of bits of The least significant bit of signed data and the least significant bit of the data bus can be matched. FIG. 5C shows the case where the n−2 bit data C is output.
5D shows the case where 2-bit data C is output, and FIG. 5E shows the case where 1-bit data C is output.

In this way, even if signed data having an arbitrary number of bits smaller than the number of bits of the data bus is output from the arithmetic unit 1, the data select circuit 3 on the output side outputs the data to the arithmetic unit 1 (in the above case, The least significant bit of the data C) can be converted into data matched with the least significant bit of the data bus and output. Note each multiplexer 4 ₀ select circuit 2, 3 ..., 5 ₀ ... has a function of outputting the bit data "0" corresponding to the empty bit data bus.

(Embodiment 2) In this embodiment, the arithmetic unit shown in FIG. 6 corresponds to an (even) bit signed divider 10 and enables division even with n / 2-bit signed data. Therefore, the data select circuit 2 is connected to the data bus for inputting the divisor and the data bus for inputting the dividend of the divider 10.
The data select circuit 30 is inserted in the data bus for outputting 0 ₁ , 20 ₂ and the remainder.

Since the divider 10 determines the sign using the most significant bit of the input data, the data select circuits 20 ₁ and 20 ₂ have the most significant bit of the n / 2-bit data and the n-bit data bus. Align the data so that the most significant bits match. That is, as shown in FIG. 7, the data select circuit 20 includes multiplexers 21 ₀ to 2 _0.
The multiplexers 21 ₀ to 21 _{n / 2-1} having 1 _n-1 select only the corresponding 1 bit A ₀ ... A _{n / 2-1} , and the multiplexers 21 _{n / 2} to 21 _n-1 The multiplexer has corresponding bits A _{n / 2} ... A _n-1 and 21 ₀ to 21
Bit A ₀ corresponding to each multiplexer up to _{n / 2-1}
… A _{n / 2-1} is selected.

When the input data A is n bits,
As shown in (a), since the difference from the number of bits of the data bus is 0, a select signal "0" indicating that is given to the multiplexers 21 _{0 to} 21 _n-1 and each of the multiplexers 21 _{0 to} 21 _{n-. The} data A _{0 to} A _n-1 corresponding to _{1 is set} to B
Output as _{0 to} B _n-1 . On the other hand, the input data A is n / 2
In the case of a bit, as shown in FIG. 8B, a select signal "1" indicating that is given to the multiplexers 21 _{0 to} 21 _n-1 to output "0" from the multiplexers 21 ₀ to 21 _{n / 2-1.} , And the bits from A ₀ to A _{n / 2-1} are output from the multiplexers from 21 _{n / 2} to 21 _n-1 .

That is, for the most significant bit of the data bus
The most significant bit of the data A input to the divider 10 matches
In addition, 0 is inserted in the empty bit of the data bus.
On the other hand, the data select circuit 30 on the output side of the divider 10
The number of bits of the remainder data of the calculation result is the number of bits of the data bus
If less than, to match the least significant bit
The configuration of the multiplexer 3 is as shown in FIG.
1₀~ 31_n-1Equipped with 31_n-1From 31_{n / 2}Up to mal
The chipplexer has a corresponding 1-bit C _n-1… C_{n / 2}of
Select only 31_{n / 2-1}From 31₀Up to multip
Lexa is the corresponding bit C_{n / 2-1}… C₀And 31_n-1Or
31_{n / 2}Bits corresponding to each multiplexer up to
C_n-1… C_{n / 2}It is designed to select and.

When the output data C from the divider 10 is n bits, the difference from the number of bits of the data bus is 0 as shown in FIG. 10 (a). Therefore, the select signal "0" indicating that is output. The data C _{0 to} C _n-1 corresponding to the respective multiplexers 31 _{0 to} 31 _n-1 are given to the multiplexers 31 _{0 to} 31 _n-1 and output as D _{0 to} D _n-1 . On the other hand, when the output data C is n / 2 bits, as shown in FIG. 10B, the select signal "1" indicating it is given to the multiplexers 31 _{0 to} 31 _n-1 to 31 _{n / 2} to 21 _n-. "0" is output from the multiplexers up to ₁ and 3 ₀ to 3
From multiplexers up to 1 _{n / 2-1} C ₀ to C _{n / 2-1}
The bits up to are output respectively.

That is, the output data C indicating the operation result output from the divider 10 with respect to the least significant bit of the data bus is converted into the data D in which the least significant bit matches and is output. Also, 0 is inserted in the empty bit of the data bus. Due to the nature of division, the output quotient need not be provided with a data select circuit. (Embodiment 3) This embodiment is a case where the number of bits of the data bus in Embodiment 2 is 32 bits.
It is possible to perform division even with signed data of bits.

Since the configuration and operation are the same as those of the second embodiment, the drawings with the same numbers and the same symbols are presented and the description thereof is omitted. 11 corresponds to FIG. 6, FIG. 12 corresponds to FIG. 7, FIG. 13 corresponds to FIG. 8, FIG. 14 corresponds to FIG. 9, and FIG. 15 corresponds to FIG. (Embodiment 4) In the present embodiment, the n (even) bit signed adder 40 shown in FIG. 16 is provided in the data bus in order to enable addition even with n / 2-bit signed data. The configuration is the same as that of the data select circuits 2 and 3 shown in FIGS. Since the adder 40 determines the sign using the most significant bit of the input data, the data select circuit 2 on the input side determines that the most significant bit of the n / 2-bit data is the most significant bit of the n-bit data bus. The data is aligned so that they match with each other, and bit data "0" is inserted into an empty bit of the n-bit data bus. Also in the data output after the operation is completed, the least significant bit is matched with the least significant bit of the data bus through the data select circuit 3 to complete the operation.

If the adder 60 is replaced with an n (even) bit signed subtractor, even 2-bit signed data can be subtracted.

[0029]

According to the first aspect of the present invention, a predetermined number of bits of signed data whose most significant bit is a sign bit is input, and a predetermined number of bits of signed data whose most significant bit is a sign bit is input as an operation result. outputs, and a constant share data bus of the arithmetic unit and the predetermined number of bits for outputting data obtained by multiplying the constant to signed data when input data multiplied by the signed data, a smaller predetermined number of bits When calculating signed data with an arbitrary number of bits, select the data on the input side of the arithmetic unit so that the most significant bit of the data input to the arithmetic unit matches the most significant bit of the data bus, and perform the arithmetic operation. On the output side of the device, the function to select the data so that the least significant bit of the data output from the arithmetic unit matches the least significant bit of the data bus, and the empty bit of the data bus. Since "0" and a function of inserting the bit data, there is an effect that operation is possible with any number of bits of the signed data smaller than a predetermined bit.

According to a second aspect of the present invention, the divisor and dividend of a predetermined number of bits of signed data in which the most significant bit is a sign bit are input, and the quotient of the signed data in which the most significant bit is a sign bit as an operation result, A data bus of a predetermined number of bits is shared with a divider that outputs a remainder, and when the data of the number of half the predetermined number of bits is input, the most significant bit of the data is input to the input side of the divider. The data is selected so that it matches the most significant bit of the bus, and at the output side of the divider, the data output from the divider is 1 with a predetermined number of bits.
In the case of / 2, it has a function of selecting data so that the least significant bit of the data matches the least significant bit of the data bus, and a function of inserting "0" bit data into an empty bit of the data bus. Therefore, there is an effect that it is possible to divide the signed data having a predetermined number of bits and the signed data having a half bit number thereof.

According to the invention of claim 3, in the invention of claim 2, since the predetermined number of bits is 32 bits, there is an effect that division of 32-bit signed data and 16-bit signed data is possible. is there. According to a fourth aspect of the present invention, a predetermined number of bits of the first and second signed data in which the most significant bit is the sign bit is input, and the signed data in which the most significant bit is the sign bit is input as the addition result of both data. Share the output adder and the data bus of a certain number of bits,
When performing addition of signed data with an arbitrary number of bits smaller than the specified number of bits, the data is input so that the most significant bit of the data input to the adder matches the most significant bit of the data bus. On the output side of the adder, the least significant bit of the data output from the adder is
Since it has a function of selecting data so as to match the least significant bit of the data bus and a function of inserting bit data of "0" into an empty bit of the data bus, it has a predetermined number of signed data and a predetermined bit. There is an effect that it is possible to add data with an arbitrary sign smaller than the number.

According to a fifth aspect of the present invention, a predetermined number of bits of the first and second signed data in which the most significant bit is a sign bit is input, and the most significant bit is a sign bit as a subtraction result of both data. When the subtractor that outputs the attached data shares the data bus with a predetermined number of bits and subtracts signed data with an arbitrary number of bits smaller than the predetermined number of bits, the data input to the subtractor on the input side of the subtractor Select the data so that the most significant bit of the data matches the most significant bit of the data bus, and at the output side of the adder, make sure that the least significant bit of the data output from the subtractor matches the least significant bit of the data bus. Since it has the function of selecting data and the function of inserting bit data of "0" into the vacant bit of the data bus, it is smaller than the predetermined number of signed data and the predetermined number of bits. There there is an effect that allows the subtraction of meaning signed data of an arbitrary number of bits.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an arithmetic circuit using a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an input-side data select circuit used in the above.

FIG. 3 is an operation explanatory diagram of the above.

FIG. 4 is a circuit diagram of an output-side data select circuit used in the above.

FIG. 5 is an operation explanatory diagram of the above.

FIG. 6 is a circuit diagram of a division circuit using a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an input-side data select circuit used in the above.

FIG. 8 is an operation explanatory diagram of the above.

FIG. 9 is a circuit diagram of an output-side data select circuit used in the above.

FIG. 10 is an operation explanatory diagram of the above.

FIG. 11 is a circuit diagram of a divider circuit using a third embodiment of the present invention.

FIG. 12 is a circuit diagram of an input-side data select circuit used in the above.

FIG. 13 is an operation explanatory diagram of the above.

FIG. 14 is a circuit diagram of an output-side data select circuit used in the above.

FIG. 15 is an operation explanatory diagram of the above.

FIG. 16 is a circuit diagram of a division circuit using a fourth embodiment of the present invention.

[Explanation of symbols]

1 arithmetic unit 2 ₀ ... data select circuit 3 ₀ ... data select circuit

Claims (5)

(57) [Claims] 1. A predetermined number of bits of signed data whose most significant bit is a sign bit is input, a predetermined number of bits of signed data whose most significant bit is a sign bit is output as an operation result, and a constant is said When a data multiplied by signed data is input, the data bus of a predetermined number of bits is shared with the arithmetic unit that outputs the data obtained by multiplying the signed data by the above constant, and a signed number of arbitrary bits smaller than the predetermined number of bits When calculating data, select the data so that the most significant bit of the data input to the arithmetic unit matches the most significant bit of the data bus on the input side of the arithmetic unit, and the arithmetic unit on the output side of the arithmetic unit. From the data output so that the least significant bit of the data matches the least significant bit of the data bus. Data selection circuit, characterized in that a function of inserting the data. 2. A division in which a divisor and a dividend of a predetermined number of bits of which the most significant bit is a sign bit are input, and a quotient and a remainder of the signed data of which the most significant bit is a sign bit are output as an operation result. Share a data bus of a predetermined number of bits with the divider, and at the input side of the divider,
When the data of 2 bit number is input, the data is selected so that the most significant bit of the data matches the most significant bit of the data bus, and the data output from the divider is a predetermined bit at the output side of the divider. When the number is 1/2, the function of selecting data such that the least significant bit of the data matches the least significant bit of the data bus, and the function of inserting "0" bit data into the empty bit of the data bus The data select circuit according to claim 1, further comprising: 3. The data select circuit according to claim 2, wherein the predetermined number of bits is 32 bits. 4. A predetermined number of bits of first and second signed data whose most significant bit is a sign bit is input, and signed data whose most significant bit is a sign bit is output as the addition result of both data. When an adder and a data bus of a predetermined number of bits are shared and signed data with an arbitrary number of bits smaller than the predetermined number of bits is added, the most significant bit of the data input to the adder is on the input side of the adder. , Select the data so that it matches the most significant bit of the data bus, and at the output side of the adder, select the data so that the least significant bit of the data output from the adder matches the least significant bit of the data bus. A data select circuit having a function and a function of inserting "0" bit data into an empty bit of a data bus. 5. A predetermined number of bits of first and second signed data whose most significant bit is a sign bit is input, and signed data whose most significant bit is a sign bit is output as a subtraction result of both data. When the subtractor shares a data bus of a predetermined number of bits and subtracts signed data of an arbitrary number of bits smaller than the predetermined number of bits, the most significant bit of the data input to the subtractor is on the input side of the subtractor. , Select the data so that it matches the most significant bit of the data bus, and at the output side of the adder, select the data so that the least significant bit of the data output from the subtractor matches the least significant bit of the data bus. A data select circuit having a function and a function of inserting "0" bit data into an empty bit of a data bus.