JP3501923B2 - Timing generator for semiconductor test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generator of a semiconductor test apparatus for generating a plurality of timing pulses within one pattern period in accordance with an interleave system, and particularly improving the accuracy of timing pulse delay time. The present invention relates to a timing generator for a semiconductor test device that reduces hardware and generates at high speed.

[0002]

2. Description of the Related Art First, an outline of a conventional semiconductor IC test apparatus will be described. FIG. 4 shows a basic configuration diagram of the semiconductor test apparatus. The test processor 1 controls the entire apparatus and gives a control signal to each unit by a tester bus. The pattern generator 2 generates an application pattern to be given to the DUT (device under test) 9 and an expected value pattern to be given to the pattern comparator 7. The timing generator 3 generates a timing pulse signal in order to obtain a test timing of the entire apparatus and supplies it to the waveform shaper 4, the comparator 6, the pattern comparator 7 and the like to take a test timing.

The waveform shaper 4 shapes the applied pattern from the pattern generator 2 into a signal waveform, passes through the driver 5, and then the DU.
A test signal is given to T9. The response signal from the DUT 9 is voltage-compared by the comparator 6, and the resulting logic signal is given to the pattern comparator 7. The pattern comparator 7 logically compares the logic pattern of the test result from the comparator 6 and the expected value pattern from the pattern generator 2 to detect a match / mismatch, and determines the quality of the DUT 9. In the case of failure, information is given to the failure analysis memory 8 and stored together with the information from the pattern generator 2, and failure analysis is performed later.

In order to generate each signal for performing these operations, the pattern generator 2, the timing generator 3, and the waveform shaper 4 are provided with a memory table and data are stored therein. The data given to these tables are supplied from the test processor 1 to the respective parts by the programmer based on the performance specifications of the DUT 9 to be measured, creating a test program considering the test pattern.

In the table of the pattern generator 2, test pattern data for each pin such as 0, 1, L, H, Z is prepared for pins 1 to n. Data relating to waveform settings such as the waveform mode is prepared in the table of the waveform shaper 4, and a test signal is generated using the test pattern data from the pattern generator 2 and the set and reset timing pulse signals from the timing generator 3. Is being supplied to the driver 5.

The timing generator 3 has a RATE setting table and a clock setting table. The RATE setting table stores data of a pattern period (Test Period), and the clock setting table stores timing data of driver waveforms. ing. A plurality of groups, for example, TS1 group, TS2 group, TSn group, and the like are prepared and read by combining these data, and timing pulses of a set signal and a reset signal are generated.

In the timing generator 3, the pattern cycle to be set is the reference clock (Reference Clock).
A fraction may be generated in an integral multiple of. Then, the fractional data (Fractional Data) of the reference clock is obtained by adding the fractional data from the previous pattern period and the set fractional data, delaying the integral multiple data of the addition result by digital means, and the addition result fractional data being analog variable. A delay circuit is used to convert the timing pulse signal to 1/2, 1/4, 1 / of the reference clock.
It is generated accurately with a resolution of 8, 1/16, ... The details will be described below.

FIG. 5A shows a basic configuration diagram of the timing generator 3. The configuration is composed of an input unit 10, an arithmetic unit 11, a reference clock delay unit 12, a retiming unit 13, and an analog variable delay unit 14. Then, the fractional data of the previous pattern period is input from the input terminal a1, the period start signal is input from a2, and the period start signal is input from a3.
The data of the timing delay time is input from and the reference clock is input from a4. Now, as an example of the test condition in which the pattern period has information equal to or less than the reference clock, a pattern having a frequency of 100 MHz and a period of 10 ns (nanoseconds) (hereinafter, the period of the reference clock is represented by “T”) is used. A timing pulse signal having a period of (5 + 3/4) T and a timing delay time of (3 + 1/2) T is continuously generated. FIG. 6 shows a timing chart in that case.

First, when the cycle start signal is input from a2, the latch circuit f1 of the input means 10 is write enable, and the cycle start signal is also given to the latch circuit f2. The latch circuit is composed of a D-type flip-flop and may or may not have a WE (Write Enable).
It is assumed that the timing delay data (3 + 1/2) from a3 is already stored (memory) in the register R. (Hereinafter, the timing delay data is referred to as "setting delay data"). The reference clock from a4 is supplied to the latch circuit f1 to latch the fractional data from a1, the data is supplied to the adder K of the arithmetic means 11, and the latch circuit f2 is supplied with a.
The period start signal from 2 is latched and given to the load terminal of the down counter C in the reference clock delay means 12 to load (input) the integer data N output from the adder K. The adder K has already output the data obtained by adding the fraction data and the set delay data. The reference clock is also applied to the clock terminal of the down counter C.

In the generation of the first timing pulse, since the fraction data from a1 is 0, the calculating means 1
The input data of the adder K of 1 is 0 and (3 + 1/2), and the output data thereof is (3 + 1/2). See Figure 6D. The integer data N of 3 is output to the down counter C of the reference clock delay means 12 and the fractional data of 1/2 is output to the latch circuit f4 of the analog variable delay means 14. The down counter C loads the data of 3 by the signal of the start of the cycle, and
It is decremented by 1 with the reference clock from 4 and the data is output from the data out terminal do. When the output signal from the data-out terminal do becomes zero with the three reference clocks, the coincidence circuit h1 coincides with zero and the reference clock delay signal S
To the latch circuit f3 of the retiming circuit 13 and the latch circuit f4 of the analog variable delay means 14.

The retiming circuit 13 always adds a fixed offset time by the fixed delay device D to the reference clock in order to eliminate the variation in the delay time of the reference clock delay signal S caused by the down counter C and the like, and always adds it. It is a circuit for timing a fixed delay time. Therefore, the reference clock signal from a4 is passed through the fixed delay device D having a delay time slightly larger than the maximum delay time from the input terminal a1 to the retiming circuit 13, and the reference clock passed through the already opened gate h2 is used. It is used as the timing pulse reference. See Figure 6E. The analog variable delay means 14 delays the time of the fractional data (1/2) latched by the latch circuit f4, and outputs a timing pulse delayed by (3 + 1/2) T from the output terminal b1. See Figure 6F. When the first pattern period ends, the fractional data (3/4) of the pattern period (5 + 3/4) T is applied to the input terminal a1.

The delay time of the second timing pulse is the sum of the fractional data (3/4) applied to the input terminal a1 and (3 + 1/2) of the memory in the register R, which is added by the adder K, The data of (4 + 1/4) is output. Figure 6
See C and D. The integer data of 4 is output to the down counter C, and the fractional data of (1/4) is output to the analog variable delay means 14, which is delayed by the digital means and the analog variable delay means in the same manner as the first shot, and then (4 + 1 / 4) A timing pulse delayed by T is output. See Figure 6F.

In the third shot, the pattern cycle has fractional data of the first and second shots as (3/4 + 3 /
Since 4) = (1 + 1/2), the configuration is not shown, but 6 reference clocks obtained by incorporating integer data of 1 into the original pattern period and adding 1 to 5 reference clocks are set as the pattern period. See Figure 6A. Therefore, the fractional data of the pattern period becomes (1/2) and is supplied to the input terminal a1. Since the data in the register R is (3 + 1/2), the addition result is 4. Therefore, the 4 output data from the adder K is sent to the down counter C, and only the digital delay is performed to generate the timing pulse. See Figure 6F. The above operation is performed after the fourth shot and the timing pulses are continuously transmitted.

FIG. 5B shows the analog variable delay means 14.
It is a structural example. Analog pulse signal is input terminal a10
Input from the output terminal b10. 15i (i =
1 to n) is, for example, a continuous row of inverters for a fixed time
The delay circuit of ₁Is (1/2) T delay,
15₂Is a delay of (1/4) T, 15_FourIs (1/16) T
Analog delay like the delay of. 16i (i = 1 to 1
n) is a selector, which is a control signal Si from the latch circuit f4.
Select either Ai or Bi in (i = 1 to n)
The analog signal directly or give a specified delay.
Or

In FIG. 5 (A), as a test condition, a basic clock has a frequency of 100 MHz, one cycle of 10 ns, a pattern cycle of (5 + 3/4) T, and a timing delay time of (3 + 1/2) T. And then generated. That is, the pattern period was 57.5 ns and the timing delay time was 35 ns. Like this one
Only one timing pulse signal can be generated within the pattern cycle. However, recently, there are many cases where 2 to 4 timing pulses are required within one pattern period. In order to generate a plurality of timing pulses within this one pattern period, they are generated by the interleave method,
Interleaving has become essential. The interleave method means a method in which they are arranged alternately.

FIG. 7 shows a circuit block diagram of the interleave system, and FIG. 8 shows a timing chart thereof. As a circuit configuration, as shown in FIG. 7, two circuits of the conventional timing generator 3 of FIG. 5A are provided in parallel with 3m and 3n,
The output is combined by the OR circuit h3 to output a composite timing pulse. It is also possible to provide a plurality of three or more timing generators 3 in parallel to generate three or more timing pulses within one pattern period. The circuit operation will be described. As an example of the test condition in FIG. 7, it is assumed that the same timing pulse as in FIG. 6 is generated, the pattern period is twice (11 + 1/2) T as in the case of FIG. 6, and the timing delay time is (3 + 1/2). ) T and the other one is (9 + 1 /
4) T. A timing pulse of (3 + 1/2) T delay is generated by the timing generator 3m, and (9 + 1/4)
Timing generator 3 generates T-delayed timing pulse
leave it to n. The start of the pattern cycle of the timing generator 3n is delayed by 5T from 3m, and the set delay data is (3 + 1/2) as in the timing generator 3m.

This will be described with reference to the timing chart of FIG. FIG. 8A is a reference clock with a period of 10 ns. Figure 8
8B to 8E are timing charts of the timing generator 3m, FIGS. 8F to 8I are timing charts of the timing generator 3n, and FIG. 8G is a generation timing of the combined timing pulse.

Since the pattern period of the timing generator 3m is (11 + 1/2) T, it takes an integer and is initially as shown in FIG.
Since it is 11T as shown in B, the fraction data of the first shot is 0 as shown in FIG. 8C. Therefore, since the output data of the adder 12 is the data (3 + 1/2) of the register R, it is the integer data of 3 and the fraction data of (1/2).
Therefore, the integer of 3 is delayed by the digital means, (1/2) is delayed by the analog variable delay means, and the timing pulse is shown in FIG.
As shown in E, the delay occurs by (3 + 1/2) T.

The pattern period of the timing generator 3n is
As shown in FIG. 8F, the timing generator 3m starts 5T later than the timing generator 3m, so the fraction data of the first cycle is (3 /
4), the data is sent as shown in FIG. 8G, is added to the data (3 + 1/2) in the register R by the adder K, and the output data is (4 + 1/4) as shown in FIG. 8H. Therefore, the timing pulse shown in FIG. 8I is generated.

In the third timing pulse, that is, in the second timing generator 3m, the fraction data of the pattern period becomes (1/2) as shown in FIG. 8C, and therefore the data of the register R (3 + 1/2). Then, the output of the adder K becomes 4 as shown in FIG. 8D. Therefore, the timing pulse is generated as shown in FIG. 8E. In the same manner, continuous timing pulses are generated.

[0021]

As described above, the generation of the interleaved timing pulse is performed by arranging two sets of the timing generators 3 of FIG. 5 in parallel and alternately operating them, as shown in FIG. Apparently double speed. If 3 sets are arranged in parallel and operated alternately, the speed will be tripled. Even with this conventional circuit configuration, the semiconductor test equipment operates sufficiently.

However, the conventional circuit configuration requires a total of two sets of hardware + α or more, which may be an obstacle to downsizing, labor saving, and speeding up of the hardware. Further, each has an analog variable delay means 14. This analog variable delay means 14
Is difficult to adjust the delay time tpd, cannot be corrected by the program, and has some inherent error. Therefore, when a plurality of different analog variable delay means 14 are used to generate timing pulses, the delay linearity error, which is the difference between the expected delay value and the actual delay value, is added to the delay pulse jitter. Can cause problems.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems, to provide a new type of timing generator which is more compact and labor-saving and replaces the interleave method in which delay linearity error does not occur.

[0024]

In order to achieve the above object, the present invention provides retiming means for generating two or more timing pulses in one pattern period and for preventing delay linearity error. The analog variable delay means is commonly used for a plurality of timing pulses. In other words, a plurality of pulses set within one pattern period are generated in synchronization with the reference clock, and each pulse is subjected to analog variable delay with fractional data less than or equal to the reference clock period T to set a plurality of arbitrary timings. A pulse is generated.

The structure is as follows. Upon receiving multiple integer values N of the setting delay data sent by the tester bus,
Reference clock delay means for outputting a plurality of reference clock delay signals S obtained by delaying the reference clock cycle T by the integer value N times, and a plurality of fractional data of the set delay data sent by the tester bus are latched and set to the values. Fractional data processing means for respectively adding the fractional data of the pattern period stored in the register R by the adder Ki and outputting the carry signal (carry signal) and the fractional data in order respectively.
A carry delay means for delaying the reference clock delay signal S from the reference clock delay means by one reference clock period T and a reference clock delay means or carry only when a carry signal is sent from the carry processor of the fraction data processing means. Retiming means for receiving the reference clock delay signal S from the delay means, reproducing and outputting the timing of the reference clock delay signal S, and fraction data from the fraction data processor of the fraction data processing means for retiming Analog variable delay means for delaying and outputting the reference clock delay signal S from the means by a fractional data value.

The reference clock delay means can be composed of an up counter and a mark memory. That is, the up-counter receives a plurality of integer values N of the set delay data sent by the tester bus and sets a flag at each of the integer values N of the mark memory, and the up-counter is cleared by the cycle start signal PS. It is preferable that the reference clock is counted after that, the count value is sent to the mark memory, and the reference clock delay signal S is generated from the mark memory when the sent count value matches the flag address.

The fraction data processing means latches a plurality of fraction data of the set delay data sent by the tester bus with a latch circuit fi (i = 11 to 1 m) for temporary storage, and stores the value and the value in the register R. Adder Ki (i = 1 to m) is added to the fractional data of the existing pattern period. Here, m is the number of timing pulses generated within one pattern period. The carry signal is sequentially output by the carry processor and given to the carry delay means, and the fraction data is sequentially outputted by the fraction data processor and given to the analog variable delay means. The number of data handled by the carry processor and the fraction data processor is the number of timing pulses, m.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described based on examples with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention, FIG. 2 shows a timing chart of FIG. 1, and FIG. 3 shows an example of a block diagram of carry processor 19 and fraction data processor 20 used in FIG. . The parts corresponding to those in FIGS. 5 and 6 are designated by the same reference numerals. First, a description will be given with reference to FIGS. 1 and 2. As a test condition, the pattern cycle is (10 + 1 /
2) T, and the timing delay time is (3 + 1/2) T and (9
+1/4) T, that is, the set delay data is (3 + 1 /
2) and (9 + 1/4), and two timing pulses are generated.

The pattern period (10 + 1/2) T is controlled by the period start signal PS and the pattern period fractional data FD. That is, the pattern cycle controlled by the reference clock (FIG. 2A) is given from the input terminal a2 by alternately generating the cycle start signals PS with intervals of 10T and 11T (FIG. 2B). The pattern cycle fraction data FD of (1/2) is given (0) from the input terminal a1 in the first pattern cycle,
After that, the fraction data of the immediately preceding pattern period is given (FIG. 2C), and is temporarily stored in the register R at the time of PS signal.

Set delay data (3 + 1/2) and (9 + 1)
/ 4) and the flag bit from the input terminal a3 to the tester
It is sent within the pattern period immediately before the timing pulse is generated on the bus. That is, one pattern period is required for data setting. 3 of integer value N of setting delay data
9 and 9 are sequentially loaded into the counter 17 of the reference clock delay means 21 and the value is immediately sent to the mark memory 18, and flags are sequentially set at the integer value addresses of the mark memory 18. In this embodiment, flags are set at addresses 3 and 9. Fraction data (1/2) and (1 /
4) is sent to the latch circuit f11 and the latch circuit f12 of the fraction data processing means 22, and is temporarily stored by the control signal inversion wc1 and the inversion wc2 from the input terminals a7 and a8. The initial clear signal from a5 is also given within the pattern cycle immediately before the timing pulse is generated.

Within the pattern period immediately before the timing pulse is generated, the contents of the mark memory 18, carry processor 19 and fraction data processor 20 are cleared at the beginning, and then the set delay data is set in the mark memory 18. A flag is set at the address of the integer value N of, and the set fraction data is latched by the latch circuits f11 and f12, respectively.
It is assumed that the fraction data of the pattern cycle is latched in the register R. Therefore, it is assumed that the adders K1 and K2 of the fractional data processing means 22 output the respective addition data obtained by adding the set fractional data and the fractional data of the pattern period. Subsequent operations will be described in chronological order with reference to FIGS.

First, when the cycle start signal PS is applied from a2 (FIG. 2B), the counter 17 of the reference clock delay means 21 is cleared, and the register R fetches the fraction data (0) of the putter cycle (FIG. 2C). ). The adder K1 stores the data (0) in the register R and the data (1 in the latch circuit f11.
/ 2) is added, and the carry signal (0) is output to the carry processor 19 (FIG. 2F), and the fraction data (1/2) is output to the fraction data processor 20 (FIG. 2G). Similarly, the adder K2 uses the data (0) in the register R and the latch circuit f1.
2 is added to the data (1/4), and the carry signal (0) is output to the carry processor 19 (FIG. 2H) and the fraction data (1/4) is output to the fraction data processor 20 (FIG. 2H). Two
I). The carry processor 19 and the fraction data processor 20 of the fraction data processing means 22 are WE (write enable).
Then, at the next reference clock, adders K1 and K
Carry signals (0) and (0) from 2 and fractional data (1/2) and (1/4) are input.

After that, when the reference clock (FIG. 2A) is input from a4, the counter 17 counts the reference clock (FIG. 2D). At the address whose count value is flagged in the mark memory 18, in this embodiment, the addresses 3 and 9 (FIG. 2D), the reference clock delay signal S is output from the output terminal do (FIG. 2E), and the latch circuit j1 is temporarily operated. Store and output. The carry signal and the fraction data of the pattern period from the adders K1 and K2 have already been input to the carry processor 19 and the fraction data processor 20, and the carry (0) for the first issue is input to each latch circuit ji. The fraction data (1/2) and the carry (0) fraction data (1/4) for the second shot are sequentially stored.

In response to the signal from the latch circuit j1, the carry processor 19 becomes the output enable and outputs the carry signal from the output terminal Q and the inverted Q. Since the carry signal is (0) for the first and second shots, Q = 0 (see FIG. 2).
J) and inversion Q = 1. Therefore, carry delay means 23
The AND gate g1 is opened and the reference clock delay signal S of the latch circuit j1 is output to the retiming means 13 (FIG. 2L, N). The latch circuit j1 is provided to match the processing time of the fractional data processing means 22 and to delay the reference clock period T by 1 to match the timing (FIG. 2E,
L), depending on the speed of the processing time of the fraction data processing means 22, the timing is adjusted by eliminating or substituting a plurality of stages. Latch circuits j2 and j3 of the retiming means 13
Is provided for delaying the reference clock delay signal S by one reference clock cycle T when the carry signal is (1) (FIG. 2M).

The carry processor 19 and the fractional data processor 20 will be described later with reference to FIG. 3 for an example of the configuration. The point is that the data is sequentially output from the set delay data at the earlier timing pulse timing. . Therefore, the carry processor 19 first receives the carry signal (0) from the adder K1 at the input terminal d1 and outputs the L potential from the output terminal Q. For the second shot, the carry signal from the adder K2 is received at the input terminal d2 and the L potential corresponding to the signal is output (FIG. 2J). After that, it repeats similarly. The operation of the fraction data processor 20 is similar, and the fraction data (1/2) and (1/4) are sequentially applied to the analog variable delay circuit 14. The output fraction data is sequentially switched after confirming the output of the timing pulse in advance.

The retiming means 13 re-times the reference clock delay signal S from the carry delay means 23 with the reference clock to eliminate the slight variation in delay time up to this point (FIG. 2O), which is the same as the conventional one. Is. The analog variable delay circuit 14 is a fractional data processor 20.
The fractional data from (1) is sequentially received (FIG. 2P), the reference clock delay signal S is given a minute delay of (1/2) T and (1/4) T, and the timing pulse is output. is there.

In the second pattern cycle, the fraction data FD of the putter cycle becomes (1/2) (FIG. 2C). The register R of the fractional data processing means 22 receives the cycle start signal PS as W.
It becomes E, and (1/2) is temporarily stored at the next reference clock and given to the adders K1 and K2. The adder K1 is a latch circuit f
11 is added to the content (1/2) to output the carry signal of (1) and the fraction data of (0) (FIG. 2F, G). The adder K2 adds the content (1/4) of the latch circuit f12,
The carry signal of (0) and the fraction data of (3/4) are output (FIG. 2H, I).

Therefore, at the third shot, the output Q of the carry processor 19 becomes (1) and the inversion Q becomes (0), and the AND gate g1 is closed and the AND gate g2 is opened. The third reference clock delay signal S is transmitted from the latch circuits j1 to j.
2, through the AND gate g2 and the OR gate g3, and output to the retiming means 13. Here, the third reference clock delay signal S is delayed by one reference clock period T by the latch circuits g2 and g3 (FIG. 2K,
L, M). At the fourth shot, the output Q of the carry processor 19 becomes (0) and the inversion Q becomes (1), and the AND gate g1 opens and the AND gate g2 closes. Therefore, the fourth reference clock delay signal S is sent from the latch circuit j1 to the AND gate g.
1, and is output to the retiming means 13 via the OR gate g3 (FIG. 2K, L, N). Thereafter, the timing pulse is continuously generated in the same manner.

FIG. 3A shows a structural example of the carry processor 19. Latch circuit j for temporarily storing a plurality of data
20 and flip-flop S with WE for switching the output signal
And several gate circuits gi. That is, the carry signal from the adder K1 is input at the input terminal d1, temporarily stored and output. Similarly, the carry signal from the adder K2 is also input through the input terminal d2, temporarily stored and output. This data is sequentially switched by the signal from the latch circuit j1 and the reference clock in the flip-flop S with WE and output from the output terminal Q and the inversion Q.

FIG. 3B shows an example of the configuration of the fraction data processor 20. Here, four latch circuits j7 to j10 are used in consideration of temporary storage of four fractional data. It is also possible to alternately use two pieces of fraction data. C1 is a 1-bit counter, that is, a flip-flop, and C2 is a 2-bit counter. MU is a multiplexer. Fractional data is input to the input terminals d1 and d2, and when the cycle start signal PS becomes WE, the 1-bit counter C1 opens the NAND gate g9 at the next reference clock and the delay circuit D2 delays the reference clock so that the reference clock becomes the NAND gate g.
After passing through 9, the latch circuit j7 and j8 latch the fractional data from the input terminals d1 and d2.

The multiplexer MU is a 2-bit counter C
Controlled by 2, the signals sent to the input terminals are output in the order of A, B, C, D, A, and B, for example. The switching is performed by raising the 2-bit counter C2 by the signal RCK sent every time the timing pulse is output.

Although described in detail above, the configuration is not limited to the embodiment. The reference clock delay means 21 uses the counter 17 and the mark memory 18, but may have another configuration. The point is that the reference clock delay signal S can be generated when the integer value N is counted and matched with the reference clock. Further, the fraction data processing means 22 is not limited to the configuration of the embodiment, and may have another configuration. The point is that the circuit can add the fractional data of the set delay data and the fractional data of the pattern period, and output the carry signal and the fractional data in order.

[0043]

As described above in detail, the present invention is an apparatus for generating a plurality of timing pulses in one pattern period, which is an integrated timing generator instead of the conventional interleave method. In particular, the retiming means 1
3 and the analog variable delay means 14 are integrated so that they can be used in common.

Therefore, the occurrence of delay linearity error, which has been a problem in the past, can be eliminated, and further downsizing of hardware, labor saving, and speedup can be realized. The present invention has a great effect in practical use.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of FIG.

3A is a block diagram of an example of a carry processor used in FIG. 1, and FIG. 3B is a block diagram of an example of a fractional data processor.

FIG. 4 is an example of a basic configuration diagram of a semiconductor test apparatus.

5A is an example of a basic configuration diagram of a timing generator, and FIG. 5B is an example of a configuration diagram of an analog variable means 14.

FIG. 6 is a timing chart of FIG.

FIG. 7 is a block diagram of an interleaved timing generator.

FIG. 8 is a timing chart of FIG.

[Explanation of symbols]

1 test processor 2 pattern generator 3, 3m, 3n timing generator 4 Wave shaper 5 drivers 6 comparator 7 pattern comparator 8 Failure analysis memory 9 DUT (device under test) 10 Input means 11 computing means 12 Reference clock delay means 13 Retiming means 14 Analog variable delay means 15i (i = 1 to n) analog delay device 16i (i = 1 to n) selector 17 up counter 18 mark memory 19 carry processor 20 Fractional data processor 21 Reference Clock Delay Means 22 Fractional data processing means 23 Carry delay means C, Ci counter D, Di fixed delay device R register N Set delay data integer value S reference clock delay signal T reference clock cycle K, Ki adder fi latch circuit gi gate circuit (AND circuit or OR circuit) ji latch circuit h1 match circuit h2 and circuit

Claims (3)

(57) [Claims] 1. A timing generator for a semiconductor test device, which generates a plurality of timing pulses within one pattern period, receives a plurality of integer values (N) of set delay data sent by a tester bus, and receives a reference clock period. A reference clock delay means (21) for outputting a plurality of reference clock delay signals (S) obtained by delaying (T) by the integer value (N) times, and a plurality of fraction data of setting delay data sent by a tester bus. Fractional data processing means for latching the value and the fractional data of the pattern period stored in the register (R) by an adder (Ki) and outputting the carry signal and the fractional data in order ( 22) and a carry processor (19) of the fraction data processing means (22)
Carry delay means (23) for delaying the reference clock delay signal (S) from the reference clock delay means (21) by one reference clock cycle only when the carry signal is sent from the reference clock delay means (21). Alternatively, a retiming means (13) for receiving the reference clock delay signal (S) from the carry delay means (23), reproducing and outputting the timing of the reference clock delay signal (S), and a fraction data processing means (22). ) Fractional data processor (2
0) receives the fraction data from the retiming means (1
Analog variable delay means (14) for delaying and outputting a fractional data value from the reference clock delay signal (S) from 3)
A timing generator for a semiconductor test device, comprising: 2. The reference clock delay means (22) comprises an up-counter (17) and a mark memory (18), the up-counter (17) adjusting a plurality of set delay data sent by a tester bus. Receiving a numerical value (N) and setting a flag at the integer value (N) of the mark memory (18), the up counter (17) is cleared by the cycle start signal (PS) and counts the subsequent reference clock. The reference clock delay signal (S) is generated from the mark memory (18) when the count value is sent to the mark memory (18) and the sent count value and the flag address match. Timing generator for semiconductor test equipment. 3. The fraction data processing means (22) latches a plurality of fraction data of the set delay data sent by the tester bus by a latch circuit (fi) for temporary storage, and stores the values and a register (R) in the register (R). The adder (Ki) and the carry data are sequentially output by the carry processor (19) to the carry delay means (23), and the carry data is processed as a fraction data. The analog variable delay means (1
4. The timing generator for a semiconductor test apparatus according to claim 1, wherein the timing generator is applied to 4).