JP3501125B2 - Electro-optical device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technical field of an electro-optical device of an active matrix driving system, and in particular, it is provided with a capacitance line for adding a storage capacitance to a pixel electrode and used for pixel electrode and pixel switching Belongs to the technical field of an electro-optical device of a type in which a conductive film for achieving good electrical conduction with a thin film transistor (hereinafter, appropriately referred to as a TFT) is provided in a laminated structure on a substrate.

[0002]

2. Description of the Related Art Conventionally, in an electro-optical device such as a liquid crystal device of an active matrix driving system driven by TFT,
When the scanning signal is supplied to the gate electrode of the TFT via the scanning line, the TFT is turned on, and the image signal supplied to the source region of the semiconductor layer via the data line is applied to the TFT.
Is supplied to the pixel electrode via the source / drain of.
Since such an image signal is supplied to each pixel electrode via each TFT for an extremely short time, the voltage of the image signal supplied via the TFT is set to be much longer than the time when the image signal is turned on. In order to hold the pixel electrode for a long time, a storage capacitor is generally added to each pixel electrode.

[0003]

In the electro-optical device of this type, there is a strong general demand for improving the quality of a display image. For this reason, in each pixel, a non-pixel opening region through which display light does not pass is transmitted. On the other hand, it is extremely important to increase the pixel aperture ratio and at the same time increase the storage capacitance to be added to each pixel electrode while making the pixel pitch finer by widening the pixel aperture region through which the display light is transmitted. Become.

Generally, since the storage capacitor is formed by utilizing the non-pixel opening region, it is basically difficult to build the storage capacitor in the pixel opening region. Therefore, as the pixel opening area is expanded so as to increase the pixel opening ratio, the non-pixel opening area in which the storage capacitor can be built becomes narrower.
Alternatively, there is a problem that the pixel aperture ratio decreases as the non-pixel aperture region is expanded so as to increase the storage capacitance.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an electro-optical device capable of increasing a pixel aperture ratio and at the same time increasing a storage capacity and capable of displaying a high-quality image. It is an issue.

[0006]

In order to solve the above problems, an electro-optical device of the present invention corresponds to a scanning line, a data line intersecting the scanning line, and the scanning line and the data line on a substrate. And a pixel electrode provided corresponding to the thin film transistor, wherein the thin film transistor includes a semiconductor layer having a channel region, and a gate electrode arranged to face the channel region. The channel region is located in the region of the data line, and the channel region and the scanning line extend above the gate electrode and below the data line. A capacitive electrode,
It is characterized in that a first storage capacitor is laminated with a second capacitance electrode arranged on the first capacitance electrode via an insulating film. The first storage capacitor may be formed in a region where the data line extends from the channel region.

According to the above configuration of the present invention, the first storage capacitor is formed above the scanning line and below the data line using the laminated structure, thereby increasing the storage capacity and displaying a high-quality image. It is possible to provide an electro-optical device capable of performing the above.

According to an aspect of the electro-optical device of the present invention, the first storage capacitor is arranged to face the first capacitor electrode with an insulating film interposed therebetween, and the drain region of the thin film transistor. And the pixel electrode is electrically connected to the pixel electrode. Further, the first storage capacitor electrode is formed below the data line via an insulating film, and the second storage capacitor electrode is formed above the scanning line via an insulating film. .

According to this structure of the present invention, the second capacitor electrode forming the first storage capacitor is formed as a relay film for electrically connecting the drain region of the thin film transistor and the pixel electrode. The problem that the distance between the layers is long and the electrical connection is difficult can be solved. Further, it is possible to prevent the etching through of the second capacitor electrode when the contact hole is opened.

In another aspect of the electro-optical device of the present invention, the first storage capacitor is a region of each of the semiconductor layer and the scanning line, leaving a connection region between the source region of the thin film transistor and the data line. It is characterized in that it is formed so as to overlap.

According to such a structure of the present invention, since the semiconductor layer and the scanning line are formed so as to overlap with each other, the pixel aperture ratio can be increased and at the same time the storage capacitance can be increased.

According to another aspect of the electro-optical device of the present invention, the second capacitance electrode is disposed so as to face the second capacitance electrode via an insulating film, and the third capacitance electrode is made of the same film as the scanning line. The second storage capacitor is formed by.

According to this structure of the present invention, the second storage capacitor is formed by utilizing the second capacitance electrode forming the first storage capacitance and the scanning line layer, so that the storage capacitors are stacked in the thickness direction of the substrate. Therefore, even if the pixel pitch is made fine, a relatively large storage capacitor can be built in the non-opening region. Further, since the third capacitor electrode is made of the same film as the scanning line, the storage capacitor can be constructed with a laminated structure having a relatively small number of layers.

In another aspect of the electro-optical device of the present invention, the third capacitance electrode is formed in parallel with the scanning line, leaving a connection region between the drain region of the thin film transistor and the second capacitance electrode. It is characterized by

According to this structure of the present invention, since the third capacitance electrode is formed in parallel with the scanning line, the storage capacitance can be increased by utilizing the non-opening region.

Another aspect of the electro-optical device of the present invention is characterized in that the third capacitance electrode is electrically connected to the first capacitance electrode.

According to such a configuration of the present invention, since there is no potential fluctuation between the first capacitance electrode and the third capacitance electrode, it is possible to prevent a situation that affects the characteristics of the thin film transistor.

In another aspect of the electro-optical device of the present invention, the electrical connection portion between the third capacitance electrode and the first capacitance electrode is
It is located in the lower region of the data line.

According to such a configuration of the present invention, a region below the data line in the gap region between the pixel electrodes, which cannot be used as the aperture region of each pixel, is connected to the third capacitance electrode and the first capacitance electrode. Since it is used, it is very advantageous in achieving a high aperture ratio of the pixel.

In another aspect of the electro-optical device of the present invention, the third capacitance electrode is a part of a first capacitance line extending along the scanning line, and the first capacitance electrode extends along the scanning line. The first capacitance line and the second capacitance line are formed by a part of the extending second capacitance line, and are extended and electrically connected to the periphery of the image display region in which the pixel electrode is arranged. Characterize.

According to such a configuration of the present invention, the first capacitance line including the plurality of third capacitance electrodes arranged along the scanning line and the plurality of first capacitance electrodes arranged along the scanning line are included. Since the second capacitance line is electrically connected to each other outside the image display region, the third capacitance electrode and the first capacitance electrode can be relatively easily and reliably connected to each other. It becomes possible to electrically connect to each other via the. Moreover, since it is not necessary to provide a contact hole for connecting the both in the image display area, the storage capacity can be increased.

According to another aspect of the electro-optical device of the present invention, the third capacitance electrode is arranged to face the third capacitance electrode via an insulating film, and the fourth capacitance electrode is made of the same film as the semiconductor layer. Is characterized in that the third storage capacitor is formed.

According to such a configuration of the present invention, since the third storage capacitor is formed using the third capacitor electrode forming the second storage capacitor and the semiconductor layer, the storage capacitors can be stacked in the thickness direction of the substrate. Therefore, even if the pixel pitch is miniaturized, a relatively large storage capacitor can be built in the non-opening region. Moreover, since the fourth capacitor electrode is made of the same film as the semiconductor layer, the storage capacitor can be constructed by a laminated structure having a relatively small number of layers.

Another aspect of the electro-optical device of the present invention is characterized in that the fourth capacitor electrode is formed so as to extend from the drain region of the thin film transistor.

According to this structure of the present invention, the storage capacitor can be formed by utilizing the drain region of the thin film transistor.

Another aspect of the electro-optical device of the present invention is characterized in that the fourth capacitor electrode is formed in parallel with the scanning line.

According to this structure of the present invention, since the third capacitance electrode is formed in parallel with the scanning line, the storage capacitance can be increased by utilizing the non-opening region.

In another aspect of the electro-optical device of the present invention, the capacitance of the second storage capacitor is the first storage capacitor and the third storage capacitor.
It is characterized in that it is small for each capacity of the storage capacity.

According to such a structure of the present invention, the second capacitor composed of the first capacitor electrode and the third electrode formed of the same film as the scanning line is formed.
Since the storage capacitance is reduced, the capacitance can be formed to the extent that it does not affect the malfunction of the TFT.

In another aspect of the electro-optical device of the present invention, the fourth capacitor electrode formed of the same film as the semiconductor layer and the fourth capacitor electrode are arranged to face the fourth capacitor electrode via an insulating film, and the semiconductor layer is shielded from light. The fourth storage capacitor is formed by the fifth storage capacitor electrode.

According to this structure of the present invention, the fourth storage capacitor is formed by using the fourth capacitor electrode formed of the same film as the semiconductor layer forming the third storage capacitor and the light shielding film for shielding the semiconductor layer. Since the storage capacitors can be stacked in the thickness direction of the substrate, a relatively large storage capacitor can be built in the non-aperture area even if the pixel pitch is made fine.
Further, since the fifth capacitor electrode is formed of the light shielding film, the storage capacitor can be constructed with a laminated structure having a relatively small number of layers. In addition, since the light-shielding film covers at least the channel region as viewed from the substrate side, it is possible to effectively prevent the return light from the substrate side from entering the channel region and changing the characteristics of the thin film transistor.

Another aspect of the electro-optical device of the present invention is characterized in that the fifth capacitance electrode is electrically connected to the first capacitance electrode in the periphery of the image display region.

According to this structure of the present invention, the first capacitance electrode, the fifth capacitance electrode, and the third capacitance electrode can be set to a common potential, and a stable storage capacitance can be formed.

According to another aspect of the electro-optical device of the present invention, a fifth capacitance electrode and a sixth capacitance electrode which is arranged to face the first capacitance electrode via an insulating film and constitutes the pixel electrode are fifth. It is characterized by forming a storage capacitor.

According to this structure of the present invention, since the fifth storage capacitor is formed by using the first capacitance electrode forming the first storage capacitor and the pixel electrode, the storage capacitors can be stacked in the thickness direction of the substrate. Therefore, even if the pixel pitch is miniaturized, a relatively large storage capacitor can be built in the non-opening region. Further, since the sixth capacitor electrode is composed of the pixel electrode, the storage capacitor can be constructed with a laminated structure having a relatively small number of layers.

Another aspect of the electro-optical device of the present invention is characterized in that the fifth storage capacitor is formed over substantially the entire circumference of one pixel.

According to this structure of the present invention, the storage capacity can be increased by utilizing the peripheral region of one pixel.

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) The configuration of a liquid crystal device which is an example of the electro-optical device of the present invention will be described with reference to FIGS. 1 to 11. FIG. 1 is an equivalent circuit of various elements, wirings, etc. in a plurality of pixels formed in a matrix which configures an image display area of a liquid crystal device, and FIG. 2 shows data lines, scanning lines, pixel electrodes, etc. FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate, and FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2. In FIG. 3, the scales of the layers and members are made different so that the layers and members are recognizable in the drawing.

In FIG. 1, a plurality of pixels formed in a matrix form the image display area of the liquid crystal device of this embodiment are provided with a pixel electrode 9a and a TFT 30 for controlling the pixel electrode 9a. The data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. Image signal S to be written in the data line 6a
, S2, ..., Sn may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Also, T
The scanning line 3a is electrically connected to the gate of the FT 30, and the scanning signal G1 is supplied to the scanning line 3a at a predetermined timing.
, Gm are line-sequentially applied in this order. The pixel electrode 9a is electrically connected to the drain of the TFT 30 and serves as a switching element T.
By closing the switch of the FT 30 for a fixed period, the image signals S1, S2 supplied from the data line 6a,
..., Sn is written at a predetermined timing. Pixel electrode 9a
The image signal S of a predetermined level written in the liquid crystal through the
, S2, ..., Sn are held for a certain period of time with a counter electrode (described later) formed on a counter substrate (described later). The liquid crystal modulates light by changing the orientation and order of the molecular assembly depending on the applied voltage level, and enables gradation display. In the normally white mode, the transmitted light amount of the incident light decreases according to the applied voltage, and in the normally black mode, the transmitted light amount of the incident light increases according to the applied voltage. Light having a contrast ratio according to the image signal is emitted from the device.
Here, in order to prevent the held image signal from leaking, the storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacity 70 is
One capacitance electrode electrically connected to the pixel electrode 9a,
It is formed between the capacitance line 300 to which a constant potential is supplied and the other capacitance electrode electrically connected via a dielectric film.
The storage capacitor 70 holds, for example, the voltage of the pixel electrode 9a for a time that is three orders of magnitude longer than the time when the source voltage is applied. As a result, the holding characteristic is further improved, and a liquid crystal device having a high contrast ratio can be realized.

In FIG. 2, a plurality of transparent pixel electrodes 9a are arranged in a matrix on the TFT array substrate of the liquid crystal device.
(The pixel electrode end 9a 'is shown by a dotted line portion), and the data line 6a and the scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively. The scanning line 3a is arranged so as to face the channel region 1a '(the region of the diagonal line on the lower right in the drawing) of the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. In this way, the TFTs 30 are provided at the intersections of the scanning lines 3a and the data lines 6a, respectively, in the channel region 1a ', in which a part of the scanning lines 3a is arranged as a gate electrode so as to face each other. The pixel electrode 9a relays the relay film 80a which is an intermediate conductive film,
The semiconductor layer 1a is electrically connected to a drain described later through the contact holes 8a and 8b. The data line 6a is electrically connected to a later-described source region of the semiconductor layer 1a made of a polysilicon film or the like through the contact hole 5.

Further, the capacitive electrode 3b (which is made of the same film as the scanning line 3a) is formed so as to at least partially overlap the capacitive electrode 1f (fourth capacitive electrode) extending from the semiconductor layer 1a with a gate insulating film described later interposed therebetween. A third capacitor electrode) may be provided. Thereby, at least a part of the storage capacitor 70 in FIG. 1 can be formed.

Further, a base light-shielding film 11a is provided in each of the regions shown by thick lines in FIG. 2 so as to pass below the TFT 30 along the scanning line 3a. More specifically, the base light-shielding film 11a is provided at a position that covers at least the channel region 1a ′ of the TFT and the junction region of the channel region 1a ′ and the source and drain regions, respectively, when viewed from the TFT array substrate side. . Further, it is preferable that the pixel electrodes 9a extend in the periphery of the image display region formed in a matrix along the direction of the scanning line 3a and are connected to the constant potential source in the peripheral region. Thus, by fixing the potential of the base light-shielding film 11a at a constant potential, T
A malfunction of the FT 30 can be prevented. As the constant potential source, a peripheral circuit for driving the liquid crystal device described later,
For example, a constant potential source such as a negative power source or a positive power source supplied to the scan line driving circuit or the data line driving circuit, a ground power source, a constant potential source supplied to the counter electrode, or the like can be given. If the potential level is set, it is desirable to keep the scanning signal supplied to the scanning line 3a at the off level. As a result, almost no parasitic capacitance is generated between the scanning line 3a and the scanning line 3a, so that the scanning signal supplied to the scanning line 3a is hardly delayed.

In this embodiment, in particular, a light-shielding conductive film (first capacitance electrode) 90 is provided in a region shown by a diagonal line rising to the right in the figure.
a is formed. The light-shielding conductive film 90a is formed between the scanning lines 3a and the data lines 6a, and the wirings such as the data lines 6a and the scanning lines 3a and the TFTs 3 except the regions where the contact holes 5 and the contact holes 8b are formed.
Since it can be overlapped with 0 or a storage capacitor formation region in a plan view, it is possible to realize light shielding on the TFT array substrate. In addition, the light-shielding conductive film 90a is formed on the scanning line 3a.
It is possible to extend from the image display area to the periphery thereof in the direction of and to connect to the constant potential source in the peripheral area. As a result, the light-shielding conductive film 90a becomes the capacitance line 300 in FIG.
Can function as. Further, through the contact hole 95, the capacitance electrode 3b made of the same film as the scanning line 3a is formed.
By connecting to the capacitor electrode 1f, a constant potential is supplied, so that the storage capacitor 70 can be easily formed with the capacitor electrode 1f. As the constant potential source, a peripheral circuit for driving the liquid crystal device described later, for example, a negative power source supplied to a scanning line drive circuit, a data line drive circuit or the like, a constant potential source such as a positive power source, a ground power source, or a counter source. The constant potential source etc. which are supplied to an electrode are mentioned.

Next, as shown in the sectional view of FIG. 3, the liquid crystal device according to the present embodiment has a transparent T structure which constitutes an example of the substrate.
An FT array substrate 10 and a transparent counter substrate 20 arranged to face the FT array substrate 10 are provided. The TFT array substrate 10 is
For example, it is made of a quartz substrate, a glass substrate or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. The TFT array substrate 10 is provided with a pixel electrode 9a made of a transparent conductive film such as an ITO film,
When a TN (Twisted Nematic) liquid crystal or the like is used for the liquid crystal layer 50, the alignment film 16 subjected to a predetermined alignment treatment such as a rubbing treatment is provided on the surface of the pixel electrode 9a.

On the other hand, the counter substrate 21 is provided with a counter electrode 21 made of a transparent conductive film such as an ITO film over the entire surface thereof, and the surface of the counter electrode 21 is subjected to a predetermined alignment treatment such as a rubbing treatment. The applied alignment film 22 is provided.

Further, a base light-shielding film 11a is provided between the TFT array substrate 10 and the TFT 30 at a position facing the TFT 30. Base light-shielding film 11a
Are formed at least at positions facing the channel region 1a ′ of the pixel switching TFT 30 and the junction region of the channel region 1a ′ and the source and drain regions, so that reflected light from the TFT array substrate 10 side, etc. The channel region 1a 'and its adjacent region are not irradiated. As a result, the characteristics of the TFT 30 do not change due to the generation of leak current caused by light. The base light-shielding film 11a is preferably Ti (titanium) or Cr.
(Chrome), W (tungsten), Ta (tantalum),
It is preferably composed of a simple metal, an alloy, a metal silicide or the like containing at least one opaque refractory metal such as Mo (molybdenum) and Pb (lead). Alternatively, an antireflection film of polysilicon or the like may be formed on the surface of the base light-shielding film 11a so that the light can be absorbed even if the incident light directly goes around. Further, when the light reflected from the TFT array substrate 10 side is weak, a polysilicon film may be used for the base light-shielding film 11a. Underlayer light-shielding film 1 from such a material
With the configuration of 1a, it is possible to prevent the base light-shielding film 11a from being destroyed or melted by the high temperature treatment in the formation of the gate insulating film 2, for example. In the present embodiment, the underlying light-shielding film 11a is formed below each scanning line 3a in a striped pattern along the scanning line 3a, but below each data line 6a is striped along the data line 6a. It is needless to say that they may be formed in a rectangular shape or may be formed in a grid pattern below each scanning line 3a and each data line 6a. By forming the underlying light-shielding film 11a in a striped pattern in this manner, the stress due to the underlying light-shielding film 11a can be relaxed, and by forming the underlying light-shielding film 11a, not only the light-shielding property is improved but also the underlying light-shielding film 11a is further reduced in resistance. Can be achieved.

A base insulating film 12 is provided between the base light-shielding film 11a and the TFT 30. The base insulating film 12 is provided to electrically insulate the semiconductor layer 1a forming the TFT 30 from the base light shielding film 11a. Further, the base insulating film 12 is formed on the TFT array substrate 10
By being formed on the entire surface of, the TFT also has a function as a base film for the TFT 30. That is, it has a function of preventing the characteristics of the TFT 30 from changing due to the roughness of the surface of the TFT array substrate 10 during polishing, the stain remaining after cleaning, and the like. The base insulating film 12 is, for example, NSG (non-doped tosilicate glass), PSG (phosphosilicate glass), or BS.
It is made of a highly insulating glass such as G (boron silicate glass) or BPSG (boron phosphorus silicate glass), or a silicon oxide film, a silicon nitride film, or the like. Further, the underlying insulating film 12 can prevent the underlying light shielding film 11a from contaminating the TFT 30 and the like.

Further, in the present embodiment, the TFT 30 formed on the base insulating film 12 has an LDD (Lightly Doped Drai).
n) structure, the semiconductor layer 1a made of, for example, a polysilicon film has a low-concentration source region 1b and a low-concentration drain region 1c sandwiching a channel region 1a ′ in which a channel is formed by an electric field from the scanning line 3a. And the high concentration source region 1d is connected to the low concentration source region 1b,
The high concentration drain region 1e is connected to the low concentration drain region 1c. As described above, by forming the TFT 30 with the LDD structure, the leak current when the TFT 30 is off can be significantly reduced, and the holding performance can be improved. Further, the TFT 30 may have an offset structure in which impurities are not implanted in the low concentration source region 1b and the low concentration drain region 1c, or the scanning line 3 may be used.
A self-aligned TFT in which a high-concentration source region 1d and a high-concentration drain region 1e are formed in a self-aligned manner by using a gate electrode which is a part of a as a mask to implant impurities at a high concentration may be used.

The gate insulating film 2 is formed on the semiconductor layer 1a as a thin film having a thickness of 100 nm or less. As the gate insulating film 2, a dense and highly insulating film can be formed by oxidizing a polysilicon film at a high temperature of 1000 ° C. or higher. If high temperature processing is not possible, use CVD (Chemical Vapor Dep
osition) or the like. On the gate insulating film 2, for example, a scanning line 3a formed of a low resistance polysilicon film into which P (phosphorus) is implanted is arranged, and the semiconductor layer 1 is formed.
The scanning line 3a in a portion overlapping with a functions as a gate electrode.

Gate insulating film 2 formed on semiconductor layer 1a
And an interlayer insulating film 81 is deposited on the scanning line 3a by CVD or the like, and at a predetermined position of the high-concentration drain region 1e,
A contact hole 8a is opened in the gate insulating film 2 and the interlayer insulating film 81. The high-concentration drain region 1e is electrically connected to the conductive relay film 80a through the contact hole 8a. The interlayer insulating film 9 is formed on the relay film 80a.
1, the interlayer insulating film 4 and the interlayer insulating film 7 are sequentially stacked, and a contact hole 8b is opened at a predetermined position of the relay film 80a (second capacitance electrode) with respect to these interlayer insulating films. The relay film 80a and the pixel electrode 9a are electrically connected through the contact hole 8b. Thus, the relay film 80a functions as an intermediate conductive film for electrically connecting the semiconductor layer 1a and the pixel electrode 9a. With this relay film 80a, for a long distance from the pixel electrode 9a to the semiconductor layer 1a,
Since it is not necessary to open the contact hole at once, it is possible to prevent the semiconductor layer 1a having a very thin film thickness of, for example, about 50 nm from penetrating. Further, there is an advantage that the diameters of the contact holes 8a and 8b can be reduced by forming the contact holes separately. This allows
Since the area for forming the contact holes 8a and 8b can be small, the pixel aperture ratio can be increased and high definition can be realized. The material of the relay film 80a is Ti, Cr, W, Ta, M as in the case of the base light-shielding film 11a.
If it is formed of a simple metal, alloy, metal silicide or the like containing at least one opaque refractory metal such as o and Pb, it can function as a light shielding film. Further, since the selection ratio at the time of etching is high, even if the relay film 80a is formed to have a film thickness of, for example, about 50 nm, it does not penetrate through the relay film 80a when the contact hole 8b is opened. Further, if the interlayer insulating film 81 for insulating the scanning line 3a and the relay film 80a is formed to have a film thickness of, for example, 500 nm or more that does not affect the switching operation of the TFT 30, the relay film 80a will be formed on the TFT 30 and the scanning line 3a. Can be provided so as to overlap with each other when viewed two-dimensionally. This allows
Since the light can be shielded below the data line 6a and in the vicinity of the semiconductor layer 1a forming the TFT 30, the incident light is directly irradiated to the channel region 1a ′ and the low concentration source region 1b and the low concentration drain region 1c which are the junction regions thereof. Or, the stray light reflected by the data line 6a or the like is not emitted.
As a result, the leak current when the TFT 30 is off can be significantly reduced, and the holding performance can be significantly improved.

In this embodiment, as shown in FIG.
A light-shielding conductive film 90a is formed on the relay film 80a via an interlayer insulating film 91. The light-shielding conductive film 90a can shield the non-opening region except the contact holes 5 and 8b, as described above. In addition, the light-shielding conductive film 9
Since 0a can function as the capacitance line 300 in FIG. 1, at least a part of the storage capacitor 70 can be formed between the conductive film 90a and the relay film 80a by using the interlayer insulating film 91 as a dielectric film. That is, the relay film 80a and the light-shielding conductive film 90a function as an electrode for forming the storage capacitor 70. Further, light can be shielded by the two layers of the relay film 80a and the light-shielding conductive film 90a in the immediate vicinity of the semiconductor layer 1a forming the TFT 30. As a result, the TFT 30
Since the leakage current at the time of turning off can be further greatly reduced, it is very advantageous for a liquid crystal device used under a strong light source such as a projection type projector. The material of the light-shielding conductive film 90a is Ti, Cr, W, Ta, Mo and Pb, like the base light-shielding film 11a or the relay film 80a.
When formed of a simple metal, an alloy, a metal silicide, or the like containing at least one opaque refractory metal such as, a wiring having a high light-shielding property and a low resistance can be realized. In addition, if a high temperature treatment of 400 degrees or more, such as activation heat treatment, is completed before forming the light-shielding conductive film 90a, a metal simple substance, an alloy, containing Al (aluminum) having a lower resistance,
The light-shielding conductive film 90a can be formed of metal silicide or the like. By forming the light-shielding conductive film 90a also serving as the capacitance line 300 with the same Al as the material of the data line 6a, the resistance of the capacitance line 300 is reduced by 2 to 3 digits as compared with the conventional polysilicon film. Can be achieved.
As a result, crosstalk in the scanning line 3a direction caused by the large time constant of the capacitance line 300 can be significantly reduced.

The light-shielding conductive film 90a may be electrically connected to the capacitor electrode 3b made of the same film as the scanning line 3a through the contact hole 95 for each pixel electrode 9a. As a result, the capacitance electrode 3b can be fixed at the same constant potential as the light-shielding conductive film 90a. Therefore, between the capacitor electrode 3b and the relay film 80a electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a, at least a part of the storage capacitor 70 is also used in this region by using the interlayer insulating film 81 as a dielectric film. Can be formed. Further, between the capacitor electrode 3b and the capacitor electrode 1f extending from the high-concentration drain region 1e of the semiconductor layer 1a, the gate insulating film 2 is used as a dielectric film to form at least a part of the storage capacitor 70 also in this region. You can also do it. Further, the contact hole 95 is formed below the data line 6a to electrically connect the semiconductor layer 1a connected to the pixel electrode 9a adjacent to the data line 6a to the data line 6a. It is advisable to make an electrical connection in the immediate vicinity of the contact hole 5. With such a configuration, it is possible to secure a large area below the data line 6a for forming the storage capacitor 70.

FIG. 4 shows an equivalent circuit diagram of one pixel constituting the liquid crystal device of this embodiment. As shown in FIG. 4, the high-concentration drain region 1e of the semiconductor layer 1a is electrically connected to the relay film 80a and the pixel electrode 9a, while the light-shielding conductive film 9 is formed.
0a and the capacitive electrode 3b are electrically connected. The light-shielding conductive film 90a extends from the image display area to the periphery thereof and is connected to the constant potential source in the peripheral area. Further, the base light-shielding film 11a and the light-shielding conductive film 90a may be electrically connected. By combining these conductive films, the storage capacitor 70 having an ideal stack structure can be formed. That is, in the present embodiment, the high-concentration drain region 1e is provided between the conductive films of the light-shielding conductive film 90a fixed to the constant potential, the capacitor electrode 3b, and the base light-shielding film 11a via the dielectric film. It becomes possible to form the capacitor electrode 1f, the relay film 80a, and the pixel electrode 9a.

Specifically, in the plan view of the adjacent pixel groups in FIG. 2, which region the storage capacitor is formed in is shown in FIGS. 5 to 9. The scales of FIGS. 2 and 5 to 9 are the same.

FIG. 5 shows a light-shielding conductive film 90a and a relay film 8.
0a shows the first storage capacitor C1 formed between the first storage capacitor C1 and the storage capacitor 0a. The interlayer insulating film 91 is used as the dielectric film. The cross-hatched area is the area where the first storage capacitor C1 is actually formed, and the contact hole 5 and the contact hole 95
In addition, the storage capacitor C1 can be formed in a considerable part of the non-opening region except the contact hole 8b. Here, when the capacitor electrode 3b is not provided, it is not necessary to open the contact hole 95 for electrically connecting the capacitor electrode 3b and the light-shielding conductive film 90a, and therefore the first electrode is also provided in this region.
The storage capacitor C1 can be formed. Further, in the present embodiment, since the first storage capacitor C1 can be formed on the channel region 1a ′ of the TFT 30 which has been impossible in the past, it is possible to improve the pixel aperture ratio and miniaturization of the transmissive liquid crystal device. Is very advantageous. As the interlayer insulating film 91, a film having a high insulating property and a high dielectric constant such as an oxide film or a nitride film can be used. Further, the relay film 80a is formed of a polysilicon film, and further, the light-shielding conductive film 90a is formed on the lower layer of the polysilicon film,
By forming the upper layer with a multilayer structure such as a light-shielding film containing a refractory metal, the interlayer insulating film 91 can be formed in a continuous process with the polysilicon film, so that a dense insulating film with few defects can be formed. You can This allows
In addition to reducing device defects, the interlayer insulating film 91a is reduced to 100n.
Since it can be formed to have a film thickness of m or less, the first storage capacitance C1 can be further increased.

Next, FIG. 6 shows a relay film 80a and a capacitor electrode 3b.
2 shows a second storage capacitor C2 formed between and. The interlayer insulating film 81 is used as the dielectric film. The cross-hatched area is an area where the second storage capacitor C2 is actually formed. The capacitor electrode 3b includes the semiconductor layer 1a and the relay film 80a.
Is divided for each pixel in the region of the contact hole 8a for electrically connecting with each other, and is electrically connected to the upper light-shielding conductive film 90a through the contact hole 95.
As shown in FIG. 6, when the capacitor electrode 3b is formed in a T shape, the second storage capacitor C2 can be efficiently formed. As the interlayer insulating film 81, a film having a high insulating property and a high dielectric constant such as an oxide film or a nitride film can be used. However, since the capacitor electrode 3b is formed of the same film as the scanning line 3a, the second storage capacitor C2
The area in which the first storage capacitor C1 is formed is smaller than the area in which the first storage capacitor C1 is formed. When the relay film 80a shields the channel region 1a ′ and its adjacent region from light, the film thickness of the interlayer insulating film 81 is required to be 500 nm or more in order to prevent malfunction of the TFT 30, so that the second storage capacitor C
2 cannot be increased as much as the first storage capacity C1.

FIG. 7 shows a third storage capacitance C3 formed between the capacitance electrode 3b and the capacitance electrode 1f. The gate insulating film 2 is used as the dielectric film. The cross-hatched area is an area where the third storage capacitor C3 is actually formed. Since the gate insulating film 2 is formed by being oxidized at a high temperature of 1000 ° C. or higher as described above, a dense and highly insulating film is formed. Therefore, the area where the third storage capacitor C3 can be formed is almost the same as the area where the second storage capacitor C2 is formed in FIG. 6, but the third storage capacitor C3 is the second storage capacitor C3.
It can be formed larger than 2. Also, the capacitor electrode 3
The third storage capacitor C3 can also be formed below the formation region of the contact hole 95 for electrically connecting the b and the upper light-shielding conductive film 90a.

Furthermore, as shown in FIG. 8, a fourth storage capacitor C4 can be formed between the capacitor electrode 1f and the base light-shielding film 11a. The base insulating film 12 is used as the dielectric film. The area of cross hatching is actually the fourth storage capacity C
4 is a region to be formed. Underlayer insulating film 12 is 500n
If the film is formed with a film thickness of m or less, the distance between the channel region 1a ′ and the base light-shielding film 11a is also reduced, so that the TFT 30 malfunctions due to the potential of the base light-shielding film 11a. Therefore,
The fourth insulating capacitance C4 may be increased by selectively thinning the underlying insulating film 12 in a region where the storage capacitor 1f and the underlying light shielding film 11a overlap each other in plan view. That is, the fourth storage capacitance C4 can be increased by thinning the portion other than the region of the base insulating film 12 facing the channel region 1a.

Further, as shown in FIG. 9, a fifth storage capacitor C5 can be formed between the pixel electrode 9a and the light-shielding conductive film 90a. The interlayer insulating film 4 and the interlayer insulating film 7 are used as the dielectric film. The cross-hatched area is an area where the fifth storage capacitor C5 is actually formed. As the interlayer insulating film 4 and the interlayer insulating film 7, for example, NSG, P
It is made of highly insulating glass such as SG, BSG, or BPSG, or a silicon oxide film, a silicon nitride film, or the like. However, since the data line 6a is formed on the interlayer insulating film 4, the displayed image is deteriorated due to the parasitic capacitance generated between the pixel electrode 9a and the data line 6a, and therefore the interlayer insulating film 7 needs to be thickened. Actually, the fifth storage capacity C5 cannot be increased as much as the first storage capacity C1.

As described above, in the liquid crystal device of the present embodiment, the first storage capacitors C1 to C5 are formed by stacking the capacitance electrodes for forming the storage capacitors 70 via the dielectric film.
Stack type storage capacity consisting of 5 layers up to storage capacity C5 7
0 can be formed. Thereby, even if the area for forming the storage capacitor is small, the large storage capacitor 70 can be efficiently formed. Here, in the liquid crystal device of the present embodiment, at least the first storage capacitor C1 can be formed.
In the future, even if the aperture ratio and the size of pixels are further increased and, for example, the storage capacitor electrode 3b cannot be formed, according to the structure of the present embodiment, the interlayer which is the dielectric film of the first storage capacitor C1 can be formed. By thinning the insulating film 91, a sufficient storage capacity 70 can be obtained.
Can be obtained. Therefore, according to the present embodiment, it is possible to select and use from among the storage capacitors of the first storage capacitor C1 to the fifth storage capacitor C5, which is advantageous for the specifications that meet the purpose of the electro-optical device. .

As shown in FIG. 3 again, the data line 6a is
It is formed on the interlayer insulating film 4 above the light-shielding conductive film 90a. Further, the data line 6a is connected to the gate insulating film 2,
Contact holes 5 are opened at predetermined positions in the interlayer insulating film 81, the interlayer insulating film 91, and the interlayer insulating film 7, and the high-concentration drain region 1 of the semiconductor layer 1 a is opened through the contact holes 5.
It is electrically connected to e. Further, since the image signal is supplied to the data line 6a, the data line 6a is made of a metal film such as Al having a low resistance and a high light shielding property, a metal silicide, or the like.

Here, in the liquid crystal device of the present embodiment, in addition to the data line 6a, the light-shielding conductive film 90a or the like can define a light-shielding region which is a non-opening region. Specifically, as shown in FIG. 10, a light-shielding conductive film 90a is formed so as to overlap the pixel electrode 9a, and the channel region 1a ′ is formed.
Most of the area including is shaded. Further, since most of the area along the data line 6a can be shielded by the light-shielding conductive film 90a, it is not necessary to define the light-shielding area only by the data line 6a as in the conventional case, and the data line 6a and the pixel electrode can be prevented. 9a and 9a can be configured so as not to overlap with each other through the interlayer insulating film 7. As a result, the parasitic capacitance between the data line 6a and the pixel electrode 9a can be significantly reduced, and the display quality is not deteriorated due to the potential variation of the pixel electrode 9a. However, the light-shielding conductive film 9
Since 0a is formed below the data line 6a, the region where the contact hole 5 for electrically connecting the data line 6a and the semiconductor layer 1a is formed cannot be shielded from light. Therefore,
The region where the contact hole 5 is formed may be formed wide so that the data line 6a partially overlaps the pixel electrode 9a. If the region where the contact hole 5 is formed is located in the immediate vicinity of the channel region 1a ', the light-shielding conductive film 90a cannot sufficiently shield the vicinity of the channel region 1a'.
In such a case, there is no problem even if the formation region of the contact hole 5 is moved along the data line 6a in the direction away from the channel region 1a '. In this embodiment, there is an advantage that the first storage capacitance C1 formed between the relay film 80a and the light-shielding conductive film 90a does not change even if the formation region of the contact hole 5 is moved in this way. Also,
The light-shielding conductive film 90a includes the relay film 80a and the pixel electrode 9a.
Since it cannot be provided in the formation region of the contact hole 8b for electrically connecting and, this region may be shielded by the relay film 80a. If the relay film 80a is formed of a light transmissive film such as a polysilicon film, the base light shielding film 11a may shield light. At this time, the formation region of the contact hole 8b should be kept away from the channel region 1a '. As shown in FIG. 10, if the contact hole 8b is provided between the adjacent data lines 6a, even if the incident light is applied to the base light-shielding film 11a, it does not reach the channel region 1a ′, which is advantageous. is there. In addition, since the pixel configuration can be formed line-symmetrically with respect to the data line 6a, for example, in a projector or the like in which liquid crystal devices having different twist directions of TN liquid crystal are combined, deterioration of display image quality such as color unevenness does not occur.

As described above, in the present embodiment, the light-shielding region can be defined on the TFT array substrate 10, so that
As shown in FIG. 3, it is not necessary to provide a light shielding film on the counter substrate 20. Therefore, when the TFT array substrate 10 and the counter substrate 20 are mechanically bonded to each other, even if the alignment is deviated, there is no light-shielding film on the counter substrate 20, so that the light transmitting region (opening region) is not changed. Absent. As a result, a stable pixel aperture ratio can always be obtained, and device defects can be greatly reduced.

Further, the liquid crystal device according to the present embodiment can have a structure stronger than the conventional structure with respect to the incident angle of the incident light. Therefore, description will be made with reference to FIG. Figure 11
(1) is a sectional view taken along the line BB ′ in FIG.
FIG. 11 (2) shows a conventional structure. Incidentally, FIG.
(1) and (2) are shown at the same scale.

Generally, when the vicinity of the channel region of the semiconductor layer 1a is irradiated with light, a leak current is generated by photoexcitation when the TFT 30 is turned off, so that the ability to retain the charges written in the pixel electrode 9a is deteriorated. Will end up. Therefore, in the present embodiment, as shown in FIG. 11A, a conductive film 90a that shields the incident light L1 is provided, and TF
With respect to the reflected light L2 from the direction of the T array substrate 10, the base light-shielding film 11a is provided to prevent the semiconductor layer 1a from being irradiated with light. Further, since the reflected light L2 is applied to the incident light L1 in an amount not more than 1/100, the width of the light-shielding conductive film 90a for shielding the incident light L1 in the channel region and its adjacent region. W
1 is longer than the width W2 of the base light-shielding film 11a. That is, the base light-shielding film 11a is formed so as not to protrude from the light-shielding conductive film 90a in the channel region and its adjacent region. Further, the width W3 of the semiconductor layer 1a is configured to be shorter than the width W2 of the base light-shielding film 11a in the channel region and its adjacent region. That is, the channel region and its adjacent region are covered with the base light-shielding film 11a when viewed from the TFT array substrate side. By adopting such a configuration, even if the incident light L1 is incident at an angle, it is possible to reduce the possibility that the light will reach the semiconductor layer 1a. Further, in the present embodiment, the light-shielding conductive film 90a is connected to the data line 6a and the semiconductor layer 1.
Since it can be formed between the layers a, it becomes possible to shield light in the immediate vicinity of the channel region as compared with the case where the data line 6a shields the channel region as in the conventional example shown in FIG. 11 (2). Now, let us consider a margin for the incident angle of the incident light L1 in the present embodiment and the conventional example. In general, it is unlikely that the incident light L1 is directly applied to the semiconductor layer 1a because the width W3 of the semiconductor layer 1a is short, for example, 1 μm. Therefore, the semiconductor layer 1a
It is assumed that the light applied to the underlying light-shielding film 11a provided below the mirror is reflected and applied to the semiconductor layer 1a. Here, it is assumed that the widths of the base light-shielding films 11a shown in (1) this embodiment and (2) conventional examples in FIG. 11 are the same W2. Further, the width of the light-shielding conductive film 90a in the present embodiment for blocking the incident light L1 and the width of the data line 6a in the conventional example are the same W1. In this embodiment, the base light-shielding film 11
The interlayer distance between a and the light-shielding conductive film 90a is D1, while in the conventional example, the interlayer distance between the underlying light-shielding film 11a and the data line 6a is D2. Here, when the interlayer distance between the base light-shielding film 11a and the data line 6a in the present embodiment is D2, the relationship of D1> D2 is satisfied. Therefore, the incident light L1
Are incident at the same angle, there is a margin in the angle of the incident light L1 in this embodiment because the interlayer distance to the underlying light shielding film 11a is short. That is, if the margin angle of the incident light L1 in this embodiment is R1 and the margin angle of the incident light L1 in the conventional example is R2,
R1> R2. From this result, the liquid crystal device of the present embodiment has a margin in the incident angle of the incident light, which is advantageous since it can cope with the future reduction in the size of the optical system and a larger incident angle. . In the present embodiment, it is also possible to form a light-shielding film on the side surface of the semiconductor layer 1a via an insulating film, and it is possible to further improve the response to the incident angle.

Further, in the liquid crystal device of the present embodiment, it is not necessary to shield the data line 6a from light as in the conventional example, so that the width W of the data line 6a in the channel region and its adjacent region is reduced.
4 can be made shorter than the width W1 of the light-shielding conductive film 90a. That is, the relationship of W1> W4 is established, and the data line 6a is formed so as not to protrude from the light-shielding conductive film 90a in the channel region and its adjacent region. This can prevent light reflected by the data line 6a from becoming stray light and irradiating the semiconductor layer 1a. In particular, since the light-shielding conductive film 90a can be formed of a film containing a refractory metal having a lower reflectance than Al forming the data line 6a, the conductive film 90a which shields stray light from the data line 6a can be formed. It is also possible to absorb with.

Further, in the liquid crystal device of this embodiment, since the relay film 80a can be formed below the light-shielding conductive film 90a, the relay film 80a can be used to form the semiconductor layer 1a.
Can be shielded in the immediate vicinity, and the light shielding property is improved. In this case, the width of the relay film 80a is equal to the width W of the light-shielding conductive film 90a.
When it is set to be substantially the same as 1, the light shielding property is further improved. If the reflected light L2 is incident from the TFT array substrate 10 side, in the conventional example, the data line 6a having a high reflectance is used as a light-shielding film. Therefore, the stray light reflected below the data line 6a is reflected in the semiconductor layer. Although there is a risk of irradiation of 1a, light is absorbed by forming the relay film 80a with a polysilicon film or a film containing a low-reflecting refractory metal in the present embodiment. As a result, the stray light reflected on the inner surface can be significantly reduced, and there is no need to worry about deterioration of image quality display due to leakage of the TFT 30. Further, by forming the relay film 80a with a low-reflecting film, the light-shielding conductive film 90a may be formed with a film containing at least the same highly reflective Al as the data line 6a. As described above, the data line 6a and the light-shielding conductive film 90a can be formed of a film containing at least a high-reflectance Al having a reflectance of 80% or more in the visible light region in the light-shielding region of the liquid crystal device. As a result, the incident light can be reflected by the data line 6a and the light-shielding conductive film 90a to prevent the temperature rise of the liquid crystal device. Therefore, in the liquid crystal device according to the present embodiment, for example, it is possible to reduce the cost for developing a projector cooling device and improve the light resistance of the liquid crystal device.

In the present embodiment described above, the surface of the interlayer insulating film 7 under the pixel electrode 9a is flattened. This is to prevent the disclination of the liquid crystal due to the step difference of the wiring or the element, and may be performed to the interlayer insulating film 4 and the like further below. Here, as the planarization treatment, an organic or inorganic SOG (Silicon On Glass) film may be applied by a spin coater, or the CMP treatment may be performed to achieve the planarization.

(Second Embodiment) The configuration of the second embodiment of the electro-optical device of the present invention will be described with reference to FIGS. 12 to 16.

A liquid crystal device, which is an example of an electro-optical device, must generally be subjected to AC inversion drive in order to prevent deterioration of the liquid crystal. Therefore, although some driving methods have been proposed, in the liquid crystal device according to the second embodiment of the present invention, as shown in FIG.
As shown in FIG. 3, the polarity of the image signal applied to the liquid crystal is inverted for each scanning line 3a, and in addition, the polarity of the image signal is inverted for each field. As a result, the direct current component applied to the liquid crystal can be suppressed as much as possible, and the occurrence of flicker can be significantly reduced. In this way, when the polarity of the image signal is inverted for each scanning line 3a, the scanning line 3a
Since the image signals of the same polarity are written in the pixel electrodes 9a adjacent to each other along the X direction, an electric field is not generated between the adjacent pixel electrodes 9a. On the other hand, since image signals of different polarities are written in the pixel electrodes 9a adjacent to each other in the Y direction along the data line 6a, an electric field is generated between the adjacent pixel electrodes 9a, and liquid crystal disclination 4 is generated.
00 occurs.

Therefore, in order to minimize the generation region of the disclination 400 in FIG. 12, in the second embodiment of the present invention, as shown in FIG. 13, a plurality of pixel groups adjacent to each other on the TFT array substrate are arranged. Is a groove 10 ′ with respect to the TFT array substrate 10 in the diagonally right upward area.
Are formed, and wirings such as the data line 6a and the TFT 30 are partially embedded and planarized. When the rubbing process is performed on the TFT array substrate in the direction of the arrow, the region where the disclination 400 is generated is further increased by not providing the groove 10 ′ in the region of the scanning line 3 a that is in contact with the opening region. It can be reduced. Thereby, the light leakage area of each pixel is reduced, and the pixel aperture ratio can be significantly improved. In particular, it is most suitable for a liquid crystal device for a projector which requires brightness and a small size.

FIG. 14 is a sectional view taken along the line AA 'in FIG. As shown in FIG. 14, the groove 10 ′ is formed in the TFT array substrate 10 in the region where the TFT 30 and the storage capacitor 70 are formed.
By forming, the pixel electrode 9a and the alignment film 16 can be formed substantially flat. The groove 10 'can be easily formed by photolithography and etching which are commonly used in pattern formation. Further, the taper angle of the side wall of the groove 10 'can be variously controlled by making full use of the dry etching method and the wet etching method. Further, the control of the depth of the groove 10 'is important for the planarization after forming the groove 10', but it can be easily controlled by the time management of dry etching or the like. As described above, when the groove 10 'is formed and flattened, the flattening can be realized without using any organic film or the like that is easily exposed to light, and therefore, a liquid crystal used in a projector using a strong light source. The device is particularly advantageous.

FIG. 15 is a sectional view taken along the line BB ′ of FIG. 13, showing the pixel electrodes 9a adjacent to each other in the X direction in FIG.
The cross-sectional structure between them is shown. In this way, the TFT array substrate 1
By forming the groove 10 ′ in 0, the formation region of the data line 6 a can be almost completely flattened. In particular, FIG.
When the rubbing process is performed along the data line 6a as shown in FIG. 3, the region where the data line 6a and the like are formed is buried and flattened. Nation never occurs.

FIG. 16 is a sectional view taken along the line CC ′ in FIG. 13, showing pixel electrodes 9a adjacent to each other in the Y direction in FIG.
The cross-sectional structure between them is shown. In this area, liquid crystal disclination occurs due to the electric field between the adjacent pixel electrodes 9a, so that as shown in FIG.
In the divided area, the groove 10 'is not formed in the TFT array substrate 10 in the formation area of the scanning line 3a so that the cell gap of the liquid crystal layer 50 becomes narrow. As a result, even if an electric field is generated between the pixel electrodes 9a adjacent to each other, the electric field between the counter electrode 21 provided on the counter substrate 20 and the pixel electrode 9a is strengthened, so that the region where liquid crystal disclination occurs is minimized. It can be made smaller.
Further, since it is not necessary to reduce the disclination by narrowing the cell gap itself of the liquid crystal, various problems such as difficulty in developing the liquid crystal for the narrow cell gap and controlling the cell gap do not occur.

As described above, in the second embodiment of the present invention,
Since the groove 10 ′ is formed on the TFT array substrate 10 and the wiring and the element can be embedded therein almost completely or partially, compared with the case where the groove can be flattened only completely like the CMP process, It is possible to realize an electro-optical device including pixels with a higher aperture ratio. The groove 10 'is T
Similar effects can be obtained by forming an interlayer insulating film such as the base insulating film 12 and the interlayer insulating film 81 in addition to the FT array substrate 10. In addition, the groove 1 provided in the TFT array substrate 10
It is needless to say that 0'and a groove provided in the interlayer insulating film such as the base insulating film 12 or the interlayer insulating film 81 may be combined for flattening.

(Third Embodiment) FIG. 1 shows the configuration of a liquid crystal device which is a third embodiment of the electro-optical device according to the present invention.
This will be described with reference to FIGS. 17 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed, and FIG.
FIG. 18 is a cross-sectional view taken along the line AA ′ of FIG. 17. In FIG. 18, the scales of the layers and members are different so that the layers and members are recognizable in the drawing.

As shown in FIG. 17, in the third embodiment,
Auxiliary wiring 3 formed of the same film as the scanning line 3a and also serving as the capacitive electrode 3b
The formation of b'is very different from that of the first embodiment. Further, the auxiliary wiring 3b 'can extend from the image display area to the periphery thereof along the direction of the scanning line 3a and can be connected to the constant potential source in the peripheral area. As the constant potential source, a negative power source supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, etc.) for driving the liquid crystal device described later, a constant potential source such as a positive power source, a ground power source, A constant potential source or the like supplied to the counter electrode may be used, and the light-shielding conductive film 90 may be used.
It is preferably the same as the potential supplied to a. Thereby, the auxiliary wiring 3b 'can function as a part of the capacitance line 300 in FIG. Also, the data line 6a
It is also possible to electrically connect to the upper light-shielding conductive film 90a through the contact hole 95 below. At this time, the connection between the auxiliary wiring 3b ′ and the light-shielding conductive film 90a via the contact hole 95 may be performed for each pixel electrode 9a or for each of the plurality of pixel electrodes 9a. In this way, the auxiliary wiring 3b ′ and the light-shielding conductive film 9 are formed.
With 0a, the capacity line 300 having a redundant structure can be constructed. In addition, also in the first and second embodiments, when there is a margin in the light-shielding region, the capacitor electrode 3b is extended and the auxiliary wiring 3 is formed.
It goes without saying that b'may be constructed.

Further, in the third embodiment, as shown in FIG. 17, the relay film 80a 'shown by a diagonal line rising to the right is formed so as not to overlap the scanning line 3a in a plane. It is very different from the form. As shown in FIG. 18, by forming the interlayer insulating film 81 with a film thickness of 100 nm or less, a large storage capacitance can be formed on the auxiliary wiring 3b ′ including the capacitance electrode. That is, the storage capacity C2 shown in FIG. 4 can be increased. In this case, since the interlayer insulating film 81 for insulating between the scanning line 3a and the relay film 80a ′ is thinned, providing the relay film 80a ′ so as to overlap the scanning line 3a increases the parasitic capacitance, The scanning signal is delayed. In addition, the relay film 80a '
Since the TFT 30 malfunctions due to the influence of the potential applied to the relay region 80a ′, the relay film 80a ′ cannot be provided near the channel region 1a ′. However, the semiconductor layer 1a and the relay film 80
Since the interlayer insulating film 81 between a and a ′ can be formed very thin, the high-concentration drain region 1e of the semiconductor layer 1a can be formed.
And the relay film 80a 'are not penetrated through the semiconductor layer 1a at the time of opening the contact hole 8a for electrically connecting. Further, there is an advantage that the opening diameter of the contact hole 8a can be made extremely small. Further, the light-shielding conductive film 90a is formed of the interlayer insulating film 91 in order to shield the channel region 1a ′ and its adjacent region from the scanning line 3a.
Although it must be formed with a film thickness of 0 nm or more, the storage capacitor C1 shown in FIG. 4 can be formed between the auxiliary wiring 3b 'and the light-shielding conductive film 90a.

(Fourth Embodiment) FIG. 1 shows the configuration of a liquid crystal device which is a fourth embodiment of the electro-optical device according to the present invention.
9 and FIG. 20. 19 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, etc. are formed, and FIG.
It is sectional drawing which followed the AA 'of FIG. Note that in FIG. 20, the scales of the layers and members are made different so that the layers and members are recognizable in the drawing. The same members as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the fourth embodiment, as shown in FIG. 19, the scanning line 3a and the data line 6a are provided substantially at the center of the non-opening area. The semiconductor layer 1a is arranged below the data line 6a so as to cross the scanning line 3a. As shown in FIG. 20, the data line 6a and the high-concentration source region 1d of the semiconductor layer 1a.
Are electrically connected via the contact hole 5 below the data line 6a. In addition, the high-concentration drain region 1e of the semiconductor layer 1a and the relay film 80a are connected to the data line 6.
Electrical connection is made below a through the contact hole 8a. By arranging the semiconductor layer 1a below the light-shielding data line 6a in this way, the counter substrate 2
It has an effect of preventing the semiconductor layer 1a from being directly irradiated with the light incident from the 0 side. Further, by forming the semiconductor layer 1a and the contact holes 5 and 8a in line symmetry with respect to the center line of the non-opening region in the scanning line 3a direction and the non-opening region in the data line 6a direction, the step shape is formed. This is advantageous because it can be made bilaterally symmetric with respect to each other and there is no difference in light leakage depending on the rotation direction of the liquid crystal.

Under the semiconductor layer 1a, the base insulating film 12 is formed.
The base light-shielding film 11a is formed via the. The base light-shielding film 11a is formed in a matrix along the data line 6a direction and the scanning line 3a direction. The semiconductor layer 1a is disposed inside the base light-shielding film 11a, and has an effect of preventing the return light from the TFT array substrate 10 side from directly irradiating the semiconductor layer 1a.

The relay film 80a is made of a conductive film containing a polysilicon film or a refractory metal, and is composed of the semiconductor layer 1a and the pixel electrode 9.
It extends in a substantially T shape along the scanning line 3a and the data line 6a between the layers a, and functions as a buffer for electrically connecting the semiconductor layer 1a and the pixel electrode 9a. Specifically, the high-concentration drain region 1 of the semiconductor layer 1a
e is electrically connected to the conductive relay film 80a through the contact hole 8a, and the relay film 80a and the pixel electrode 9a are electrically connected through the contact hole 8b.
By adopting such a configuration, even when a deep contact hole is formed in the interlayer insulating film, the relay film 80a having a large etching selection ratio is provided, and the semiconductor layer 1a is penetrated when the contact hole is opened. You can avoid danger. The relay film 80a is similarly formed in the contact hole 5 for electrically connecting the data line 6a and the high concentration source region 1d of the semiconductor layer 1a.
The same film may be used for relaying.

In the fourth embodiment, the interlayer insulating film 91 is laminated on the relay film 80a, and the light-shielding conductive film 9 is formed thereon.
0a is formed. The light-shielding conductive film 90a is extended to the outside of the image display region in the scanning line 3a direction so as to cover the relay film 80a except for the contact hole 8b, and is supplied to the scanning line driving circuit, the data line driving circuit, and the like. The potential is fixed by being electrically connected to a constant potential source such as a negative power source or a positive power source, a ground power source, or a constant potential source supplied to the counter electrode. Therefore, the relay film 80a
Can be used as one capacitance electrode and the light-shielding conductive film 90a can be used as the other capacitance electrode to form the storage capacitance C1 shown in FIGS. At this time, it goes without saying that the interlayer insulating film 91 functions as a dielectric film of the storage capacitor C1.
Here, since the interlayer insulating film 91 is stacked only to form the storage capacitor C1, the relay film 80a and the light-shielding conductive film 9 are formed.
The storage capacitance C1 can be increased by thinning the interlayer insulating film 91 to a thickness that does not cause a leak with 0a. Further, in the fourth embodiment, by forming the interlayer insulating film 81 thick, the relay film 80a can be extended to above the TFT 30 and the scanning line 3a, so that the storage capacitance C1 can be efficiently increased. Further, in the fourth embodiment, the semiconductor layer 1a is extended and the capacitance electrode is not formed. As a result, it is not necessary to form the capacitance electrode and the capacitance line for forming the storage capacitance in the same film as the scanning line 3a. Therefore, as shown in FIG. 19, the scanning line 3a is shielded from the conductive film 90a.
Alternatively, it can be arranged at almost the center of the non-opening region defined by the base light-shielding film 11a. Further, since it is not necessary to reduce the resistance of the semiconductor layer 1a made of a polysilicon film, it is not necessary to implant an impurity in the capacitor electrode forming portion,
The number of processes can be reduced.

In the fourth embodiment, the channel region 1a 'of the TFT 30 is formed at the intersection of the scanning line 3a and the data line 6a, so that the channel region 1a' is formed at the center of the non-opening region in the data line 6a direction and the scanning line 3a direction. Can be provided. As a result, the incident light from the counter substrate 20 side and the TFT array substrate 1
Since the position where the return light from the 0 side is not irradiated with the light is the most, the leak current of the TFT 30 due to the light can be significantly reduced.

Furthermore, in the fourth embodiment, as shown in FIG. 19, the pattern width is narrowed in the order of the light-shielding conductive film 90a, the relay film 80a, and the base light-shielding film 11a near the channel region 1a '. It is devised so that the incident light is not directly applied to the base light-shielding film 11a. Further, by interposing the relay film 80a made of a polysilicon film between the light-shielding conductive film 90a and the semiconductor layer 1a, the reflected light on the surface of the base light-shielding film 11a and the return light from the TFT array substrate 10 side are absorbed. It is possible to have the effect of making it have an advantage in light resistance.

In the fourth embodiment, the data lines 6a,
The light-shielding conductive film 90a, the underlying light-shielding film 11a, etc.
Since the non-opening region can be formed on the T array substrate 10, the light shielding film need not be provided on the counter substrate 20. This allows
When the TFT array substrate 10 and the counter substrate 20 are mechanically bonded to each other, even if the alignment is deviated, the counter substrate 2
Since there is no light-shielding film on 0, the area through which light passes (opening area) does not change. As a result, a stable pixel aperture ratio can always be obtained, and device defects can be greatly reduced.

(Overall Configuration of Electro-Optical Device) The overall configuration of the liquid crystal device in each of the above-described embodiments will be described with reference to FIGS. 21 and 22. Note that FIG. 21 shows T
22 is a plan view of the FT array substrate 10 together with the constituent elements formed thereon as viewed from the counter substrate 20 side.
FIG. 22 is a sectional view taken along line HH ′ of FIG. 21.

In FIG. 21, a sealing material 52 is provided along the edge of the counter substrate 20 on the TFT array substrate 10 on which elements and wirings are formed. A light-shielding frame 53 for defining the periphery is provided. The frame 53 may be provided on the TFT array substrate 10 side as in the present embodiment, or may be provided on the counter substrate 20 side. In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connecting terminal 102 for supplying an image signal to the data line 6a at a predetermined timing are provided along one side of the TFT array substrate 10. A scanning line driving circuit 104 for supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to this one side. It goes without saying that the scanning line driving circuit 104 may be provided on only one side if the delay of the scanning signal supplied to the scanning line 3a does not matter. Further, the data line driving circuits 101 may be arranged on both sides along the side of the image display area. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for supplying a common signal are provided between the scanning line driving circuits 104 provided on both sides of the image display area. In addition, the counter substrate 2
At least one position of the corner portion of 0 is provided with a vertical conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20. That is, the counter electrode potential applied from the external circuit connection terminal 102 is
The counter electrode 2 provided on the counter substrate 20 via the wiring provided on the TFT array substrate 10 and the vertical conducting material 106.
1 is supplied. Then, as shown in FIG. 22, the counter substrate 20 is fixed to the TFT array substrate 10 by the sealing material 52. On the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit that supplies an image signal to a plurality of data lines 6a at a predetermined timing, a plurality of data lines. 6
Even if a precharge circuit for supplying a precharge signal of a predetermined voltage level to a is supplied respectively to the image signal a, an inspection circuit for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or shipping, good. As described above, in the liquid crystal device according to the present embodiment, the TF for controlling the pixel electrode 9a is used.
Since the peripheral circuits such as the data line driving circuit 101 and the scanning line driving circuit 102 can be formed on the same TFT array substrate 10 in the step of forming T30, a high-definition and high-density liquid crystal device can be realized. You can

Further, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate may be mounted on the TFT array substrate 10. You may make it electrically and mechanically connect through the anisotropic conductive film provided in the peripheral part. Further, the side of the counter substrate 20 on which the projection light enters and the TFT array substrate 10
On the side from which the emitted light is emitted, for example, TN mode,
VA (Vertically Aligned) mode, PDLC (Polymer D)
A polarizing film, a retardation film, a polarizing plate or the like may be arranged in a predetermined direction depending on an operation mode such as ispersed Liquid Crystal) mode and normally-white mode / normally-black mode.

Since the liquid crystal device in each of the embodiments described above is applied to a projector for color display, three liquid crystal devices are respectively used as light valves for R (red) G (green) B (blue). The light of each color separated through the dichroic mirror for RGB color separation enters the respective light valves as projection light. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, an RGB color filter is provided in a predetermined area facing the pixel electrode 9a together with its protective film,
It may be formed on the counter substrate 20. Alternatively, the pixel electrode 9a facing the RGB on the TFT array substrate 10
It is also possible to form a color filter layer below with a color resist or the like. With this configuration, the liquid crystal device according to each embodiment can be applied to a liquid crystal device for color display such as a direct-view type or a reflection type color liquid crystal television other than the projector. Further, microlenses may be formed on the counter substrate 20 so as to correspond to each pixel. By forming the microlens in this way, the efficiency of collecting incident light can be significantly improved, and a bright liquid crystal device can be realized. Furthermore, a dichroic filter that produces RGB colors may be formed by stacking a number of interference layers having different refractive indexes on the counter substrate 20 and utilizing light interference. This counter substrate with a dichroic filter can realize a liquid crystal device for brighter color display.

In the liquid crystal device in each of the embodiments described above, the incident light is made to enter from the counter substrate 20 side as in the conventional case, but the base light-shielding film 11a and the light-shielding conductive film 90a are provided in the TFT array. Since it is provided on the substrate 10, light may be incident from the TFT array substrate 10 side and emitted from the counter substrate 20 side. Also, TF
There is no need to separately arrange a polarizing plate coated with an AR (Anti Reflection) coating for preventing reflection on the back surface side of the T array substrate 10 or to attach an AR film,
The material cost can be reduced by that much, and the yield is not significantly reduced due to dust, scratches, etc. when the polarizing plate is attached, which is very advantageous. Further, since the light resistance is excellent, even if the light utilization efficiency is improved by using a bright light source or polarization conversion by the polarization beam splitter, image deterioration such as crosstalk due to light does not occur. Further, in the present embodiment, the conductive film 90a is formed to have a light-shielding property, but when another film having a light-shielding property is formed against the incidence of light from the counter substrate side, the conductive film 90a is shielded from light. May not form due to sex. Even if the conductive film 90a does not have a light shielding property, the storage capacitance can be increased according to the configuration of this embodiment.

Although the switching element provided in each pixel is described as a positive stagger type or coplanar type polysilicon TFT, it is an inverse stagger type TFT.
The respective embodiments are also effective for other types of TFTs such as and amorphous silicon TFTs.

The electro-optical device of the present invention is not limited to the above-described embodiments, but can be appropriately modified within the scope of the gist or concept of the invention which can be read from the claims and the entire specification. An electro-optical device with various modifications is also included in the technical scope of the present invention.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the first embodiment.

3 is a cross-sectional view taken along the line A-A 'of FIG.

FIG. 4 is a view showing the configuration 1 of the electro-optical device according to the embodiment of the invention.
It is an equivalent circuit diagram of a pixel.

FIG. 5 is a plan view showing a light-shielding conductive film and a relay film of FIG.

FIG. 6 is a plan view of the relay film and the capacitor electrode extracted from FIG.

FIG. 7 is a plan view showing a capacitance electrode and a semiconductor layer extracted from FIG. 2;

FIG. 8 is a plan view showing a semiconductor layer and a base light-shielding film extracted from FIG.

FIG. 9 is a plan view showing a light-shielding conductive film and a pixel electrode of FIG.

10 is a base light-shielding film, a light-shielding conductive film in FIG.
It is a top view which extracts and shows a relay film and a data line.

11 is a sectional view taken along the line BB ′ of FIG.
(2) is a sectional view of a conventional example.

FIG. 12 is a schematic diagram showing polarities of image signals supplied to a plurality of pixel electrodes in a matrix forming an image display area in the electro-optical device according to the second embodiment of the invention.

FIG. 13 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the second embodiment.

FIG. 14 is a cross-sectional view taken along the line A-A ′ in FIG.

FIG. 15 is a cross-sectional view taken along line B-B ′ of FIG.

16 is a cross-sectional view taken along the line C-C ′ of FIG.

FIG. 17 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the third embodiment.

18 is a cross-sectional view taken along the line A-A ′ of FIG.

FIG. 19 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the fourth embodiment.

20 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 21 is a plan view of the TFT array substrate in the liquid crystal device of each of the embodiments, together with the respective components formed thereon, as viewed from the counter substrate side.

FIG. 22 is a cross-sectional view taken along the line H-H ′ of FIG. 21.

[Explanation of symbols]

1a ... semiconductor layer 1a '... Channel region 1b ... Low concentration source region 1c ... low concentration drain region 1d ... High-concentration source region 1e ... high-concentration drain region 1f ... Capacitance electrode 2 ... Gate insulating film 3a ... scanning line 3b ... Capacitance electrode 4 ... Interlayer insulating film 5 ... Contact hole 6a ... Data line 7 ... Interlayer insulating film 8a ... Contact hole 8b ... Contact hole 9a ... Pixel electrode 10 ... TFT array substrate 11a ... Base light-shielding film 12 ... Base insulating film 16 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 30 ... TFT 50 ... Liquid crystal layer 70 ... Storage capacity 80a, 80a '... Relay film 81 ... Interlayer insulating film 90a ... Conductive film with light shielding property 91 ... Interlayer insulating film 95 ... Contact hole 101 ... Data line drive circuit 104 ... Scan line drive circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 G02F 1/1333 G02F 1/1335 G02F 1/1343 H01L 29/78

Claims (17)

(57) [Claims] 1. A scan line on a substrate, a data line intersecting with the scan line, a thin film transistor provided corresponding to the scan line and the data line, and a pixel electrode provided corresponding to the thin film transistor. The thin film transistor includes a semiconductor layer having a channel region, and a gate electrode arranged to face the channel region, wherein the channel region is located in the region of the data line, and A first capacitance electrode and a first capacitance electrode disposed in a region above the gate electrode and below the data line and in which the channel region and the scanning line extend, and the first capacitance electrode via an insulating film. An electro-optical device characterized in that a first storage capacitor is laminated with a two-capacitance electrode. 2. The electro-optical device according to claim 1, wherein the first storage capacitor is formed in a region along the data line from the channel region. 3. The electrical capacitor according to claim 1, wherein the second capacitive electrode of the first storage capacitor forms a relay film that electrically connects the drain region of the thin film transistor and the pixel electrode. Optical device. 4. The first storage capacitor is formed so as to overlap the respective regions of the semiconductor layer and the scanning line, leaving a connection region between the source region of the thin film transistor and the data line. Claim 1 to 3 characterized by the above-mentioned.
The electro-optical device according to claim 1. 5. A second storage capacitor is formed by the second capacitance electrode and a third capacitance electrode which is arranged to face the second capacitance electrode via an insulating film and is made of the same film as the gate electrode. The electro-optical device according to claim 1, wherein the electro-optical device is a device. 6. The third capacitance electrode is formed in parallel with the scanning line, leaving a connection region between the drain region of the thin film transistor and the second capacitance electrode. Electro-optical device. 7. The electro-optical device according to claim 5, wherein the third capacitance electrode is electrically connected to the first capacitance electrode. 8. The electro-optical device according to claim 7, wherein an electrical connection portion between the third capacitance electrode and the first capacitance electrode is located in a region below the data line. 9. The third capacitor electrode comprises a part of a first capacitor line extending along the scanning line, and the first capacitor electrode comprises a part of a second capacitor line extending along the scanning line. ,
9. The first capacitance line and the second capacitance line are extended to the periphery of an image display region where the pixel electrode is arranged and electrically connected to each other. The electro-optical device according to claim 1. 10. A third storage capacitor is formed by the third capacitance electrode and a fourth capacitance electrode which is arranged to face the third capacitance electrode via an insulating film and is made of the same film as the semiconductor layer. 9. The electro-optical device according to claim 5, which is characterized in that. 11. The electro-optical device according to claim 10, wherein the fourth capacitor electrode is formed to extend from a drain region of the thin film transistor. 12. The fourth capacitance electrode is formed in parallel with the scanning line.
1. The electro-optical device according to 1. 13. The capacity of the second storage capacity is the first storage capacity.
13. The electro-optical device according to claim 10, wherein the electro-optical device is smaller than each of the storage capacitor and the third storage capacitor. 14. A fourth capacitance electrode formed of the same film as the semiconductor layer, and a fifth capacitance electrode which is arranged to face the fourth capacitance electrode via an insulating film and shields the semiconductor layer.
A storage capacitor is formed, and the storage capacitor is formed.
The electro-optical device according to claim 3. 15. The electro-optical device according to claim 14, wherein the fifth capacitance electrode is electrically connected to the first capacitance electrode around the image display area. 16. A fifth storage capacitor is formed by the first capacitance electrode and a sixth capacitance electrode which is arranged to face the first capacitance electrode with an insulating film interposed therebetween and which constitutes the pixel electrode. The electro-optical device according to claim 1. 17. The electro-optical device according to claim 16, wherein the fifth storage capacitor is formed over substantially the entire circumference of one pixel.