JP3496661B2 - Reconfigurable device with programmable interconnect network suitable for data path - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reconfigurable device which is a logic device capable of implementing various programmable functions, and more particularly to a reconfigurable device having a programmable interconnection network suitable for a data path.

[0002]

2. Description of the Related Art In recent years, reconfigurable devices such as PLDs and FPGAs, which are logic devices capable of realizing various programmable functions, have been rapidly developed. By increasing the degree of integration and speed, it is expected to realize not only conventional emulation at the time of ASIC design and simple replacement of peripheral circuits, but also a reconfigurable computer whose hardware configuration can be changed according to the application. It
Such a reconfigurable device includes a two-dimensional array of functional cells in which various logic functions can be set programmable.
It consists of those functional cells and a programmable interconnection network that connects various circuits (for example, I / O circuits and memories) mounted on the device in a programmable manner. Various programmable interconnection networks having a hierarchical structure including wirings of various lengths have been devised in order to enable efficient connection between functional cells and various circuits. Figure 21
Shows a conventional example of a programmable interconnection network having a hierarchical structure. This shows one row of a two-dimensional array of functional cells 10 and a portion of the associated programmable interconnect network. Programmable interconnect network 20 includes short distance programmable interconnect channels 21 composed of short wires and long distance programmable interconnect channels 22 composed of long wires. Short range programmable interconnect channel 21 is programmable switch 58-1,58-2
Is divided into short-distance sectors 65-1, and long-distance programmable interconnect channel 22 is divided into long-distance sectors 65-2 by programmable switch 58-2. The programmable switch is a circuit that connects and disconnects wirings connected to both sides thereof in a programmable manner.
For example, programmable switch 58-2 is
Between adjacent wires that run on the same axis as 62-2, or wire 61
-Problemably connect between different kinds of wires running in parallel like -1 and 62-1. In the wiring structure divided into such sectors, there is a problem that a large delay occurs as compared with the inside of the sector because the programmable switch must pass through in signal transmission across a plurality of sectors. For this reason, if the size of the implemented macroblock does not match well with these sector structures, the delay becomes large. In many cases, a complex and large-scale process is performed as a whole while sequentially transmitting signals to neighboring macroblocks such as a data path. However, when such a circuit is implemented in a sector type wiring structure as shown in FIG. However, some macroblocks cross sectors and a large delay is generated there. Generally, when a large-scale circuit is implemented in a sector-type wiring structure, a large number of places unavoidably occur in a sector within a macroblock or between macroblocks, resulting in a problem that high performance cannot be obtained. It should be noted that FIG. 21 shows only an example to show the essence of the problem, and for example, the number of wirings, the sector size, the number of programmable interconnect channels, etc. specifically shown in the figure are not important. As a typical example having such a sector type wiring structure, there is, for example, US Patent 5469003. US Patent 5218240 also discloses another type of sector wiring structure. It has a structure in which the long-distance sector 65-2 and the short-distance sector 65-1 in FIG. 21 are the same, except that the functional cell 10 is a short-distance programmable interconnect channel 21 (in this patent a local bus Connection) and not the long-distance programmable interconnect channel 22 (referred to as an express bus in this patent). Long range programmable interconnect channel 22 is a short range programmable interconnect channel 21 and programmable switch 58-2.
The functional cell can be accessed via. This configuration allows long distance programmable interconnect channels 22
The load capacity is reduced and high-speed signal transmission becomes possible. However, in this wiring structure, the wiring network is completely divided into sectors, and does not have longer-distance wiring resources. Therefore, as shown in FIG. 21, the long-distance sector 65-2 does not bridge the break of the short-distance sector 65-1 to partially compensate the demerit of the sector division.

Next, the problem of the conventional example concerning the connection system between the programmable interconnection network and the functional cells will be described. FIG. 22
Is a conventional example of a connection method between a hierarchical programmable interconnection network (not limited to a sector type) and a functional cell (for example, AT & T Field-Programmable Gate Arrays Data Boo
k, April 1995). The programmable interconnect network consists of a horizontally programmable horizontal interconnect network 20 and a vertically programmable vertical interconnect network 30. The horizontal programmable interconnect network 20 includes at least a short range horizontal programmable interconnect channel 21 and a long range horizontal programmable interconnect channel 22, and the vertical programmable interconnect network 30 includes at least a short range vertical programmable interconnect channel 31 and a long range vertical programmable interconnect channel. Includes connection channel 32. At the intersection 59 of the horizontal programmable interconnection network 20 and the vertical programmable interconnection network 30, there is a cross programmable switch 55 capable of programmable connection / disconnection between intersecting wirings. The function cell 10 includes an input selection switch 11, a function block 13, and an output selection switch 15.
including. A function block 13 is probably selectable in function and produces from a plurality of inputs 12 at least one output 14 in response to said selected function. Input selection switch
11 selects a plurality of signals from the programmable interconnection network to generate the input 12 of the functional block 13, and the output selection switch 15 selectively outputs the output 14 of the functional block 13 to the programmable interconnection network. In this conventional example, the functional cell 10
The wiring of all the programmable interconnection networks associated with and the functional cells are directly connected. This seems to enable signal transmission at a seemingly faster speed than in the case of indirectly connecting through other wiring. However, in such a direct connection method, since all the functional cells within the range through which the wiring passes have a connection, the load capacity applied to the wiring becomes large. Therefore, particularly in the case of long-distance wiring, there arises a problem that the load capacity of those wirings becomes huge and signal transmission becomes slow. Further, if a large number of wiring resources are prepared to secure the routability, the input selection switch 11 for selecting a signal from those wirings and the output selection switch 15 for selecting an output to those wirings become very large. However, there will be a large penalty in terms of area and delay. In the example shown in FIG. 22, the intersection 59
Programmable switch 55
Although not provided, if they are provided at other intersections to increase routability, or if programmable switches are also provided between wirings running in parallel, this also increases the area and delay. . Conversely, if the number of wirings connected to a functional cell is reduced in order to reduce the load capacity applied to the wiring, there arises a problem that some wirings of the programmable interconnection network cannot be accessed from the functional cell. As described above, the direct connection method in which all two points that need to be connected are directly connected by a switch has a big problem. Note that, in FIG. 22, the input and output selection switches are collectively shown in the functional cell 10 for simplicity, but at least a part of these switches is brought out to the outside, for example, in the part 19 of FIG. Even if installed, the essence does not change. Further, FIG. 22 is merely an example for showing the essence of the problem, and for example, the wiring specifically shown in the drawing,
The number of switches, programmable interconnect channels, etc. is not important. Further, FIG. 22 shows an example in which the programmable interconnection network is located above and to the left of the functional cells and connected to the functional cells. AT & T Field-Programm
As shown in "Able Gate Arrays Data Book, April 1995", the essence does not change even if the programmable interconnection networks are located above, below, to the left and right of the functional cells and are connected to the functional cells.

In order to solve the above-mentioned problems related to sector division and problems related to the direct connection method, US Patent 5631578
Has devised a wiring structure as described below. (This is a modification of the previously mentioned US Patent 5218240.) As shown in FIG. 23, the first programmable interconnect has two types of programmable interconnect networks 20-1 and 20-2 that run in parallel with each other. Net 20-1 is the first local bus 23-1
1st Express Bus 24-1 and 1st Super Bus 25
-1, and the second programmable interconnection network 20-2 includes a second local bus 23-2, a second express bus 24-2 and a second super bus 25-2. The wires of the local bus are connected to each other by the first programmable switch 58-1 and the second programmable switch 58-2, and are connected to the functional cell 10. The wires of the express bus are coupled to each other by the first programmable switch and also to the local bus by the first programmable switch. The superbus is coupled to the local bus by a second programmable switch, but the second programmable switch does not split the superbus. Express buses and super buses are not directly connected to functional cells. The first programmable switch and the second programmable switch are arranged alternately, but the positions of both programmable switches are switched in the first programmable interconnection network 20-1 and the second programmable interconnection network 20-2. On behalf of. As a result, the first express bus 24-1 and the second express bus 24
-2 and because the position of the programmable switch that is the break of the wiring is different, there will be an express bus that does not pass through the break at any place. Moreover, since the express bus and the super bus do not have a connection with the functional cell, the load capacity is small and high-speed signal transmission is possible. These buses are accessible to the local buses connected to the functional cells via the programmable switches connected to them. However, this conventional example has only partially alleviated the above-mentioned problems of the sector type wiring structure and has not yet been sufficiently solved. This is because the local bus is still divided into sectors. In general, short-distance wiring is used more frequently than long-distance wiring, and problems due to sector division occur more frequently in short-distance wiring. This is particularly the case when a large number of macroblocks as described above are arranged and data is sequentially transferred to neighboring macroblocks for large-scale processing. Thus, the wiring structure shown in FIG. 23 is insufficient as a solution to the sector division problem. In addition, USPate
In nt5631578, wiring resources other than those shown in FIG. 23 are also given, but only the essential parts necessary for explaining the problem are shown here.

Further, in all the conventional examples described above, the same wiring structure is provided in the vertical direction and the horizontal direction. Such an isotropic wiring structure appears to be a seemingly preferable structure for the purpose of the reconfigurable device, which allows to implement as many circuits as possible. However, in a large-scale application circuit, a large part of the circuit is often occupied by a data path that sequentially processes multi-bit data. This is especially the case for reconfigurable computers, which are expected to have a large market in the future. In such a multi-bit data path, there is little demand for signal transmission in the data bit arrangement direction (carry propagation direction), and there is a great demand for signal transmission in the direction perpendicular to it. And when implementing this kind of circuit, the isotropic wiring structure is a great waste.

US Patent 5592106 uses another type of wiring structure to address the problems associated with sector division and the problems associated with direct connection schemes. FIG. 24 is an outline of the wiring structure. The horizontal programmable interconnection network 20 includes local feedback channels 26 and intermediate channels 27, which are short-distance wiring networks, and global channels 29 and half-length channels 28, which are long-distance wiring networks. The global channel 29 is composed of a wiring group having the same length as the entire width of the two-dimensional array of the functional cells 10, and the half length channel 28 is composed of a wiring group having a half length thereof. The wiring lengths of the intermediate channel 27 and the local feedback channel 26 are almost the same. The long distance input selection switch 11-2 selects one signal from the long distance wiring network (global channel and half length channel) and outputs it to one wiring of the intermediate channel 27. The short range input select switch 11-1 selects a signal from the short range wiring network (intermediate channel 27 and local feedback channel 26) to generate the input 12 of the functional block 13. Each wiring of the local feedback channel is connected to the output 14 of one functional block without a programmable switch, and the long distance wiring network is
It is selectively connected to the output 14 of the functional block via the output selection switch 15. The short distance input selection switch 11-1 and the long distance input selection switch 11-2 do not divide the wiring passing therethrough. In addition, adjacent wires running on the same axis are not connected by a programmable switch. The feature of this conventional example is that the wiring in the intermediate channel 27 and the wiring in the local feedback channel 26 are shifted by one functional cell from each other. Therefore, the other wiring is connected even at the break of a certain wiring, and the short-distance wiring network is not divided into sectors. In addition, the long-distance wiring network is not directly connected to the input of the function block 13,
Connected via 27. As a result, sufficient accessibility to the functional cell 10 can be realized even if each long-distance input selection switch 11-2 is connected only to a part of the long-distance wiring network. Therefore, the load capacity of the long-distance input selection switch applied to each wiring of the long-distance wiring network can be reduced. However, in this conventional example, the half length channel 28 still remains sectored. Also, the function cell 10
The output from to the long-distance wiring network is directly connected without passing through other channels. In the case of this method, in order to suppress the increase in load capacity due to the output of the functional cells, only a few functional cells can be connected to one wiring. For this reason, if the number of functional cells increases, the number of long-distance wiring lines will increase significantly. In general, the longer the wiring is, the less frequently it is used, and this is a great waste. On the contrary, if the number of long-distance wirings is reduced by this method, the output of a large number of functional cells is connected to one wiring, which causes a problem that load capacitance increases and delay increases. In this conventional example, an anisotropic wiring structure having different wiring structures in the horizontal direction and the vertical direction (not shown in FIG. 24) is adopted. However, it employs a method in which only the global channel is arranged in the vertical direction and the output from the functional cell is directly connected to it. This causes a problem of increasing the load of the wiring and lowering the signal transmission speed. Further, since the local feedback channel of this conventional example directly connects only the output of one functional cell to each wiring, a large number of wirings are required as compared with the system in which the wirings are shared by a plurality of functional cells. This not only increases the wiring area, but also causes a problem that the short-distance input selection switch 11-1 becomes large because signals are selected from a large number of wirings. It should be noted that FIG. 24 shows only the essential part of the US Patent 5592106 for the problem here, and does not show all the parts shown in the patent. In addition, the numbers of wirings and switches, wiring lengths, and the like shown in FIG. 24 are merely examples arbitrarily selected for explanation.

[0007]

As described above, the conventional programmable interconnection network has the following problems. The first problem is that it is difficult to obtain good performance when implementing a large-scale application circuit. The reason is that since the wiring is divided into sectors, the size of macroblocks is limited in order to obtain high performance, and also in signal transmission between macroblocks, it is generally unavoidable that the sector boundaries cross. This is because the delay is large because it exists in the. The second problem is that the area occupied by the switch is large. The reason is that, between the functional cells and the programmable interconnection network, in the programmable interconnection network, and the like, the portions that need to be coupled are directly connected by the switch. This increases the number of switches and occupies a large area. Further, a large number of switches add a great load capacitance to the wiring, which slows down signal transmission. The third problem is that there is a lot of waste when implementing multi-bit data. The reason is that the isotropic wiring structure includes more wiring resources than required in the direction of low demand. The fourth problem is that the longer the wiring, the greater the number of wirings and the more waste. The reason is that the output is directly coupled from the functional cell to the long distance wiring.
An object of the present invention is to provide a reconfigurable device having a high-speed programmable interconnection network, which has sufficient routability with a small number of switches and wirings and can efficiently implement a multi-bit data path, in particular.

[0008]

SUMMARY OF THE INVENTION In accordance with the present invention, both short and long distance programmable interconnect channels in the horizontal direction employ a shift structure in which the wiring is staggered by a fixed amount so that the programmable interconnect is not divided into sectors. Form a net. Also, the functional cells have direct connections only with short range horizontal programmable interconnect channels and no direct connections with long range horizontal programmable interconnect channels. Signal transmission between the functional cells and the long-distance horizontal programmable interconnect channels takes place both via input and output via the short-distance horizontal programmable interconnect channels and programmable switches. This reduces the load on the long-distance horizontal programmable interconnect channels and enables high-speed transmission.
Also in the vertical direction, there are short-range and long-range programmable interconnect channels, the long-range programmable interconnect channels being coupled to the short-range programmable interconnect channels via programmable switches.
The short-range vertical programmable interconnect channel has a coupling with the short-range horizontal programmable interconnect channel via a programmable switch to access the functional cell through this path. The wiring structure as described above enables the functional cells to access all the programmable interconnect channels with very few switches and also enables the routing between the programmable interconnect channels of all kinds. Here, the vertical direction corresponds to the bit arrangement direction of multi-bit data, and the number of lines of the programmable interconnection network running in that direction is smaller than that in the horizontal direction. This reduces wasted wiring when implementing a multi-bit data path. further,
The number of long-distance programmable interconnect channel wirings, both vertical and horizontal, is equal to or less than the number of short-distance programmable interconnect channel wirings, thereby reducing wasteful long-distance wiring. This is achieved by accessing the long-distance programmable interconnect channel through the short-distance programmable interconnect channel as described above, while ensuring sufficient accessibility between the functional cell and the long-distance programmable interconnect channel. Achieved without significant load on the distance programmable interconnect channels.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of a programmable interconnection network of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an outline of a reconfigurable device. The reconfigurable device 100 includes a functional cell 10 arranged in a two-dimensional array, a horizontally programmable horizontal interconnection path (HPIW) 20 laid along with each row of the two-dimensional functional cell array, and the two-dimensional array. It consists of vertically running vertical programmable interconnects (VPIWs) 30 associated with each column of the functional cell array. The function cell 10 is a logic circuit that can programmatically set various logic functions and generates an output signal according to the set logic function from an input signal. A programmable interconnect network consisting of HPIWs 20 arranged in each row and VPIWs 30 arranged in each column is used for the functional cell 10 and other circuits arranged on the device (not shown in FIG. 1, for example I / O circuit, RAM, etc.) are programmable connections between inputs and outputs. Such a reconfigurable device has a tile 40 composed of one functional cell and its associated part of the programmable interconnection network as a structural unit, and is constructed by laying the tiles in a two-dimensional matrix. It can also be seen (a portion of the tiles tiled in FIG. 1 is illustrated by a dotted square). It should be noted that FIG. 1 shows only the outline of the main components related to the present invention among the components of the reconfigurable device. The connections between the programmable interconnect network and the functional cells and between the HPIW and VPIW are not shown in FIG. 1, which will be described in detail later.

Next, a first embodiment of the HPIW of the present invention will be described. FIG. 2 shows one of the two-dimensional arrays of FIG.
The functional cell 10 for a row and the HPIW 20 attached thereto are shown in more detail. (For clarity, VPIW, HP
The connections between the IW and the functional cells and within the HPIW are not shown. The HPIW 20 includes at least a short-range horizontal programmable interconnect channel 21 and a long-range horizontal programmable interconnect channel 22, each horizontal programmable interconnect channel 21 and 22 consisting of one or more lanes. 50 programmable switches in each lane
It consists of a series of interconnect wiring segments coupled in series through. In FIG. 2, 40-1, 40-2, and 40-3 are examples of the above-mentioned tiles, and the entire circuit of FIG. 2 can be regarded as such that the tiles are linearly laminated in the horizontal direction ( Only three tiles 40-1, 40-2 and 40-3 are shown in FIG. 2 as an example.) The interconnect wiring segment has a length that is substantially an integral multiple of the tile width. After that,
Horizontal programmable interconnect channels are abbreviated to HPIC and interconnect wiring segments are abbreviated to ILS.

For example, 21-1 in FIG. 2 is the first lane in the short-range HPIC 21, which is an ILS (for example, 61-1) having a length of 3 tiles.
Are connected in series via. The short-range HPIC21 shown in Fig. 2 consists of a total of three lanes with a similar structure, and the ILS of the second lane (eg 61-2) is the ILS of the closest lane (61-). It is arranged by shifting one tile width from 1) to the right, and the ILS of the third lane (eg 61
-3) is shifted from the ILS (61-2) in the second lane closest to it to the right by one tile width. In addition, in FIG.
22-1 is the first lane of the long haul HPIC22, which is 18
The ILS (for example, 62-1) having the length corresponding to the tile width is connected in series via the programmable switch 50. The long-range HPIC22 shown in Fig. 2 consists of a total of three lanes with a similar structure.
(Eg 62-2) is the ILS in the first lane closest to it
It is placed 6 tiles to the right from (62-1), and the ILS in the third lane (eg 62-3) is 6 to the right from the ILS (62-2) in the second lane closest to it. The tiles are shifted by the width of the tiles. Note that it was specified as an example in the above description.
ILS 61-1, 61-2, 61-3, 62-1, 62-2, 62-3 are shown in bold in Figure 2 for clarity.

As mentioned above, in a programmable interconnect channel consisting of multiple identically configured lanes, IL
The structure in which S is sequentially shifted along with the lane by a fixed tile width in a certain direction is called a shift structure, and when the shift amount is a P tile width, it is called a P tile width shift structure. Also, short range HPIC and long range HP
ILS of IC is abbreviated as short-range HPILS and long-range HPILS, respectively. ILS length or segment length is the ILS
It is represented by the number of tiles through which is passed.

The programmable switch 50 will be described below. The programmable switch is a switching circuit that can programmatically set the connection state between both terminals. FIG. 3 shows a first example of the programmable switch 50. It consists of a 1-bit memory cell 1 and an NMOS transistor 2 whose gate terminal is connected to the data output terminal Q of the memory cell 1. Each source / drain terminal of the NMOS transistor 2 is connected to the bidirectional terminal of the programmable switch 50. These are 51-1 and 51-2. The retention value of memory cell 1 is 1 (high logic level) or 0 (low logic level)
Depending on whether the two-way terminals of programmable switch 50
The state between 51-1 and 51-2 is either connected or disconnected.
The programmable switch of this example has a feature that it requires a small area. However, there is a disadvantage that the high signal cannot be transmitted completely.

FIG. 4 is a second example of the programmable switch 50. It consists of a 1-bit memory cell 1 and a transmission gate 4, and the data output Q of the memory cell 1 is connected to the gate terminal of the NMOS transistor 2 constituting the transmission gate 4, and the inverted data output Qb of the memory cell 1 is connected to the transmission gate 4. Compose the PMOS
They are connected to the gate terminals of transistor 3, respectively. The transmission gate 4 is connected to one source / drain terminal of the NMOS transistor 2 and the PMOS transistor 2.
It is connected to that of 3 to form one bidirectional terminal, and the other source / drain terminal of the NMOS transistor 2 and that of PMOS transistor 3 are connected to form the other bidirectional terminal. Used as bidirectional terminals 51-1 and 51-2 of programmable switch 50. Depending on whether the holding value of the memory cell 1 is 1 or 0, the bidirectional terminals 51-1 and 51-2 of the programmable switch 50 are either connected or not connected. The programmable switch of this example is slightly larger than that of the first example, but has an advantage that both high and low signals can be completely transmitted.

FIG. 5 shows a third example of the programmable switch 50. This is the first 1-bit memory cell 1-1 and the first tri-state buffer 5-1 whose control terminal is connected to its data output terminal Q, and the second 1-bit memory cell 1-2 and its data. The second tri-state buffer 5-2 has a control terminal connected to the output terminal Q. The output terminal of the first tri-state buffer 5-1 is connected to the input terminal of the second tri-state buffer 5-2 and the first bidirectional terminal 51-1 of the programmable switch 50 is connected.
Therefore, the output terminal of the second tri-state buffer 5-2 is connected to the input terminal of the first tri-state buffer 5-1 and becomes the second bidirectional terminal 51-2 of the programmable switch 50. When the holding values of memory cells 1-1 and 1-2 are 1,0 respectively, the signal is transmitted from bidirectional terminal 51-2 to 51-1. When the holding values are 0 and 1, respectively, bidirectional terminal 51- From 1
When a signal is transmitted to 51-2 and both hold values are 0, both bidirectional terminals are disconnected. Although the programmable switch of this example requires a large area, the above-mentioned 2
The programmable switch in the example is a passive device that does not have a buffer (or signal reproduction) function, whereas this example is characterized in that it is an active device having a buffer function. For this reason, it is suitable for connecting between wirings having a large load.

In addition, examples of the programmable switch 50 include a fuse and an antifuse, which allow the user to set the connection state only once.

FIG. 6A is a more detailed view of the portion 70 of FIG. Each tile (for example, 40-1 to 40-
9) includes one functional cell 10, and three short-range HPILS and three long-range HPILS are passed through each. Within the tile, each short-range HPILS is directly connected to a functional cell, and one short-range HPILS and one long-range HPILS are coupled via an HPIC-to-HPIC programmable switch 50-3 (this coupling between HPICs). Called). The programmable switch 50-1 in the short range HPIC is always included in each tile.
Programmable switch 50-2 in a long-range HPIC is, for example, 40
Tiles that contain one, such as -1,40-7, and 40-2 to 40-6
There are tiles that do not include it.

FIG. 7 is a block diagram of the functional cell 10. The functional cell 10 includes an input / output wiring 16 directly connected to the short-range HPIC, an input selection switch 11-i for selecting one signal from the input / output wiring 16 and generating an input 12-i of the functional block 13, and ( i = 1,2, ...), a function block 13 that generates an output 14 from an input 12-i (i = 1,2, ...) according to a preset function, and an output 14 of the function block 13 is input / output wiring And an output selection switch 15 for selectively outputting to 16. Here, the number of input / output wirings, the number of input selection switches and output selection switches, the way of connecting the input / output wirings to the input selection switch and the output selection switch, and the number of inputs and outputs of the functional block shown in FIG. This is only an example and the present invention is not limited to this. However, the number of inputs of each input selection switch and the number of outputs of the output selection switch are plural. Input selection by the input selection switch, output selection by the output selection switch, and selection of the function of the functional block are all programmable.

As shown in FIG. 6A, in the programmable interconnection network of the present invention, a plurality of functional cells are generally connected to each short distance HPILS, but more specifically, a plurality of output selection switches. Are connected. This is different from the wiring connected to the output of one functional cell only like the local feedback channel 24 in FIG. 24 of the conventional example, and outputs an output signal by selecting from a plurality of functional cells to one wiring. Means that you can. As a result, in the short-range HPIC of the present invention, the number of wiring lines can be reduced as compared with the conventional local feedback channel.

Each functional cell is
It is directly connected to the left and right closest and next closest (next closest to) functional cells without a programmable switch.
For example, the functional cell of tile 40-3 can directly communicate with the functional cells of both sides (tiles 40-2, 40-4) through ILS61-2, and the functional cell of tile 40-3 on the right side (tile 40-4) and through it. Further, it can directly communicate with the function cell on the right side (tile 40-5), and directly communicate with the function cell on the left side (tile 40-2) and further left side (tile 40-1) via the ILS61-1. it can. Each short-distance HPILS is connected to the functional cell in all tiles through which it passes, but the short segment length allows a small load capacity and high-speed signal transmission. For example, in the case of FIG. 6A, each short-range HPILS is connected to only three functional cells. Further, by connecting a plurality of short-range HPILS via the programmable switch 50-1 in the short-range HPIC, it is possible to transmit a signal over a length of one segment. In the signal transmission between functional cells using short-range HPIC, the signal transmission through only one short-range HPILS without a programmable switch has the minimum delay. This is simply called short distance shortest connection. The short-range HPILS directly connected to a certain functional cell is the short-range HPILS of that functional cell, and conversely, the short-range HPILS directly connected to a certain short-range HPILS is its short-range HILS.
It is called the recently functional cell of PILS. In the example of FIG. 6 (A), each functional cell has three short-distance short distance HPILS, through which short distance shortest connection can be made with the functional cells up to two left and right. By the way, generally, in short-distance wiring, the wiring resistance is small and can be neglected approximately. At this time, the wiring delay is determined only by the load capacitance connected to it, and does not depend on the signal transmission distance. That is, short-distance wiring can be considered to have approximately the same delay anywhere in the wiring. Therefore, it can be said that the delay is the same everywhere in the short range HPILS recently.

In an embodiment of the present invention, all functional cells are routed through the three closest short-range HPILS to which they are connected, respectively, from that functional cell to the next proximity to the right, to the next proximity to the left, to the left and right. The shortest connection is possible to the closest functional cell. In this way, if the functional cells are allotted the same wiring resources and have the same shortest connection range through them, the wiring structure is said to be uniform. The uniformity of the short range HPIC in the embodiment of the present invention is derived from the one-tile shift structure described above. This shift structure does not divide the programmable interconnect channel into sectors, unlike conventional sector wiring structures. That is, the programmable switches in all lanes included in the programmable interconnect channel are not in the same position. Where there is a programmable switch joint in one lane, there is no joint in another lane and the wiring is continuous. As a result, even if the circuit is large, it can be realized with high performance as long as it is configured to transmit signals within the shortest connectable range. Further, since the shift structure is uniform, there are no restrictions on the size and arrangement of macroblocks. This is particularly suitable for implementing a data path that performs large-scale processing while sequentially transferring data to neighboring functional cells.

By the way, generally, the closer the wiring is, the more frequently it is used, and in order to obtain high performance, it is necessary to reduce the far wiring as much as possible and use the short wiring. The shift structure is characterized in that it has a large number of short-range HPILS at short distances as viewed from each functional cell, which is also convenient. In fact, focusing on each tile in FIG. 6 (A), from each tile, two tiles are adjoined on each side, and two tiles are adjoined on both sides, one for each short distance HPILS.
You can see that is extended. For example, using tile 40-3 as an example, tile 40-4 on the right has two nearest short distances.
HPILS 61-2, 61-3 is also connected to the tile 40-2 on the left with two recent short distance HPILS 61-1, 61-2. And the tile 40-5 on the right next to it has one recent short distance HPILS61-3.
However, there is also a recent short-range HPIL in tile 40-1 on the left next to it.
S 61-1 is connected.

As mentioned above, the short range HPIC has all three ILSs of the three lanes directly connected to the functional cells in each tile, while the long range HPIC has one of three lanes. Only the ILSs of the above are combined with one short-range HPILS via the inter-HPIC programmable switch in each tile. However, recently, by using short range HPILS, each functional cell can be connected to all lanes of long range HPIC with the same delay. For example, taking tile 40-3 in FIG. 6A as an example, all short distance HPILS 61-1, 61-2, 61-3 passing through that tile are directly connected to the functional cell, while the other Long-distance HPILS6 passing through that tile
Only 62-1 out of 2-1, 62-2, 62-3 is short range HPILS 61-2
HPICs are connected to each other, and the functional cell is connected to one long-distance HPILS62-1. Therefore, the remaining long-distance HPILS 62-2 and 62-3 have no connection to the functional cells in the same tile. However, the tile
The 40-3 functional cells are the latest short-range HPILS 61-1 and 61
-3 long-distance HPILS with tiles 40-2 and 40-4 next to each other
Since the HPICs are connected to 62-3 and 62-2, it is possible to connect to both long-range HPILS via these. Thus, the functional cells of tile 40-3 have recently become short-range HPILS61-1, 61-2, 61-
3 and all HPILS can be connected to all lanes of a long haul HPIC via one HPIC programmable switch connected to each HPILS. Moreover, the delay to each long-distance lane at this time is all the same. This is because, as mentioned above, the delays on short haul HPILS are virtually the same everywhere nowadays, regardless of whether the connection path to each long haul lane through it is within its own tile or through the next tile. This is because the delay will be the same. Thus, it is the shortest distance between a functional cell and a long-range HPILS that a functional cell can connect to a long-range HPILS via only the short-range HPILS of that functional cell and one inter-HPIC programmable switch connected to it. It is called connection and it is a long distance that can be connected as short as possible from the functional cell.
The HPILS is called the latest long-distance HPILS of the function cell, and the function cell that can be connected as shortest as seen from the long-distance HPILS on the contrary is called the long-distance HPILS recent function cell. In addition, to enable two different functional cells to connect to the same long-distance HPILS for the shortest time so that signals can be transmitted between both functional cells is called shortest connection between functional cells in long-distance HPIC, or simply long-distance shortest connection. Call.

As described above, each functional cell is a long-distance HPIC.
Recent long-distance HPIL with equal delay connection to all lanes
Have S These recent long-distance HPILSs consist of wires extending to the right from each functional cell, wires extending to the left, and wires extending to the left and right to a medium length.
For example, taking the tile 40-3 of FIG. 6A as an example, the long-distance HPILS62-3 has recently been extended to the right,
It continues from 2 tiles to +15 tiles. here,
"-I tile" represents the i-th tile to the left from a certain tile (or a functional cell in it), and is a "+ j tile"
Represents the jth tile on the right. Recently long distance HPIL
S62-1 is a wiring that extends long to the left, as seen from tile 40-3 +
It continues from 3 tiles to -14 tiles. Recently long distance
HPILS62-2 extends to the left and right to a medium length and runs from -8 tiles to +9 tiles. The functional cells of tile 40-3 can be connected to these three recent long haul HPILS with equal delay. By the way, as shown in FIG. 6 (A), each long-distance HPIL
S has HPIC coupling only every three tiles. For example, for long haul HPILS62-3, tiles 40-8 and 40-9 are HP
There is IC coupling, but the tiles on both sides of them have no HPIC coupling. But long range HPILS 62-3 has tiles 40-8
And 40-9 HPIC coupling and short-range HP connected to it
Through ILS 61-4 and 61-5, tiles 40-8 and
The shortest connection can be made to the functional cells of the tiles on both sides of 40-9. That is, all the functional cells in the range 41 of FIG. 6 (A) are the recent functional cells of the long-distance HPILS62-3, and therefore all of these functional cells have this long-distance HPILS62-3.
The shortest long-distance connection can be made from other functional cells that can be connected to the shortest distance to, for example, the functional cell of tile 40-3. As can be seen from the above example, each long-distance HPILS has HPIC only every three tiles.
By using the short-range HPILS that is connected to each HPIC even though it has no inter-coupling, long-distance shortest connection is possible between functional cells that are continuously arranged without a gap.
Further, in the embodiment of the present invention, the programmable switch 50 in the long-distance HPIC is used unless it is limited to the long-distance shortest connection.
By connecting multiple long-distance HPILS via -2, even longer-distance signal transmission is possible. The ILS 61-1, 61-2, 61-3, 61-4, 61-5, specified as an example in the above description,
62-1, 62-2, 62-3 are shown in Figure 6 for clarity.
It is indicated by a thick line in (A).

In the embodiment of the present invention, the range in which long distance and shortest connection from each functional cell is not necessarily the same. For example, the tiles 40-1 to 40-6 have the same long-distance HPILS of the same 62-1, 62-2, 62-3, so the long-distance and short-distance connection of the functional cells of those tiles is the absolute maximum. The position will be the same. This means that the relative long-distance shortest connection range viewed from the tiles 40-1 to 40-6 having different positions is different for each tile. For example tile 40-3
The relative long-distance shortest connection range seen from is -13 tiles to +15 tiles, but the relative long-distance shortest connection range seen from the tile 40-4 on the right is -14 tiles to +1 tile.
There are 4 tiles, both are different. Also, for example, tile 40
The long haul HPILS of the -7 functional cells is also 62-1, 62-2, 62-3, of which the long haul HPILS 62-1 does not pass through tile 40-7. Thus, long-distance HPILS may not pass through their tiles these days. As described above, the long-distance wiring structure does not necessarily look equivalent to each functional cell. However, even if there are some differences in long distance and shortest connection range, there are always three types of recent long distance HPILS for all functional cells: long distance HPILS extended to the right and long distance extended to the left. HPILS, and long-distance HPILS with medium stretch to the left and right are assigned. The difference in the long-distance shortest connection range between the functional cells is relatively small as compared with the size of the long-distance shortest connection range, which is practically no problem. In this way, when the wiring structure is not completely equivalent from the viewpoint of each functional cell but is roughly the same,
This is called a quasi-uniform wiring structure. Short range HPIC
In order to have perfect uniformity as shown in the figure, it is necessary to have a 1-tile shift structure.
In that case, N lanes are required. Therefore, long distance HP
When ICs are made uniform, a large number of ICs (eg, Figure 6
In the example of (A), 18 lanes will be required.
However, in general, the demand for long-distance wiring is smaller than that for short-distance wiring, and therefore a large waste occurs in a uniform wiring structure in which the number of lanes increases as the wiring segment length increases.
Therefore, in the present embodiment, the long-distance HPIC has a P-tile shift structure (1 <P. P = 6 in the example of FIG. 6A) to reduce the number of lanes, and I did the same. At this time, the long-distance HPIC loses complete uniformity, but since the quasi-uniformity is maintained as described above, there is almost no problem in implementing the application circuit.
In this way, the disadvantage of losing perfect uniformity is slight, while the long-distance HPIC obtained in exchange for it.
The area saving benefit from the reduction of wiring resources is extremely large.

In addition, the long distance HP of this P tile shift structure
The closer the IC is to each functional cell, the more recent long distances
There is also a characteristic that HPILS exists, and this characteristic also fits the general tendency that the short distance wiring is more frequently used. This will be exemplified below. Now, the section from one programmable switch in the long distance HPIC to the next programmable switch (not necessarily in the same lane) is called a unit section of the long distance HPIC. For example, in FIG.
(A) has five unit sections 63-1, 63-2, 63-3, 63-4, 63-5
It is shown. Here recently long distance HPILS 62-1, 62-2,
Focusing on tiles 40-1 to 40-6 that share 62-3, three unit sections 63-3 including these tiles have three tiles, and two adjacent unit sections 63-2 and 63-4 each have two tiles. It can be seen that one long, long-distance HPILS has recently been extended to each of the book and the next adjacent unit sections 63-1 and 63-5. Thus, the closer to each function cell, the longer the distance HPILS
The feature is that the number of Some tiles, such as tile 40-7, are on the boundary of a unit section and have a longest distance HPILS that does not pass through the unit section to which it belongs. In this case, the unit section where the three most recent long-distance HPILS pass is next to the unit section to which it belongs. For example, the tile 40-7 belongs to the unit section 63-4, but the unit section through which the three latest long distance HPILS pass is the adjacent 63-3. However, even in such cases, there is still a tendency that the number of long-distance HPILS becomes larger recently as it is closer to the tile.

Next, the signal transmission delay of the long distance and shortest connection will be described. In the long-distance shortest connection in the embodiment of the present invention, both the function cells on the signal output side and the signal input side have recently been connected to the short-distance HPILS and one connected to it.
Recently long distance HPIL via HPIC programmable switch
Since it is connected to S, the function cell is long-distance HPIL as before.
At first glance, the signal transmission delay seems to be larger than that of the method of directly connecting to S (for example, FIG. 22). However, in the conventional method, in order to allow a functional cell to access a long-distance HPILS in all tiles through which the long-distance HPILS pass, it is necessary to connect the functional cell and the long-distance HPILS in all the tiles. I won't. For this reason, each long distance
Due to the large number of connections in HPILS, a very large load capacity is added, which slows down signal transmission. On the other hand, in the embodiment of the present invention, as described above, each long-distance HPILS only has HPIC-to-HPIC coupling for every three tiles. OK,
High-speed signal transmission can be realized. Moreover, it is substantially long distance
It also maintains high connectivity, with all tiles that HPILS traverses being able to connect to functional cells. (Since the long-distance HPILS is connected to the functional cell via the short-distance HPILS, strictly speaking, there is a gap between the transit range of the long-distance HPILS and the long-distance shortest connection range between the functional cells using the long-distance HPILS. However, this is a deviation of at most one tile, and it does not matter practically.) Now, the long distance HP of the conventional method
The delay of the ILS is X, the delay of the long range HPILS of the present invention is x, and the delay of the short range HPILS of the present invention is y. Since the difference between the load capacity applied to the conventional long-distance HPILS and that in the present invention increases in proportion to the wiring length, Xx increases with the wiring length. This means that in long-distance HPILS, which is long enough, the long-distance shortest connection delay 2y + x of the present invention is the delay of the conventional method.
It means smaller than X. That is, the short distance HPIL of the present invention enables short distance HPIL on both the signal output side and the input side.
The decrease in delay x of long-haul HPILS due to lighter load is greater than the increase in delay 2y due to passing through S. (Note that the delay of the programmable switch between HPIC passing on the signal output side is x for driving the long distance HPILS, and the delay of the programmable switch between HPIC passing on the signal input side is for driving the short distance HPILS to y. In addition, in the conventional method, since the input and output of the functional block must be selected from both the short distance and long distance HPIC wiring resources, the input selection switch and the output selection switch are enlarged. On the other hand, in the embodiment of the present invention, since the functional cell is connected only to the short-range HPIC, the input selection switch and the output selection switch, which are significantly smaller than those in the conventional system, are sufficient. The downsizing of the input selection switch and the output selection switch as described above leads not only to reduction in circuit area but also reduction in delay.

By the way, the long-distance signal transmission in the embodiment of the present invention becomes faster than the conventional example because the long-distance HPIL is transmitted.
This is the case when S is sufficiently longer than short-range HPILS. Traditional
In the method that prepares many kinds of HPICs with relatively small difference in wiring length (for example, the ratio of length is at most about 2: 1) as seen in FPGA, the input selection switch and output selection switch are also large scale. In addition, since the number of programmable switches for connecting between wires is also large, the transmission speed does not increase as expected. And, in comparison, the area cost is very large. From this, it can be said that it is better to use a small number (about two types) of HPICs with a large difference in wiring length.

As described above, the delay of the long distance shortest connection in the embodiment of the present invention is 2y + x. Generally, long distance HP
The delay x of ILS is larger than the delay y of short-range HPILS, that is, the relation of y <x is established. From this, 3y <2y + x
That is, the longest shortest connection delay is three short distance HPI
It can be said that it is larger than the delay when LS is connected in series. Therefore, the segment length of a long-haul HPILS is shorter than that of a short-haul HPILS because the long-haul shortest connection is faster than the long-haul transmission by connecting multiple short-haul HPILS.
Must be at least four times S.

The short distance and long distance HPICs each have three lanes, and the short distance HPILS has a segment length of 3 and the long distance HPILS has a segment length of 18. The embodiments of the present invention have been described above. Is not limited to this. Generally, short-range HPIC is short-range HPIL with segment length M.
It includes M lanes in which S is connected in series via programmable switches, and they are arranged in a 1-tile shift structure. The functional cells of each tile are directly connected to the M short-range HPILS through that tile. Also, generally long-range HPIC
Contains M lanes in which long-distance HPILS with a segment length N are connected in series via programmable switches, and they are arranged in a P tile shift structure. Where the natural numbers M, N,
P satisfies the relation N = P · M, 4 ≤ P. Each short range HPILS
Long distance through one HPIC programmable switch
Combined with HPILS, any consecutive M tiles have different lanes of long-range HPIC and inter-HPIC connections. At this time, the functional cells can be connected to all the wiring resources of the HPIW with very few programmable switches and compact input selection switches and output selection switches, and high-speed signal transmission can be realized. The short-range HPIC uniformity and the long-range HPIC quasi-uniformity make it possible to implement large datapaths with few wiring seams. In addition, by accessing the long-distance HPIC only via the short-distance HPIC for both input and output, the long-distance HPIC that is rarely used
The number of IC lanes is suppressed and the load capacity is significantly reduced.

By the way, in FIG. 6A, as can be seen by comparing the tiles 40-1, 40-2, and 40-3, for example, the arrangement of the connection points between the functional cells and the short-range HPICs and the programmable between the HPICs are arranged. The layout of connection points between switches and short-range and long-range HPILS and the layout of programmable switches in short-range HPIC are different for each tile. Such apparent complexity can be eliminated by rewriting as follows. FIG. 6B is a rewriting of the range 71 in FIG. 6A. This is for each short range and long range HPIC,
Lowest HP while going from any tile to its right
ILS is moved to the top, and this movement is called rotation, and such notation is called rotation notation. Using this notation, all tiles have the same placement of the connection points and programmable switches described above. The rotation notation is useful not only when drawing a drawing but also when designing a circuit as an LSI, because it is clear that it is sufficient to arrange the same hard macros in an LSI design. However, even with rotation notation
In the HPIC part, exception patterns occur at regular intervals. For example, tiles 40-10, 40-11, 40-1 include long range HPIC programmable switch 50-2, but not other tiles.
Such irregularities are due to the quasi-uniformity of the long range HPIC of the present invention. In order to clearly show the wiring route in the rotation notation, as an example in FIG. 6B, short distance HPILS 61-1 and long distance HPILS 62 are shown.
-1 is indicated by a bold line. Further, FIG. 6B also shows a fixed logical value supply switch 80 which has not been shown so far. The fixed logic value supply switch is a circuit that can programmably set a fixed logic value (low or high logic signal) or put the output in a high impedance state. In a reconfigurable device, some programmable interconnect wiring may be unused depending on the circuit implemented therein. However, in general, in a logic circuit, a wiring having an indeterminate logic value to which an output signal is not supplied from anywhere is not allowed. Each is connected to a fixed logic value supply switch. The fixed logic value supply switch is set to output a fixed logic value when the programmable interconnect wire connected to its output terminal is unused, and when the wire is used, the output goes to a high impedance state. Is set.

FIG. 8 shows a first example of the fixed logical value supply switch 80. The data output Q of the 1-bit memory cell 1 is connected to the gate of the NMOS transistor 2, the source of the NMOS transistor 2 is connected to the ground 6, and the drain of the NMOS transistor 2 is connected to the output terminal 81 of the fixed logic value supply switch 80. It is a thing. Output of 1-bit memory cell 1
When Q is a high logic value, a low logic value is output to the output terminal 81 of the fixed logic value supply switch 80, and when the output Q of the 1-bit memory cell 1 is a low logic value, the output of the fixed logic value supply switch 80 The terminal 81 is in a high impedance state.
That is, the first example is a fixed logical value supply switch that supplies a low logical value as a fixed logical value.

FIG. 9 shows a second example of the fixed logical value supply switch 80. This is because the data output Q of the 1-bit memory cell 1 is applied to the gate of the PMOS transistor 3 and the power supply voltage Vcc is applied.
The source of the PMOS transistor 3 and the drain of the PMOS transistor 3 are connected to the output terminal 81 of the fixed logic value supply switch 80, respectively. When the output Q of the 1-bit memory cell 1 has a low logical value, a high logical value is output to the output terminal 81 of the fixed logical value supply switch 80, and when the output Q of the 1-bit memory cell 1 has a high logical value, it is fixed. The output terminal 81 of the logic value supply switch 80 is in a high impedance state. That is, the second example is a fixed logic value supply switch that supplies a high logic value as a fixed logic value.

By the way, in FIG. 6B, the tile 40
-10, 40-11, 40-1 all include programmable switch 50-2 in long range HPIC, but the wiring to which they are connected is the lowest in tile 40-10, the middle in tile 40-11,
The tile 40-1 is different at each tile, such as the topmost tile. If there are many different tiles like this, the LSI
It takes time and effort to create many hard macros. However, the tile differences described here are not due to the quasi-uniformity of the long range HPIC of the present invention. FIG. 10A shows a second example of the first embodiment of the HPIW of the present invention. This is an example in which the shift amount P in the long distance HPIC is 4 and the segment length N in the long distance HPILS is 12. FIG. 10B shows the rotation notation of the portion 71 in FIG. 10A. As can be seen from Fig. 10 (B), the programmable switch in the long-range HPIC
In tiles 40-10, 40-11, 40-12, 40-13 including 50-2,
All of these programmable switches are connected to the lowest wiring. Thus, even in the long-distance HPIC having the P tile shift structure (1 <P), it is possible to make all the tiles including the programmable switch in the long-distance HPIC the same. Generally, when the number of lanes M of the long-distance HPIC and the shift amount P are relatively prime, and only then, the wirings to which the programmable switches are connected in the tile can all be the same. Note that in FIG. 6B, both the programmable switch and the fixed logic value supply switch in the long distance HPIC are included in the same tile, but it is not always necessary to include these in the same tile. In general, there is only one fixed logic value supply switch for each ILS, and its position does not matter. FIG. 10B shows an example in which the programmable switch 50-2 and the fixed logic value supply switch 80 in the long distance HPIC are arranged in different tiles. In general, the fixed logic value supply switch 80 in the long range HPIC is also periodically placed every P tile. At this time, the same can be said for the tile including the fixed logic value supply switch as in the case of the programmable switch described above. That is, for all tiles including fixed logic value supply switches in the long distance HPIC, the necessary and sufficient conditions for connecting the fixed logic value supply switches to the same wiring are the number of lanes M of the long distance HPIC and the shift amount P. And are disjoint.

Next, a second embodiment of the HPIW of the present invention will be described. The second embodiment of the HPIW of the present invention is a plurality of HPIWs of the first embodiment of the present invention (each of which is
HPIW is called the sub-HPIW) is placed in parallel and is connected to the functional cell. FIG. 11 is an example of the configuration. HPIW20 consists of first and second sub-HPIW. The first sub-HPIW consists of the first short-range HPIC 21A, the first long-range HPIC 22A, and the first HPIC coupling that connects the two, and the second sub-HPIW is the second short-range HPIC 21B and the second short-range HPIC 21B. Each functional cell 10 is directly connected to the first and second short-range HPICs, which is composed of a long-range HPIC 22B and a second inter-HPIC coupling connecting both. Although FIG. 11 shows an example in which two sub HPIWs are installed, any number of sub HPIWs may be installed as needed. In the second embodiment of the HPIW of the present invention, the wiring resources are multiple times those of the first embodiment,
There is an advantage that routability is improved.

Next, a third embodiment of the HPIW of the present invention will be described. In the third embodiment of the HPIW of the present invention, the long distance HPICs in the second embodiment of the HPIW of the present invention are arranged so as to be shifted from each other. FIG. 12 is an example of the configuration. HPIW20 consists of first and second sub-HPIW.
The first deputy HPIW is the first short haul HPIC 21A and the first long haul
The HPIC22A and the first inter-HPIC coupling connecting them, the second sub-HPIW consists of the second short-range HPIC21B and the second long-range HPIC 22B, and the second inter-HPIC coupling connecting them, Each functional cell 10 is directly connected to the first and second short range HPICs. As shown in Figure 12, the second long-range HP
IC22B is shifted two tiles to the right compared to the first long-range HPIC 22A. As mentioned above, long range HPIC is not perfectly uniform for each functional cell. HPIW of the present invention
When a plurality of long-distance HPICs are placed at the same position as in the second embodiment, the non-uniformity is not improved because the joints (programmable switches) of all long-distance HPICs come to the same position. On the other hand, when a plurality of long-distance HPICs are shifted and arranged as in the third embodiment of the HPIW of the present invention, the joints of the long-distance HPICs are dispersed and arranged at different positions, so that the uniformity is improved. Becomes higher. Generally, when arranging L long-range HPICs having a P-shift structure, if the i + 1th long-range HPIC is shifted to the right by P / L tiles with respect to the i-th long-range HPIC (i = 1, 2, ... L-1), the most uniform.

Next, a fourth embodiment of the HPIW of the present invention will be described. The fourth embodiment of the HPIW of the present invention is one in which the number of long-range HPICs is smaller than the number of short-range HPICs. FIG. 13 is an example of the configuration. HPIW20 is a first and second short range HPIC 21A, 21B, and one long range HP
Includes IC 22. The short-range HPICs 21A and 21B are respectively coupled to the long-range HPIC 22 through the HPIC coupling, and each functional cell 10 is directly connected to both short-range HPICs. As mentioned above, long-range HPIC is generally less frequently used than short-range HPIC.
Therefore, as in the fourth embodiment of the HPIW of the present invention, by increasing only the number of short-range HPICs and suppressing the number of long-range HPICs, it is possible to avoid an unnecessary increase in wiring.

Next, a fifth embodiment of the HPIW of the present invention will be described. The fifth embodiment of the HPIW of the present invention includes a plurality of short-range HPs in the fourth embodiment of the HPIW of the present invention.
At least one of the ICs has a long-range HPIC and no HPIC coupling. FIG. 14 is an example of the configuration. HPIW20 is the first and second short range HPIC 21A, 21
B, and one long-range HPIC 22. The first and second short-range HPICs 21A and 21B are directly connected to each functional cell 10, and only the first short-range HPIC 21A is coupled to the long-range HPIC 22 via the inter-HPIC coupling. Second short range HPIC
Since there is no inter-HPIC coupling between the 21B and the long-distance HPIC 22, the load capacity applied to the short-distance HPIC 21B and the long-distance HPIC 22 is reduced as compared with the fourth embodiment (FIG. 13) of the HPIW of the present invention, and the signal is reduced. The transmission will be faster. In addition, the number of programmable switches forming the HPIC coupling is reduced, so that the circuit area is also reduced.

Next, a sixth embodiment of the HPIW of the present invention will be described. The sixth embodiment of the HPIW of the present invention consists of a sub-HPIW having a plurality of different structures. FIG. 15 (A)
An example of the first sub HPIW included in the sixth embodiment of the HPIW of the present invention is shown in FIG. The first deputy HPIW is the first short-range HPIC21
A and the first long-range HPIC 22A and the first connecting them both
It consists of HPIC-to-ICP coupling. The first short-range HPIC21A has a segment length of 5, consists of 5 lanes, and has a 1-tile shift structure. The first long haul HPIC22A has a segment length of 30,
It consists of 5 lanes and has a 6 tile shift structure.
The first short range HPIC 21A and the long range HPIC 22A are connected by one HPIC connection for each tile. Figure 15
(B) shows a rotation notation example of the configuration of the sixth embodiment of the HPIW of the present invention. This HP IW20 is
First sub HPIW (short range HPIC 21A, long range HPIC 22A
And their HPIC coupling) and a second sub-HPIW having the same structure as the second example of the first embodiment of the HPIW of the present invention.
(Short range HPIC 21B, long range HPIC 22B and their HPIC
Inter-joint) and. First and second short range HPIC21A,
21B is directly connected to each functional cell 10. The sixth embodiment of the HPIW of the present invention has a plurality of sub HPs having different segment lengths.
Since the IW is included, it is possible to provide wiring resources of various wiring lengths. This makes it possible to efficiently implement a wider variety of application circuits.

The second to sixth embodiments of the HPIW of the present invention have been described above, but what is shown here is only an example including the essence of the present invention. In particular, the number of sub HPIWs, the segment length of the short-range HPIC, and the shift amount of the long-range HPIC are not limited to the above example.

Generally, in a large scale circuit, a data path for processing multi-bit data occupies a larger area than a random logic. In particular, when reconfigurable computing is used to map a computer application to a circuit, the data path occupies a large proportion. Further, in such multi-bit data processing, most of the time, data having an integer multiple of a certain typical number of bits (for example, 8 bits) is handled, not an arbitrary bit width. In order to be able to efficiently implement such a circuit, it is arranged in a two-dimensional array within a reconfigurable device 100 (a portion of which is shown in the figure), as shown in FIG. The signal processing unit 110 is a collection of the tiles 40 each having the typical number of bits.
Then, it is preferable to configure the data path as a combination of the signal processing units 110. This signal processing unit
The 110 is called an ALU (arithmetic logic unit). In FIG. 16, each ALU 110 for one column at the left end is surrounded by a bold rectangle for the sake of clarity. Each ALU consists of 8 tiles that are arranged in a vertical column. The column direction in which these tiles are arranged (300 direction in Fig. 16) is the bit direction, and the direction perpendicular to that is data (200 direction in Fig. 16). Call it direction. ALU
Is a block in which a part of inputs of a plurality of functional cells constituting the same and a configuration memory are shared, and is compact as compared with the case where each functional cell is completely independent. Each ALU also has a carry signal 90 that propagates from the lowest tile to the highest tile. A specific example of such an ALU is disclosed in, for example, JP-A-11-353152.
Since the ALU has a long shape in the bit direction, the adjacent ALU
In the data transfer to and from, the transfer in the vertical direction (bit direction) requires a large cost in terms of wiring area and delay as compared with the transfer in the horizontal direction (data direction). Therefore, in order to create an efficient data path, data transfer in the bit direction should be suppressed as much as possible. Therefore, generally, in the programmable interconnection network of FIG. 1, the VPIW 30 running in the bit direction is less in demand than the HPIW 20 running in the data direction, and a small wiring resource is sufficient. Also,
In signal transmission in the data direction, since processing is often performed while sequentially transferring data to neighboring arithmetic units, high uniformity is required. Therefore, the HPIW of the present invention as described above is suitable. On the other hand, in the bit direction, signal processing is often performed in ALU units, so a VPIW suitable for it is required.

FIG. 17 is a structural example of the first embodiment of the VPIW of the present invention. This is a more detailed view of one row of functional cells 10 and the associated VPIW 30 in the two-dimensional array of FIG. (For the sake of clarity, the coupling means between the VPIW and the functional cell and the HPIW are not shown.) VPIW30
Is at least a short range vertical programmable interconnect channel 31 and a long range vertical programmable interconnect channel
32 and each vertical programmable interconnect channel
31 and 32 each consist of one or more lanes. Each lane consists of a series of ILSs connected in series via programmable switches. However, the long-distance vertical programmable interconnect channel may be composed of global wiring that extends seamlessly from the top edge to the bottom edge of the reconfigurable device. After that, the vertical programmable interconnect channel is VPIC, and the ILS that composes each lane is VPIC.
Abbreviated as ILS. In the example shown in FIG. 17, the short-range VPIC31
Is composed of two lanes, and each lane is composed of a short distance VPILS 121 with a length of one ALU vertically connected by a short distance VPIC programmable switch 50-5. Long-distance VPIC32
Consists of two lanes, each lane of short-distance VPILS 121
Comprised of a long-distance VPILS122 that is sufficiently long compared to. Of FIG.
Reference numeral 110 shows an example of the above-mentioned signal processing unit of multi-bit data, that is, one ALU. In the first embodiment of the VPIW of the present invention, the short-distance VPIC 31 has a sector structure having a seam at the boundary of each ALU. The wiring structure that is organized for each ALU is suitable for signal processing in ALU units. Each short distance VPIL
S is coupled to one long-distance VPILS via one inter-VPIC programmable switch 50-6. This coupling is called inter-VPIC coupling. A fixed logical value supply switch 80 is connected to each VPILS. The method of combining the VPIW and the functional cell will be described later.

FIG. 18 shows a structural example of the second embodiment of the VPIW of the present invention. The second embodiment of the VPIW of the present invention is
This is a shift structure introduced in VPIW. The configuration example of FIG. 18 is obtained by shifting one of the two lanes of the short distance VPIC 31 upward by a half ALU in the configuration example of FIG. VPIC associated with each short-distance VPILS associated with this shift
The inter-coupling and fixed logic supply switches shift as well, with one inter-VPIC coupling and fixed logic supply switch for each short-distance VPILS. This shift structure enables short distance VPILS without a crotch between the ALUs arranged vertically, which enables high-speed signal transmission between the ALUs in the vertical direction. Also, a short distance that seamlessly extends from the top tile to the bottom tile within each ALU.
Since VPILS is also available, it can be used for signal processing in ALU units.

In general, it is preferable that the length of the short distance VPILS be an integral multiple of the length of the ALU in the bit direction.
S is a wiring sufficiently longer than the short distance VPILS. As with HPIW, long haul VPIC is only accessible via short haul VPIC, so long haul VPILS is preferably four times longer than short haul VPILS. As mentioned above, vertical wiring is used less frequently than horizontal wiring, so the number of lanes K for short-distance VPIC is less than the number M of lanes for short-distance HPIC, and long-distance wiring is short-distance wiring. The number of lanes in long-distance VPIC should be less than K as it is less frequently used.
Each short-distance VPILS is one long-distance VPILS with one VPIC coupling
Connected to. However, when the number of lanes of the long-distance VPIC is smaller than the number of lanes of the short-distance VPIC, a plurality of lanes of the short-distance VPIC may be coupled to one lane of the long-distance VPIC between the VPICs. Short-distance VPIC has at least one lane
It is desirable to have a short distance VPILS that runs seamlessly from the top tile to the bottom tile in U (ie the programmable switches in the short distance VPIC are located at the boundaries of the ALU).

FIG. 19 shows a plurality of rows of HPIWs 20-1 to 20-6, a plurality of columns of VPIWs 30-1 to 30-5, and a two-dimensional array of functional cells 10.
And the coupling means between them are shown (the fixed logic value supply switch is not shown in order to avoid complication). This is the HPIW of the HP of the fourth embodiment shown in FIG.
This is an example in which IW is used and VPIW of the first embodiment shown in FIG. 17 is used as VPIW. In the bottom row of FIG. 19, tile examples 40-1 to 40-5 are shown. Each VPILS of short-range VPIC31
Of the short-distance HPILS intersecting with it, one HPILS for each row is coupled through the cross programmable switch 55 (this is called cross coupling). For example, short-range VPIL
The S121-1 has cross-coupling with a single HPILS in each row HPIC 21A, and the short-range VPILS121-2 has short-range HPIC 2A in each row.
It has a cross-link with one HPILS in 1B. Here, as shown in FIG. 20, the cross programmable switch 55 is composed of a wiring 57 running in the horizontal direction and a wiring 56 running in the vertical direction, which are connected via the programmable switch 50 at the intersection. Each functional cell can access the short-range VPIC only through short-range HPILS and cross-coupling. In the conventional FPGA, not only such cross-coupling between wirings but also functional cells and VPIC
There was also a direct connection between and. However, in the embodiment of the present invention, since the short-distance VPILS has a length of at least 1 ALU, if the direct connection with the functional cell is provided in all the tiles through which the short-distance VPILS pass, the load capacity becomes considerably large. In addition, if both the short-range VPIC and the short-range HPIC are directly connected to the functional cell, the input and output selection switches in the functional cell are enlarged, which also results in a large penalty in terms of area and delay. As described above, in the method of providing a large number of direct connections, the signal transmission speed does not increase as much as expected, although the area increases significantly.
On the other hand, the wiring structure accessible to the short-range VPIC only through the short-range HPIC as in the embodiment of the present invention has a sufficient programmable switch and a compact input and output selection switch to provide sufficient connectivity. There is an advantage that can be secured. In addition, the short-distance VPIC of the present invention has a lighter load, and thus can perform high-speed transmission as compared with the conventional one.
The delay penalty due to indirect access via HPIC can be compensated.

The wiring structure in which the short-distance VPIC accesses the functional cell through the short-distance HPIC has another advantage. That is, each short-distance VPILS can access not only the functional cells in the column through which it passes, but also the functional cells in the columns on the left and right sides of the column with equal delay. For example, in FIG.
The short-range VPILS 121-1 is accessible through the functional cell of the tile 40-3 through which it passes and the short-range HPILS, but the functional cells of the tiles 40-2 and 40-4 on both sides of it are also the same short-range HPILS. The shortest distance to VPILS121-1 can be accessed with the same delay as the functional cell of tile 40-3. On the contrary, each functional cell can access the short-distance VPILS of itself and its adjacent columns through the short-distance HPILS recently with the same delay. Thus, the connection between the functional cell and the short-range VPILS through one recent short-range HPILS and cross-coupling is VP.
Short-distance VPILS, which can be the shortest connection in IW and the shortest connection from functional cells, is recently called short-distance VPILS. In the example of FIG.
The short distance VPIC per row has only two lanes,
Each functional cell has a total of 6 recent short-distance VPILS, including the short-distance VPIC on both sides.

In the embodiment of the present invention, the long-distance VPIC is connected only to the short-distance VPIC by the inter-VPIC coupling, and in order to connect the functional cell to the long-distance VPIC, the short-distance HPIC and the short-distance VPIC are connected.
Have to go through. However, since there is only one coupling between VPICs for each short-distance VPILS, long-distance VPICs are
The load capacity of the long-distance VPIC is greatly reduced and its transmission speed becomes very high compared to the case where each has a function cell and HPIW of each row. Therefore, even in the signal transmission between functional cells via the long distance VPIC, the embodiment of the present invention is faster than the conventional example in the signal transmission of a sufficiently long distance. Moreover, in the embodiments of the present invention, the functional cells can access all the wiring resources and the access between all the programmable interconnect channels with a small number of programmable switches and compact input and output selection switches. is there.

[0048]

The first effect is that a high performance data path can be efficiently implemented. The reason is,
This is because the programmable interconnect having a high uniformity in the horizontal direction in which multi-bit data mainly moves is used. Furthermore, the vertical direction in which the ALU extends uses programmable interconnects suitable for ALU-unit processing, and the number of wires is smaller than that in the horizontal direction. The second effect is
It is possible to realize sufficient connectivity with a small number of switches. The reason is that the functional cell is directly connected only to the short range HPIC, and the short range VPIC and the long range HPIC access the functional cell through a few programmable switches and the short range HPIC. Furthermore, the long range VPIC is connected to the short range VPIC via a few programmable switches. The third effect is that high-speed signal transmission is possible. The reason is that long distance HPIC and long distance VPIC are connected with only a few programmable switches, so that the load is very light and high-speed signal transmission is possible. A fourth effect is that it is possible to reduce the number of long-distance wirings that are rarely used. The reason is that both the input and output access the long-distance wiring through the short-distance wiring,
This is because the number of long-distance wirings can be reduced without reducing accessibility and transmission speed.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a reconfigurable device.

FIG. 2 is a schematic diagram of the first embodiment of the HPIW of the present invention.

FIG. 3 is a first example of a programmable switch.

FIG. 4 is a second example of a programmable switch.

FIG. 5: Third example of programmable switch

FIG. 6A is a block diagram of the first embodiment of the HPIW of the present invention. FIG. 6B is a diagram showing the first embodiment of the HPIW of the present invention in the rotation notation.

FIG. 7 is a block diagram inside a functional cell.

FIG. 8 is a first example of a fixed logic value supply switch.

FIG. 9 is a second example of a fixed logical value supply switch.

FIG. 10 (A) is a block diagram of a second example of the first embodiment of the HPIW of the present invention, and (B) shows a second example of the first embodiment of the HPIW of the present invention in a rotation notation. Figure

FIG. 11 is a configuration diagram of a second embodiment of the HPIW of the present invention.

FIG. 12 is a block diagram of a third embodiment of the HPIW of the present invention.

FIG. 13 is a configuration diagram of a fourth embodiment of the HPIW of the present invention.

FIG. 14 is a configuration diagram of a fifth embodiment of the HPIW of the present invention.

15A is a first sub HPIW included in the sixth embodiment of the HPIW of the present invention, and FIG. 15B is a configuration diagram of the sixth embodiment of the HPIW of the present invention.

FIG. 16 is a schematic diagram of a reconfigurable device suitable for multi-bit data processing.

FIG. 17 is a block diagram of the first embodiment of the VPIW of the present invention.

FIG. 18 is a block diagram of a second embodiment of the VPIW of the present invention.

FIG. 19 is a diagram showing the entire configuration of a programmable interconnection network of the present invention.

FIG. 20 is a block diagram of a cross programmable switch.

FIG. 21 is a first example of a conventional programmable interconnection network.

FIG. 22 is a connection example of a conventional programmable interconnection network and a functional cell.

FIG. 23 is a second example of a conventional programmable interconnection network.

FIG. 24 is a third example of a conventional programmable interconnection network.

[Explanation of symbols]

1, 1-1, 1-2: 1-bit memory cell 2: NMOS transistor 3: PMOS transistor 4: Transmission gate 5-1, 5-2: Tri-state buffer 6: Ground 10: Functional cell 11, 11-i ( i is a natural number): Input selection switches 12, 12-i (i is a natural number): Function block input 13: Function block 14: Function block output 15: Output selection switch 16: Function cell input / output wiring 19: Programmable mutual Connections between connection networks and functional cells 20, 20-i (i is a natural number): Horizontal programmable interconnects (HPIW) 21, 21A, 21B: Short-range horizontal programmable interconnect channels (short-range HPIC) 21-1: Short haul HPIC lanes 22, 22A, 22B: Long haul horizontal programmable interconnect channels (long haul HPIC) 22-1: Long haul HPIC lanes 23-1, 23-2: Local bus 24-1, 24-2: Express Bus 25-1, 25-2: Super Bus 26: Local Feedback Channel 27: Intermediate Channel 28: Half Length Channel 29: Global Channels 30, 30-i (i is a natural number): Vertical Programmable Interconnect (VPIW) 31: Short Distance Vertical Programmable Interconnect Channel (Short Distance VPIC) 32: Long Distance Vertical Programmable Interconnect Channels (Long-Distance VPIC) 40, 40-i (i is a natural number): Tile 41: Example of recent function cell of long-distance HPILS 62-3 50: Programmable switch 50-1: Programmable within short-distance HPIC Switch 50-2: Long-distance HPIC programmable switch 50-3: HPIC-to-HPIC programmable switch 50-5: Short-distance VPIC programmable switch 50-6: VPIC-to-VP programmable switch 51-1, 51-2: Bidirectional programmable switch Terminal 55: Cross programmable switch 56: Vertically running wiring 57: Horizontally running wiring 58-1, 58-2: Programmable switch 59 in the conventional example Interconnection 61-i (i is a natural number): Short-distance horizontal programmable interconnect wiring segment (short distance HPILS) 62-i (i is a natural number): Long-distance horizontal programmable interconnect wiring segment (long distance HPILS) 63- i (i is a natural number): long-distance HPIC unit section 65-1: short-distance sector 65-2: long-distance sector 70, 71: HPIW for one row and a part of the functional cell 80: fixed logical value supply switch 81: fixed Output terminal of logical value supply switch 90: Carry signal of ALU 100: Reconfigurable device 110: Signal processing unit of multi-bit data processing 121, 121-1, 121-2: Short distance vertical programmable interconnection wiring segment (short distance VPILS) 122: Long-distance vertical programmable interconnect wiring segment (long-distance VPILS) 200: Data direction 300: Bit direction Vcc: Power supply voltage Q: Memory cell data output Qb: Memory cell inverted data output

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/177 H03K 19/173 101

Claims (32)

(57) [Claims] 1. An integrated circuit comprising a plurality of functional cells and a programmable interconnection network that connects the plurality of functional cells in a programmable manner, wherein the integrated circuit comprises one of the functional cells and the programmable interconnection network. It is configured by a two-dimensional array of tiles including a portion that passes through the vicinity of the functional cell, the functional cell can set various functions programmable, and at least one based on the set function from a plurality of inputs. A functional block that generates an output; an input selection switch that has a plurality of inputs and a plurality of sub-outputs and that can programmably set which of the plurality of inputs is transmitted to the sub-plurality of outputs; It has one input and can programmably set whether to transfer the input to each output or to make the output high impedance. A force selection switch and an input / output wiring, the output of the input selection switch is connected to the input of the functional block, the input of the output selection switch is connected to the output of the functional block, An input and an output of the output selection switch connected to the input / output wiring; the programmable interconnection network includes a horizontal programmable interconnection path that horizontally runs each row of the two-dimensional array, A horizontal programmable interconnect running in a direction includes a short range horizontal programmable interconnect channel and a long range horizontal programmable interconnect channel, the short range horizontal programmable interconnect channel comprising:
Consists of short-distance horizontal programmable switches placed horizontally for each M tile and short-distance horizontal interconnection wiring segments that are continuous wiring that connects between the adjacent short-distance horizontal programmable switches in the horizontal direction. A tile comprising first to Mth short-distance horizontal lanes, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane. Located to the right of the containing tile (i = 2,3, ... M), the long-distance horizontal programmable interconnect channel is
From the first, consisting of long-distance horizontal programmable switches placed horizontally every N tiles and long-distance horizontal interconnect wiring segments that are continuous wiring that connects each adjacent long-distance horizontal programmable switch. First
The tile comprising M long-distance horizontal lanes, the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane is the right of the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane. Located at the P-th position (i = 2,3, ... M), where M, N, P are natural numbers, and N = P · M and 4 ≤
P, each of the short-distance horizontal interconnect wiring segments is coupled to one of the long-distance horizontal interconnect wiring segments via one horizontal channel-to-channel programmable switch, and the horizontal inter-channel programmable switch to each tile. One long horizontal interconnect wiring segment connected to the horizontal inter-channel programmable switch included in any M tiles arranged in a row in the horizontal direction belongs to different lanes. Each of the input / output wires is directly connected to each of the short distance horizontal interconnect wire segments that pass through the tile within each tile, and the programmable switch is capable of programmable connection or disconnection between two terminals. A reconfigurable device characterized by being a circuit. 2. The tile according to claim 1, wherein the tiles in each column of the two-dimensional array form an ALU grouped by U, and a plurality of functional cells in the ALU are:
At least one of configuration data that determines the functions of the functional block and the input selection switch, an input of the input selection switch, and an input of the functional block is shared, and the programmable interconnection network further includes the two-dimensional array. A vertical programmable interconnect for vertically running each column, the vertical programmable interconnect for vertically running each column includes a short-range vertical programmable interconnect channel and a long-range vertical vertical programmable interconnect channel; The short range vertical programmable interconnect channel is
It consists of short-distance vertical programmable switches placed vertically for each V tile, and short-distance vertical interconnect wiring segments that are continuous wiring that connects between the vertically adjacent short-distance vertical programmable switches. The first to Wth short vertical lanes, the short vertical interconnect wiring segments of at least one of the short vertical lanes being seamless and continuous from the top tile to the bottom tile in the ALU. Extended wiring, the long distance vertical programmable interconnect channel
Comprising L long-distance vertical lanes running in a vertical direction, each of the long-distance vertical lanes including a vertical-running wire having a length of four times or more of the short-distance vertical interconnect wire segment, and the natural number V is An integer multiple of the natural number U, the natural numbers L, W, M satisfy L ≤ W <M, and each of the short-distance vertical programmable interconnect wiring segments corresponds to one long-distance vertical interconnect wiring segment. Coupled via one programmable switch, each said short-distance vertical programmable interconnect wiring segment intersecting with each one of said short-distance horizontal programmable interconnect wiring segments being connected via a cross programmable switch. Characterizing reconfigurable device. 3. The reconfigurable device according to claim 1, wherein the M and the P are prime to each other. 4. The reconfigurable device according to claim 2, wherein the M and the P are prime to each other. 5. An integrated circuit comprising a plurality of functional cells and a programmable interconnection network that connects the plurality of functional cells in a programmable manner, wherein the integrated circuit comprises one of the functional cells and the programmable interconnection network. It is configured by a two-dimensional array of tiles including a portion that passes through the vicinity of the functional cell, the functional cell can set various functions programmable, at least one based on the set function from a plurality of inputs. A functional block that generates an output; an input selection switch that has a plurality of inputs and a plurality of sub-outputs, and that can programmably set which of the plurality of inputs is transmitted to the sub-plurality of outputs; It has one input and can programmably set whether to transfer the input to each output or to make the output high impedance. A force selection switch and input / output wiring, the output of the input selection switch is connected to the input of the functional block, the input of the output selection switch is connected to the output of the functional block, An input and an output of the output selection switch connected to the input / output wiring; the programmable interconnection network includes a plurality of horizontal programmable interconnection paths that run in a horizontal direction in each row of the two-dimensional array; Each of the horizontal programmable interconnects of: comprises a short range horizontal programmable interconnect channel and a long range horizontal programmable interconnect channel, wherein the short range horizontal programmable interconnect channel is
Consists of short-distance horizontal programmable switches placed horizontally for each M tile and short-distance horizontal interconnection wiring segments that are continuous wiring that connects between the adjacent short-distance horizontal programmable switches in the horizontal direction. A tile comprising first to Mth short-distance horizontal lanes, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane. Located to the right of the containing tile (i = 2,3, ... M), the long-distance horizontal programmable interconnect channel is
From the first, consisting of long-distance horizontal programmable switches placed horizontally every N tiles and long-distance horizontal interconnect wiring segments that are continuous wiring that connects each adjacent long-distance horizontal programmable switch. First
The tile comprising M long-distance horizontal lanes, the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane is the right of the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane. Located at the P-th position (i = 2,3, ... M), where M, N, P are natural numbers, and N = P · M and 4 ≤
P, each of the short distance horizontal interconnect wiring segments is coupled via a single horizontal channel programmable switch with one of the long distance horizontal interconnect wiring segments belonging to the same horizontal programmable interconnect path as In each of the horizontal programmable interconnection paths, the horizontal inter-channel programmable switch is included in each tile, and the horizontal inter-channel programmable switch included in any of M tiles arranged in the horizontal direction is connected. The long distance horizontal interconnect wiring segments all belong to different lanes, and each of the input / output wires of the functional cell is directly connected to each of the short distance horizontal interconnect wiring segments passing through the tile in each tile. , The programmable switch connects between two terminals A reconfigurable device that is a circuit that can be connected or disconnected in a ramable manner. 6. The tile according to claim 5, wherein the tiles in each column of the two-dimensional array form an ALU grouped by U, and a plurality of functional cells in the ALU are:
At least one of configuration data that determines the functions of the functional block and the input selection switch, an input of the input selection switch, and an input of the functional block is shared, and the programmable interconnection network further includes the two-dimensional array. A vertical programmable interconnect for vertically running each column, the vertical programmable interconnect for vertically running each column includes a short-range vertical programmable interconnect channel and a long-range vertical vertical programmable interconnect channel; The short range vertical programmable interconnect channel is
It consists of short-distance vertical programmable switches placed vertically for each V tile, and short-distance vertical interconnect wiring segments that are continuous wiring that connects between the vertically adjacent short-distance vertical programmable switches. The first to Wth short vertical lanes, the short vertical interconnect wiring segments of at least one of the short vertical lanes being seamless and continuous from the top tile to the bottom tile in the ALU. Extended wiring, the long distance vertical programmable interconnect channel
Comprising L long-distance vertical lanes running in a vertical direction, each of the long-distance vertical lanes including a vertical-running wire having a length of four times or more of the short-distance vertical interconnect wire segment, and the natural number V is An integer multiple of the natural number U, the natural numbers L, W, M satisfy L ≤ W <M, and each of the short-distance vertical programmable interconnect wiring segments corresponds to one long-distance vertical interconnect wiring segment. Two short-distance vertical programmable interconnect wiring segments that intersect each other, and each short-distance horizontal programmable interconnect wiring segment is connected to each short-row horizontal programmable interconnect wiring segment through a cross-programmable switch. A plurality of the cross programmable switches included in a tile are different from each other in the short distance horizontal programmable interconnect array. Reconfigurable Device characterized in that it is connected to the segment. 7. The reconfigurable device according to claim 5, wherein the M and the P are mutually prime. 8. The reconfigurable device according to claim 6, wherein the M and the P are mutually prime. 9. The method of claim 5, wherein between at least two of the plurality of horizontal programmable interconnects, the long-distance horizontal programmable switches belonging to them are at least one tile apart from each other in the horizontal direction. Reconfigurable device. 10. The method of claim 6, wherein between at least two of the plurality of horizontal programmable interconnects,
A reconfigurable device, characterized in that the long-distance horizontal programmable switches belonging to them are horizontally separated from each other by at least one tile. 11. The reconfigurable device according to claim 9, wherein the M and the P are mutually prime. 12. The M and the P according to claim 10.
A reconfigurable device characterized in that and are mutually prime. 13. The reconfiguration of claim 5, wherein among the plurality of horizontal programmable interconnects, the long distance horizontal programmable switches belonging to them are horizontally separated from each other by at least one tile. Possible device. 14. The reconfiguration of claim 6, wherein among the plurality of horizontal programmable interconnects, the long distance horizontal programmable switches belonging to them are horizontally separated from each other by at least one tile. Possible device. 15. The M and the P according to claim 13,
A reconfigurable device characterized in that and are mutually prime. 16. The M and the P according to claim 14.
A reconfigurable device characterized in that and are mutually prime. 17. An integrated circuit comprising a plurality of functional cells and a programmable interconnection network that connects the plurality of functional cells in a programmable manner, wherein the integrated circuit comprises one of the functional cells and the programmable interconnection network. It is configured by a two-dimensional array of tiles including a portion that passes through the vicinity of the functional cell, the functional cell can set various functions programmable, and at least one based on the set function from a plurality of inputs. A functional block that generates an output; an input selection switch that has a plurality of inputs and a plurality of sub-outputs and that can programmably set which of the plurality of inputs is transmitted to the sub-plurality of outputs; It has one input and can be programmable whether to transfer the input to each output or to make the output high impedance. An output selection switch and an input / output wiring, the output of the input selection switch is connected to the input of the functional block, the input of the output selection switch is connected to the output of the functional block, An input and an output of the output selection switch connected to the input / output wiring; the programmable interconnection network includes a plurality of horizontal programmable interconnection paths that run in a horizontal direction in each row of the two-dimensional array; Each of the horizontal programmable interconnects of the plurality of horizontal programmable interconnects includes a short-range horizontal programmable interconnect channel, a portion of the plurality of horizontal programmable interconnects further includes a long-range horizontal programmable interconnect channel, and the short-range horizontal programmable interconnect channel. Is
Consists of short-distance horizontal programmable switches placed horizontally for each M tile and short-distance horizontal interconnection wiring segments that are continuous wiring that connects between the adjacent short-distance horizontal programmable switches in the horizontal direction. A tile comprising first to Mth short-distance horizontal lanes, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane, the tile including the short-distance horizontal programmable switch of the i-th short-distance horizontal lane. Located to the right of the containing tile (i = 2,3, ... M), the long-distance horizontal programmable interconnect channel is
From the first, consisting of long-distance horizontal programmable switches placed horizontally every N tiles and long-distance horizontal interconnect wiring segments that are continuous wiring that connects each adjacent long-distance horizontal programmable switch. First
The tile comprising M long-distance horizontal lanes, the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane is the right of the tile containing the long-distance horizontal programmable switch of the i-th long-distance horizontal lane. Located at the P-th position (i = 2,3, ... M), where M, N, P are natural numbers, and N = P · M and 4 ≤
At each of the horizontal programmable interconnects satisfying P and including the long distance horizontal programmable interconnect channels,
Each of the short distance horizontal interconnect wiring segments is coupled to one of the long distance horizontal interconnect wiring segments belonging to the same horizontal programmable interconnect path as that via one horizontal channel programmable switch,
The horizontal inter-channel programmable switch is included in each tile, and the long-distance horizontal interconnection wiring segment to which the horizontal inter-channel programmable switch included in any of M tiles that are continuously arranged in the horizontal direction is connected. All belong to different lanes, each of the input / output wires of the functional cell is directly connected to each of the short distance horizontal interconnect wire segments passing through the tile in each tile, and the programmable switch has two terminals. A reconfigurable device, which is a circuit capable of programmable connection and disconnection. 18. The tile according to claim 17, wherein the tiles of each column of the two-dimensional array form an ALU grouped by U, and a plurality of functional cells in the ALU are:
At least one of configuration data that determines the functions of the functional block and the input selection switch, an input of the input selection switch, and an input of the functional block is shared, and the programmable interconnection network further includes the two-dimensional array. A vertical programmable interconnect for vertically running each column, the vertical programmable interconnect for vertically running each column includes a short-range vertical programmable interconnect channel and a long-range vertical vertical programmable interconnect channel; The short range vertical programmable interconnect channel is
It consists of short-distance vertical programmable switches placed vertically for each V tile, and short-distance vertical interconnect wiring segments that are continuous wiring that connects between the vertically adjacent short-distance vertical programmable switches. The first to Wth short vertical lanes, the short vertical interconnect wiring segments of at least one of the short vertical lanes being seamless and continuous from the top tile to the bottom tile in the ALU. Extended wiring, the long distance vertical programmable interconnect channel
Comprising L long-distance vertical lanes running in a vertical direction, each of the long-distance vertical lanes including a vertical-running wire having a length of four times or more of the short-distance vertical interconnect wire segment, and the natural number V is An integer multiple of the natural number U, the natural numbers L, W, M satisfy L ≤ W <M, and each of the short-distance vertical programmable interconnect wiring segments corresponds to one long-distance vertical interconnect wiring segment. Two short-distance vertical programmable interconnect wiring segments that intersect each other, and each short-distance horizontal programmable interconnect wiring segment is connected to each short-row horizontal programmable interconnect wiring segment through a cross-programmable switch. A plurality of the cross programmable switches included in a tile are different from each other in the short distance horizontal programmable interconnect array. Reconfigurable Device characterized in that it is connected to the segment. 19. The M and the P according to claim 17.
A reconfigurable device characterized in that and are mutually prime. 20. The M and the P according to claim 18.
A reconfigurable device characterized in that and are mutually prime. 21. The at least one horizontal programmable interconnect path of claim 17, further comprising at least one said horizontal programmable interconnect channel, wherein each of said short range horizontal interconnect wiring segments comprises said long range horizontal programmable interconnect channel. The long distance horizontal interconnection wiring segment belonging to the horizontal programmable interconnection path including the connection channel is coupled through one horizontal channel programmable switch, and one horizontal channel programmable switch is included in each tile. , The long-distance horizontal interconnect wiring segments connected to the programmable switches between the horizontal channels included in any M tiles arranged in a row in the horizontal direction are all in different lanes, and reconfigurable. device. 22. The at least one horizontal programmable interconnect path of claim 18, further comprising at least one said horizontal programmable interconnect channel, wherein each of said short range horizontal interconnect wiring segments comprises said long range horizontal programmable interconnect channel. The long distance horizontal interconnection wiring segment belonging to the horizontal programmable interconnection path including connection channels is coupled through one horizontal channel programmable switch, and one horizontal channel programmable switch is included in each tile. , The long-distance horizontal interconnection wiring segments connected to the programmable switches between the horizontal channels included in any M tiles arranged in a row in the horizontal direction are all reconfigurable in that they belong to different lanes. device. 23. The M and the P according to claim 21.
A reconfigurable device characterized in that and are mutually prime. 24. The M and the P according to claim 22.
A reconfigurable device characterized in that and are mutually prime. 25. An integrated circuit comprising a plurality of functional cells and a programmable interconnection network that connects the plurality of functional cells in a programmable manner, wherein the integrated circuit comprises one of the functional cells and the programmable interconnection network. It is configured by a two-dimensional array of tiles including a portion that passes through the vicinity of the functional cell, the functional cell can set various functions programmable, and at least one based on the set function from a plurality of inputs. A functional block that generates an output; an input selection switch that has a plurality of inputs and a plurality of sub-outputs, and that can programmably set which of the plurality of inputs is transmitted to the sub-plurality of outputs; It has one input and can be programmable whether to transfer the input to each output or to make the output high impedance. An output selection switch and an input / output wiring, the output of the input selection switch is connected to the input of the functional block, the input of the output selection switch is connected to the output of the functional block, An input and an output of the output selection switch connected to the input / output wiring, and the programmable interconnection network includes first to Jth horizontal programmable interconnection paths that run horizontally in each row of the two-dimensional array. Including first to Jth horizontal programmable interconnects each including a short-range horizontal programmable interconnect channel, wherein the first to Jth horizontal programmable interconnects include first to Kth horizontal programmable interconnects. The connection path further includes a long-distance horizontal programmable interconnect channel, wherein J and K are natural numbers K ≤ J. In the jth horizontal programmable interconnect, the short-range horizontal programmable interconnect channels are adjacent to each other in the horizontal direction by short-range horizontal programmable switches placed for each Mj tile in the horizontal direction. Consisting of first to Mj short-distance horizontal lanes composed of short-distance horizontal interconnection wiring segments that are continuous wirings connecting the short-distance horizontal programmable switches, and the short wiring of the i-th short-distance horizontal lane. The tile including the distance horizontal programmable switch is located to the right of the tile including the short distance horizontal programmable switch in the i-1th short distance horizontal lane (i = 2,3, ... Mj), and the Mj is Is a natural number (j = 1, 2, ... J), and in the first to Kth horizontal programmable interconnects, the jth horizontal programmable phase The long-distance horizontal programmable interconnect channel of the interconnection path is a long-distance horizontal programmable switch placed horizontally for each Nj tile and continuous wiring connecting each adjacent long-distance horizontal programmable switch. A tile comprising the first to Mj long-distance horizontal lanes composed of the long-distance horizontal interconnection wiring segments, the tile including the long-distance horizontal programmable switch of the i-th long-distance horizontal lane is the i-th long Is located Pjth to the right of the tile containing the long-distance horizontal programmable switch in the long-distance horizontal lane (i = 2,3, ... Mj, j = 1, ... K), and Nj and Pj are natural numbers. Yes, Nj = Pj · Mj and 4
Satisfying ≦ Pj (j = 1, ... K), the natural numbers P1 to PK
At least two of which are different and / or at least two of the natural numbers M1 to MK are different, and each of the short distance horizontal interconnection wiring segments is One long-distance horizontal interconnection wiring segment belonging to the same horizontal programmable interconnection path is coupled through one horizontal channel programmable switch, and one horizontal channel programmable switch is included in each tile. The long-distance horizontal interconnection wiring segments connected to the programmable switches between the horizontal channels included in any Mj tiles arranged consecutively in the direction all belong to different lanes (j = 1, ... K).
), Each of the input and output wires of the functional cell is directly connected to each of the short distance horizontal interconnect wire segments that pass through the tile within each tile, and the programmable switch programmableally connects between two terminals. A reconfigurable device, which is a circuit that can be turned on and off. 26. The tile according to claim 25, wherein the tiles in each column of the two-dimensional array form an ALU grouped by U, and a plurality of functional cells in the ALU are:
At least one of configuration data that determines the functions of the functional block and the input selection switch, an input of the input selection switch, and an input of the functional block is shared, and the programmable interconnection network further includes the two-dimensional array. A vertical programmable interconnect for vertically running each column, the vertical programmable interconnect for vertically running each column includes a short-range vertical programmable interconnect channel and a long-range vertical vertical programmable interconnect channel; The short range vertical programmable interconnect channel is
It consists of short-distance vertical programmable switches placed vertically for each V tile, and short-distance vertical interconnect wiring segments that are continuous wiring that connects between the vertically adjacent short-distance vertical programmable switches. The first to Wth short vertical lanes, the short vertical interconnect wiring segments of at least one of the short vertical lanes being seamless and continuous from the top tile to the bottom tile in the ALU. Extended wiring, the long distance vertical programmable interconnect channel
Comprising L long-distance vertical lanes running in a vertical direction, each of the long-distance vertical lanes including a vertical-running wire having a length of four times or more of the short-distance vertical interconnect wire segment, and the natural number V is An integer multiple of the natural number U, the natural numbers L, W, M satisfy L ≤ W <M, and each of the short-distance vertical programmable interconnect wiring segments corresponds to one long-distance vertical interconnect wiring segment. Two short-distance vertical programmable interconnect wiring segments that intersect each other, and each short-distance horizontal programmable interconnect wiring segment is connected to each short-row horizontal programmable interconnect wiring segment through a cross-programmable switch. A plurality of the cross programmable switches included in a tile are different from each other in the short distance horizontal programmable interconnect array. Reconfigurable Device characterized in that it is connected to the segment. 27. The reconfigurable device according to claim 25, wherein the Mj and the Pj are disjoint in at least j of any one of 1 to K. 28. The reconfigurable device according to claim 26, wherein the Mj and the Pj are disjoint at least in j of any one of 1 to K. 29. The at least one of the K + 1 to Jth horizontal programmable interconnects of claim 25, wherein each of the short distance horizontal interconnect wiring segments is a jth horizontal programmable interconnect. Connected to one of the long-distance horizontal interconnection wiring segments belonging to, through one horizontal channel programmable switch, one horizontal channel programmable switch is included in each tile, and arranged horizontally in series. The long distance horizontal interconnect wiring segments to which the horizontal channel-to-horizontal programmable switches included in any Mj tiles are connected belong to different lanes, and j is one of 1 to K. Configurable device. 30. The at least one of the K + 1 to Jth horizontal programmable interconnects of claim 26, wherein each of the short distance horizontal interconnect wiring segments is a jth horizontal programmable interconnect. Connected to one of the long-distance horizontal interconnect wiring segments belonging to the above through one horizontal channel programmable switch, one horizontal channel programmable switch is included in each tile, and is horizontally aligned. The long distance horizontal interconnect wiring segments to which the horizontal channel programmable switches in any Mj tiles are connected all belong to different lanes, and j is one of 1 to K. Configurable device. 31. The reconfigurable device according to claim 29, wherein the Mj and the Pj are prime to each other in at least one j of K. 32. The reconfigurable device according to claim 30, wherein the Mj and the Pj are disjoint in at least j of any one of 1 to K.