JP3492973B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.
In particular, the present invention relates to a method for manufacturing a MOS type semiconductor device having an elevated source / drain diffusion layer stacked above an interface between a gate insulating film and a semiconductor substrate.
Concerned.

[0002]

2. Description of the Related Art In recent years, integrated circuits in which a large number of transistors, resistors and the like are integrated on a semiconductor substrate have been widely used in central parts of computers and communication equipment. The design rule of this kind of integrated circuit tends to be reduced year by year as the device is highly integrated.

In the MOS type integrated circuit, in order to suppress the short channel effect due to the reduction of the gate length, it is required to make the depth of the diffusion layer shallow. On the other hand, the resistance of the resistance due to the shallow depth of the diffusion layer is required. It is necessary to prevent the increase.

As a method of keeping the diffusion layer resistance low while making the diffusion layer depth shallow, an elevated source / drain structure in which only the source / drain regions are lifted upward,
It is said that a manufacturing method in which silicide, which is a compound of silicon and a metal, is combined with salicide formed in a self-aligned manner is effective.

[0005]

The technique for forming an elevated source / drain structure has been attempted by several methods so far. For example, as a method of selectively forming only the source / drain portions with a single crystal silicon film, a method of vapor phase epitaxial growth, a method of depositing amorphous silicon and then solid phase epitaxial growth, and doping impurities by an implantation process are proposed. Has been done.

However, in the conventionally proposed methods,
There are various problems such as inferior selective growth property and selective removal property of amorphous silicon, and deepening of diffusion layer depth due to activation annealing of doped impurities and crystallinity recovery annealing.

As a method of forming a diffusion layer, a method of forming a diffusion layer after etching a semiconductor substrate to the depth of the diffusion layer in advance (Japanese Patent Laid-Open No. 11-186542), depositing amorphous silicon and performing selective solid phase growth Method of implanting conductivity type impurities after silicidizing the exposed region (Japanese Patent Laid-Open No. 7-2
2338), a method of selectively depositing amorphous silicon only on the source / drain portions (Japanese Patent Laid-Open No. 9-82957) and the like have been proposed.

However, in these conventional diffusion layer forming methods, a short channel effect may occur depending on the etching amount of the semiconductor substrate surface. Further, if impurities are introduced by implantation, an annealing step must be performed after that, and the diffusion layer cannot be made thin. Further, since the precision of the selective etching cannot be increased, there is a problem that the source / drain regions cannot be formed into a desired shape / size.

When the elevated source / drain diffusion layer is formed by solid phase growth, (111) -facet is generated in the vicinity of the gate oxide film and the element isolation, and the upper surface of the diffusion layer is silicidized. The distance from the pn junction becomes short, and leakage easily occurs. Further, there arises a problem that the impurity concentration immediately below the gate is reduced and the diffusion layer resistance is increased.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device capable of forming a shallow diffusion layer in a semiconductor substrate and reducing the resistance of the diffusion layer, and a manufacturing method thereof. To do.

[0011]

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device having a MOS transistor formed on a semiconductor substrate,
The step of depositing an amorphous silicon film containing conductive impurities on the upper surface of the semiconductor substrate, and the solid-phase epitaxial growth of the amorphous silicon film while inheriting the crystal orientation of the semiconductor substrate from the interface between the gate insulating film and the semiconductor substrate. A step of forming an elevated source / drain diffusion layer in which the upper surface of the source / drain region is higher, and an n-type MOS transistor and a p-type MOS each having an elevated source / drain diffusion layer
And a step of forming a CMOS including a transistor, and before forming an amorphous silicon film on one of the n-type MOS transistor and the p-type MOS transistor, an n-type MOS transistor region and a p-type MOS transistor are formed.
A carbon mask material covering the transistor region is formed, and the carbon mask material on the MOS transistor region forming the amorphous silicon film is removed by etching to remove the other MO of the n-type MOS transistor and the p-type MOS transistor.
Provided is a method for manufacturing a semiconductor device, which comprises forming a carbon mask covering an S transistor region.

In the present invention, the source / drain regions are formed by solid phase epitaxial growth, and the shape and thickness of the source / drain regions can be set individually for the n-type MOS transistor and the p-type MOS transistor. The resistance can be reduced and the parasitic capacitance can be reduced. Further, since the elevated source / drain diffusion layers are formed by solid phase epitaxial growth, the junction depth can be made shallow and the short channel effect can be suppressed. Further, since the diffusion layer can be formed thick, the resistance can be reduced.

[0013]

In the present invention, an n-type MOS transistor and a p-type
Since carbon is used as a mask material when forming the type MOS transistor, the precision of selective etching can be improved.

[0015]

[0016]

[0017]

[0018]

In the present invention, amorphous silicon or polycrystalline silicon which is not single-crystallized is removed by wet etching, so that the precision of selective etching can be improved by a simple method.

[0020]

In the present invention, since the upper surfaces of the elevated source / drain regions are silicidized, the distance between the silicide interface and the pn junction can be increased, leakage can be reduced, and the use of silicide can reduce the resistance. Can be achieved.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention will be specifically described below with reference to the drawings. Hereinafter, a case of manufacturing a MOS transistor as a semiconductor device will be described.

Reference Example 1 FIGS. 1 to 4 are sectional views showing steps of manufacturing a MOS transistor according to Reference Example 1 of the present invention. First, as shown in FIG. 1 (a), a gate insulating film 103 is formed in a region isolated by an element isolation region 102 on a semiconductor substrate 101 by a known method, and an upper surface of the insulating material 105 (for example, silicon nitride) is formed. A gate electrode 104 covered with a film is formed.

Next, by using a CVD (Chemical Vapor Deposition) apparatus, a substance 106 which becomes a side wall of the gate electrode 104, for example, a silicon nitride film is deposited (FIG. 1).
(b)). The material used for the sidewall of the gate electrode is not limited to silicon nitride. Further, the deposition device is not limited to the CVD device, and a sputtering device, a vapor deposition device or the like may be used.

Next, as a plasma etching apparatus, for example, a RIE (Reactive Ion Etching) apparatus is used to perform etching to form the gate sidewall 106 as shown in FIG. 1 (c). Note that the gate electrode may be oxidized before depositing the gate sidewall material. In the following, the case where the side wall of the electrode is oxidized will be described, but this oxide film is omitted in FIG.

Next, as shown in FIG. 1D, for example, a silicon nitride film is deposited by a CVD device as a mask material 107 for masking one MOS region. The material used for the mask material is not limited to silicon nitride. Further, the deposition device is not limited to the CVD device, and a sputtering device, a vapor deposition device or the like may be used.

Next, a lithographic process is performed to remove NF ₃ gas 3
Plasma etching is performed at a flow rate of 0 sccm and 60 sccm of Cl ₂ gas to etch the nMOS region of the mask material 107 with high selectivity with respect to the gate insulating film, the gate sidewall, and the element isolation region (FIG. 1 (e)).

Next, the gate insulating film 103 on the source / drain region of the nMOS is subjected to a dilute hydrofluoric acid treatment to expose the surface of the source / drain region of the nMOS (FIG. 2 (a)). Next, after treating the surface of the substrate with a gas containing hydrogen, an in-situ P-type plasma treatment with a silicon-based gas such as silane (SiH ₄ ) is performed using an LPCVD apparatus.
Amorphous silicon 108 containing phosphorus is flushed with H ₃ gas.
It is deposited to a thickness of 00 nm (Fig. 2 (b)).

Next, annealing is performed at a temperature of 500 ° C. to 850 ° C. to selectively perform solid phase epitaxial growth of the amorphous silicon 108 on the source / drain regions using the semiconductor substrate as a seed portion. As a result, as shown in Fig. 2 (c), the pMOS
The solid phase epitaxial growth film 109 is formed in the formation region, and the amorphous silicon film 110 is formed in the nMOS formation region.

Next, wet etching is performed for 10 minutes with an etching solution having a composition ratio of hydrofluoric acid: nitric acid: pure water = 1: 50: 75, and the amorphous silicon film 110 is selected with respect to the solid phase epitaxial growth film 109 with good selectivity. Etching (Fig. 2
(d)).

Next, plasma etching is performed at a flow rate of 30 sccm of NF ₃ gas and 60 sccm of Cl ₂ gas to etch the mask material with good selectivity (FIG. 3 (a)). It is desirable to oxidize the solid phase growth film 109 before etching. Hereinafter, the case where the solid phase growth film is oxidized will be described. This oxide film is not shown.

Although a pMOS is formed in FIG. 3B and subsequent figures, the pMOS is also formed.
It is formed in the same procedure as nMOS.

First, a silicon nitride film 112 is deposited by a CVD apparatus (FIG. 3 (b)), and then a lithography process is performed to change the pMOS region in the silicon nitride film 112 to NF ₃ gas 30sccm, Cl ₂ gas 60sc.
Plasma etching is performed at a flow rate of cm to achieve high selectivity (Fig. 3 (c)).

Next, the oxide film 103 on the source / drain regions of the pMOS is treated with dilute hydrofluoric acid to expose the surface of the source / drain regions of the pMOS. Next, after the substrate surface is treated with a gas containing hydrogen (Fig. 3 (d)), a silicon-based gas such as silane (SiH ₄ ) and B ₂ H ₆ gas are flown in-situ using an LPCVD device. Then, amorphous silicon 113 containing boron is deposited (FIG. 4 (a)).

Next, as shown in FIG. 4 (b), 500 ° C. to 850 ° C.
By annealing between the two, amorphous silicon on the source / drain regions is selectively solid-phase epitaxially grown using the semiconductor substrate as a seed portion. This allows
The solid phase epitaxial growth film 114 and the amorphous silicon film 115 are formed adjacent to each other.

Next, a wet etching process is performed for 12 minutes with an etching solution having a composition of hydrofluoric acid: nitric acid: pure water = 1: 50: 75 to etch the amorphous silicon film 115 with respect to the solid phase epitaxial growth film 114 with good selectivity. Yes (Fig. 4
(c)).

Next, plasma etching is performed on the silicon nitride film 112 at a flow rate of 30 sccm of NF ₃ gas and 60 sccm of Cl ₂ gas to etch with good selectivity (FIG. 4 (d)). It is desirable to oxidize the solid phase growth film 114 before etching. Hereinafter, the case where the solid phase growth film is oxidized will be described, but this oxide film is not shown.

The source / drain regions formed by the above steps can have different shapes for nMOS and pMOS. Also, the solid phase growth film thickness of nMOS and pMOS can be set individually.

Although FIGS. 1 to 4 show an example in which the pMOS region is formed after the nMOS region is formed first, the pMOS region is formed.
The nMOS region may be formed after forming the region.

Further, although the example in which the gate side wall is formed has been described with reference to FIGS. 1 to 4, a structure in which the gate side wall is not formed is also conceivable. For example, FIGS. 5 to 8 are cross-sectional views showing a manufacturing process of a semiconductor device when the gate sidewall is not formed. Figure 5 (a)
Then, the upper surface is an insulating material 205 (for example, a silicon nitride film)
After the gate electrode 204 covered with is formed, the gate sidewall is oxidized to form an oxide film 206 as shown in FIG. 5B. Thereafter, the same steps as those in FIGS. 1 to 4 are performed, and finally a semiconductor device having a shape as shown in FIG. 8D is obtained.

5 to 8, reference numeral 201 is a semiconductor substrate, reference numeral 202 is an element isolation region, reference numeral 203 is a gate insulating film, reference numeral 204 is a gate electrode, reference numeral 205 is an insulating material, and reference numeral 206 is gate insulating. A film, reference numeral 207 is a mask material, reference numeral 208 is amorphous silicon, reference numeral 209 is a solid phase epitaxial growth film, reference numeral 210 is an amorphous silicon film, reference numeral 212 is a silicon nitride film, reference numeral 214 is a solid phase epitaxial growth film, and reference numeral 215 is an amorphous silicon film. Are shown respectively.

In the MOS transistors shown in FIGS. 1 to 4 and the MOS transistors shown in FIGS. 5 to 8 described above, an example in which the upper surfaces of the gate electrodes 104 and 204 are covered with the insulating material 105 and 205 has been described. It may not be covered with a substance. For example, FIGS. 9 to 12 show an example in which the oxide film on the upper surface of the gate electrode is removed when the source / drain regions are treated with dilute hydrofluoric acid.

9 to 12, reference numeral 301 is a semiconductor substrate, reference numeral 302 is an element isolation region, reference numeral 303 is a gate insulating film,
Reference numeral 304 is a gate electrode, reference numeral 305 is an insulating material, reference numeral 306
Is a gate side wall, 307 is a mask material, 308 is amorphous silicon, 309 is a solid phase epitaxial growth film,
Reference numeral 310 is an amorphous silicon film, reference numeral 312 is a silicon nitride film, reference numeral 314 is a solid phase epitaxial growth film, reference numeral 315.
Indicates an amorphous silicon film, and symbols 316 and 317 indicate polycrystalline silicon.

On the other hand, FIGS. 13 to 16 show at least the plasma etching treatment and the dilute hydrofluoric acid treatment in FIG. 13 (b), or in the plasma etching treatment in FIG. 13 (c) and FIG. 15 (c). An example is shown in which the oxide film on the upper surface of the gate electrode is removed by performing one. In these cases, polycrystalline silicon 316, 317 and 416, 417 may be formed on the gate electrode.

13 to 16, reference numeral 401 is a semiconductor substrate, reference numeral 402 is an element isolation region, reference numeral 403 is a gate insulating film,
Reference numeral 404 is a gate electrode, reference numeral 405 is an insulating material, reference numeral 406.
Is a gate sidewall, reference numeral 407 is a mask material, reference numeral 408 is amorphous silicon, reference numeral 409 is a solid phase epitaxial growth film,
Reference numeral 410 is an amorphous silicon film, reference numeral 412 is a silicon nitride film, reference numeral 414 is a solid phase epitaxial growth film, reference numeral 415.
Indicates an amorphous silicon film, and reference numerals 416 and 417 indicate polycrystalline silicon.

When performing solid phase epitaxial growth, the amorphous silicon films 110, 1 after solid phase growth are used.
At least a part of 15, 210, 215, 310, 315, and 410, 415 may be polycrystallized. For example, when the high-temperature annealing at about 850 ° C. at the time of solid-phase growth, a part of the amorphous region is polycrystalline, also this reference in that case
Examples are applicable.

In addition, in FIGS. 1 to 16, an example has been described in which the shape of the solid phase epitaxial growth film closest to the semiconductor substrate in distance (hereinafter referred to as the first solid phase growth film) differs between pMOS and nMOS. , The shape of the first solid phase growth film is pMOS and nMOS
And the shape of the second solid phase growth film formed on the upper surface is different between pMOS and nMOS.

For example, in FIGS. 17 to 20, after the first solid phase growth film 509 is formed by the same process as in FIG. 1, the same process as in FIG. An example of forming the solid phase growth films 511 and 512 of 2 is shown. Also when the semiconductor device is manufactured by the manufacturing method of FIGS. 17 to 20, the pMOS and the nMOS can have different shapes. Further, in FIGS. 19 and 20, solid phase growth can also be performed on the gate electrode.

Reference numerals 509, 609, 709, 811 in FIGS. 17 to 20 denote the first.
Solid-state growth film of 511,512,611,612,711,712,811,812
Indicates the second solid phase growth film. In addition, FIG. 17 shows FIG.
4 is a MOS transistor, FIG. 18 is a MOS transistor corresponding to FIGS. 5 to 8, FIG. 19 is a MOS transistor corresponding to FIGS. 9 to 12, and FIG. 20 is a MOS transistor corresponding to FIGS. 13 to 16. is there.

The shape after the solid phase epitaxial growth film is formed on the source / drain regions is as shown in FIGS.
(d), FIG. 12 (d), FIG. 16 (d), FIG. 17 (b), FIG. 18 (b), FIG. 19 (b),
It is not limited to the one shown in FIG. For example, nMOS
As for the shape of the solid-phase epitaxial growth film of pMOS and pMOS, at least one of them may have facet at any position of the gate insulating film, the gate electrode oxide film, and the gate sidewall.

Further, the process of forming the nMOS is not limited to the case of flowing the gas containing PH ₃ to deposit the amorphous silicon containing phosphorus as in the present reference example , and the gas containing AsH ₃ is also passed. In general, a gas containing a group V atom, such as a case where amorphous silicon containing As is deposited to form an nMOS region, or a gas containing both PH ₃ and AsH ₃ is flown to deposit amorphous silicon containing P and As. It also includes a case where the nMOS region is formed such that a group V atom is contained in the amorphous silicon by mixing a plurality of kinds of.

The gate insulating film of this reference example may be made of a material other than SiO ₂ , and may be a silicon nitride film, a silicon oxynitride film, or a high dielectric film, such as an oxide film containing Ti, Zr, Ta, or Al.
Also, a laminated film of these may be used.

The shapes of the source and drain regions are
Since it affects the diffusion layer resistance and the gate-source / drain capacitance, it is desirable to set the nMOS and pMOS separately to the optimum shape. Unlike the usual case where the impurity implantation process is performed after solid phase growth of amorphous silicon containing no impurities, in this reference example , the shape of the source / drain is defined by the solid phase growth film thickness in the substrate vertical direction and the horizontal direction. Since the nMOS and pMOS can be independently formed including the shape of solid phase growth, it is possible to form the optimum resistance of the source / drain portion and the parasitic capacitance generated in the gate and the source / drain portion separately for the nMOS and pMOS.

[0054] (Reference Example 2) Step of Reference Example 2 is similar to Example 1, the peripheral region of the portion in contact with the semiconductor substrate of the elevated source / drain diffusion layer of the semiconductor substrate <010> direction I try to face it. This facilitates solid phase growth while contacting the element isolation region and the sidewall of the gate insulating film,
Compared to the conventional structure (solid-phase-grown film thickness around the gate electrode) (structure where the peripheral region of the elevated source / drain diffusion layer in contact with the semiconductor substrate faces the <011> direction of the semiconductor substrate) The layers can be thick.

[0055] The MOS transistor is a reference Example 3 (Reference Example 3) The present invention is characterized in that conductive impurity concentration in the semiconductor substrate is represented by complementary error function.

The manufacturing process of the reference example 3 is almost the same as that of the first and reference examples 2, but an annealing process is added after the solid-phase growth of the conductivity type impurity. For example, in the same chamber where conductive amorphous silicon is deposited, change the gas to be supplied to an inert gas at 750 ° C.
Anneal to some extent to diffuse impurities.

When solid phase growth is performed at a relatively high temperature on a film containing conductive impurities, solid phase growth occurs while the impurities occupy electrically active positions. When solid-phase growth is performed at a relatively low temperature, redistribution of impurities during solid-phase growth hardly occurs. For this reason, an annealing step is required to form the diffusion layer, but since the conductive type impurities diffuse in the solid phase, the conductive type impurity concentration in the semiconductor substrate has a distribution represented by a complementary error function. This is different from the concentration distribution represented by the normal distribution by implantation.

This complementary error function is due to solid phase diffusion, and even when other conductivity type impurities such as arsenic and boron other than phosphorus are used, the impurity concentration in the depth direction in the semiconductor substrate is the complementary error function. Source / drain regions represented by

When the conductivity type impurities are introduced by the implantation, a large number of lattice vacancies are generated and the diffusion layer is deepened by the accelerated diffusion due to the vacancies, but the film containing the conduction type impurities not introduced by the implantation. The solid-phase diffused diffusion layer can form a shallow diffusion layer.

In Reference Example 2 and Reference Example 3 described above,
It is also applicable to a MOS transistor having only one of pMOS and nMOS, and when this reference example is applied to CMOS, at least one of the nMOS and pMOS has the structure of this reference example. If you have.

[0061] MOS transistor is a reference Example 4 (Reference Example 4) The present invention is characterized in that it has a solid phase epitaxial growth elevated source / drain formed by an amorphous silicon film containing a conductive type impurities.

21A to 22C are cross-sectional views showing the manufacturing process of Reference Example 4 . First, as shown in FIG. 21 (a), ginseng
Similar to the first to third reference examples , the element isolation region 902, the gate insulating film 903, and the gate electrode 904 whose upper portion is covered with the insulating material 905 such as a silicon nitride film are formed on the semiconductor substrate 901. Preferably, the gate electrode 904 is oxidized to form an oxide film (not shown), and then an insulating material 906, for example, a silicon nitride film is deposited on the upper surface of the gate electrode 904 by, for example, a CVD device. Note that the insulating material 906 may be deposited on the upper surface of the gate electrode 904 using a sputtering device or a vapor deposition device instead of the CVD device.

Next, an etching method using plasma,
For example, the gate sidewall 906 is formed by processing by RIE (Reactive Ion Etching).

Next, the oxide film 90 is formed by using, for example, dilute hydrofluoric acid.
A process of exposing the source / drain region 3 is performed to expose the surface of the source / drain region of the semiconductor substrate 901 (FIG. 22 (a)). Next, after treating with a gas containing hydrogen, LPC
Silicon-based gas, such as silane (SiH ₄ ) using a VD device
And a gas containing conductivity type impurity atoms is caused to flow in-situ to deposit amorphous silicon 907 containing conductivity type atoms (FIG. 22 (b)).

Further, as shown in FIG. 22 (c), from 500 ° C. to 850
By performing annealing at a temperature of ℃, amorphous silicon on the source / drain regions is selectively subjected to solid phase epitaxial growth (909) using the semiconductor substrate as a seed portion.

Here, the solid phase growth layer is formed by depositing amorphous silicon containing conductive impurities and forming solid phase epitaxial growth a plurality of times, or by adjusting the gas flow rate so that the concentration of the conductive impurity in the film is controlled. It also includes the case of non-uniformity.

In this reference example , the case where the gate side wall 906 is formed is shown. However, as shown in FIGS. 23 and 24, after the gate electrode is processed (FIG. 23 (a)), the gate electrode side wall is oxidized. A step of removing the gate insulating film (FIG. 23 (c)) may be performed before the step of forming the gate sidewall shown in FIG. 21 (b) is performed (FIG. 23 (b)). By such a manufacturing method, the diffusion layer region under the gate insulating film can have a high concentration without increasing the depth of the diffusion layer in the semiconductor substrate.

23 and 24, reference numeral 1001
Is a semiconductor substrate, reference numeral 1002 is an element isolation region, reference numeral 1003 is a gate insulating film, reference numeral 1004 is a gate electrode, reference numerals 1005 and 1006 are insulating materials, and reference numeral 1007 is amorphous silicon.

In addition, in Reference Example 4 described above, an example in which an insulating material is formed on the upper surface of the gate electrode has been described, but FIGS. 25 to 25 are respectively corresponding to FIGS. 21 to 22 and 23 to 24.
As shown in FIGS. 26 and 27, it is not necessary to form an insulating material on the gate electrode when depositing amorphous silicon. However, in this case, solid-phase growth of polycrystalline silicon may occur on the gate electrode.

The last two digits of each reference numeral shown in FIGS. 25 to 27 correspond to the last two digits of each reference numeral shown in FIGS. 21 to 24.

The gas containing a conductivity type atom is a gas containing any one of a P atom, an As atom, and a V group atom or a plurality of these atoms at the time of forming an nMOS, and specifically, for example, PH ₃ , A
It is a gas such as sH ₃ . B atom and III during pMOS formation
It is a gas containing any one of group atoms or a plurality of these atoms, and specifically, a gas such as B ₂ H ₆ . Also,
When forming a CMOS, it can be realized by the same process as in Reference Example 1.

Reference Example 5 FIG. 28 is a sectional view showing a manufacturing process of a MOS transistor according to Reference Example 5 of the present invention. In this reference example , as shown in FIG. 28 (a), the single crystal region containing the conductive type impurity which is solid-phase grown on the source / drain regions is performed through the same procedure as in the reference example 4.
Form 1309. When the deposition temperature of the amorphous silicon containing the conductivity type impurities is relatively low, for example, about 525 ° C., an additional annealing step is required to activate the impurities.

For example, after depositing amorphous silicon containing conductive impurities, annealing is performed at 500 ° C. to 850 ° C. to selectively solidify the amorphous silicon on the source / drain regions using the semiconductor substrate as a seed portion. The elevated source / drain diffusion layers grown by phase epitaxial growth are subsequently subjected to an RTA (rapid thermal annealing) process to activate impurities in the elevated source / drain diffusion layers.

In this reference example , RTA was used to activate the impurities, but the activation annealing is not limited to this.
Moreover, the case where at least one of solid phase growth and activation annealing is repeated a plurality of times is also included.

Further, in this reference example , the case where the activation annealing is performed before the removal step of the region where the solid phase growth is not performed on the single crystal has been described (FIGS. 28 (a) (b)) and FIG. As shown in c) and (d), activation annealing may be performed after the step of removing the region where solid phase growth is not performed on the single crystal.

Reference Example 6 Reference example 6 is the same as the reference example 5 except that
Solid phase epitaxial growth of the amorphous silicon film is performed in the same chamber as the chamber for depositing the amorphous silicon film containing conductive impurities.

For example, with the semiconductor substrate in the source / drain regions exposed, a gas containing silicon and a gas containing conductive impurities are simultaneously flown in an LPCVD furnace at 600 ° C. for 20 seconds to form an amorphous material containing conductive impurities. An elevated source / drain having a film thickness of about 250 nm is obtained by depositing silicon and then changing the supplied gas to nitrogen which is an inert gas and performing annealing for about 2 minutes.

In this reference example , without exposing to the atmosphere,
In particular, since amorphous silicon can be solid-phase grown without dropping to room temperature, the crystallinity of the solid-phase growth film can be improved and the resistance of the elevated source / drain diffusion layer can be reduced. Also, in this reference example ,
The annealing process is performed at 600 ℃, but the annealing temperature is 6
The temperature is not limited to 00 ° C., and annealing may be performed using an RTA device or the like in the same chamber.

Reference Example 7 FIG. 29 is a cross-sectional view showing a manufacturing process of a MOS transistor according to Reference Example 7 of the present invention. This reference example is reference examples 4 to
A feature of the semiconductor device, which has undergone the steps described in Example 6 and is solid-phase grown as shown in FIG. 29 (a), is that the region 1410 that has not been solid-phase grown on a single crystal is removed.

In the semiconductor device having the solid phase epitaxial growth film 1409 and the amorphous silicon film 1410, for example, wet etching treatment is performed for 10 minutes with an etching solution having a composition of hydrofluoric acid: nitric acid: pure water = 1: 50: 75 to obtain an amorphous silicon film. 1410 is etched with good selectivity to the solid phase epitaxial growth film 1409 (FIG. 29 (b)).

The solid phase epitaxial growth layer 1409 may be formed by combining the amorphous silicon containing conductivity type impurities, the solid phase epitaxial growth step, and the etching step of the non-single-crystallized region a plurality of times. included.

The solid phase epitaxial growth layer also includes the case where the amorphous region 1410 after solid phase growth is polycrystallized. For example, the amorphous region is polycrystallized when high-temperature annealing at about 850 ° C. is performed.

Furthermore, in this reference example , amorphous silicon or polycrystalline silicon that has not been single-crystallized is removed by wet etching. However, the removing method is not limited to wet etching, and other methods including plasma etching are also applicable. Dry etching is also included.

Reference Example 8 In Reference Example 8 , the selective etching step of Reference Example 7 is wet etching. According to the applicant's experiment,
It was found that the region where solid phase growth is not selectively performed can be efficiently removed when an etchant containing hydrofluoric acid and nitric acid is used as an etchant for wet etching. For example, it was found that the selection ratio of amorphous silicon / single crystal silicon could be 20 or more when etching was performed for 10 minutes with an etchant of hydrofluoric acid: nitric acid: pure water = 1: 50: 75.

When amorphous silicon containing conductive impurities is deposited on the entire surface and solid phase growth is performed, a step of removing the non-single-crystallized region on the element isolation and the gate side wall is required after solid phase growth. This removal step is based on wet etching.

In the above-mentioned reference example , as an etchant for wet etching, one containing hydrofluoric acid and nitric acid was illustrated, but the material of the etchant is not limited to the above.

Reference Example 9 Reference Example 9 is characterized in that a mixed solution of hydrofluoric acid, nitric acid and pure water is used as an etchant for wet etching.

According to the experiments of the present applicant, when an etchant containing hydrofluoric acid, nitric acid and pure water is used as an etchant for wet etching, it is possible to efficiently remove a region where solid phase growth is not selectively performed. all right.
This etchant has been used for mirror surface treatment of silicon substrates and formation of etch pits since the early LSI industry.
A method of selectively etching amorphous silicon in a system in which an insulating material such as amorphous silicon, single crystal silicon, a silicon nitride film, and a silicon oxide film is mixed has not been conventionally proposed.

Particularly, amorphous silicon is 1 × 10 ¹⁹ / cm
The optimum etchant containing a high concentration of conductive impurities of ³ or more has not been known.

According to the experiment of the applicant, when amorphous silicon contains phosphorus of 1 × 10 ¹⁹ / cm ³ or more, amorphous silicon, single crystal silicon, silicon oxide film, and silicon nitride film are mixed. In this system, when etching is performed for 10 minutes with an etchant of hydrofluoric acid (50%): nitric acid (70%): pure water = 1: 50: 75, the etching rate of amorphous silicon is 20 or more compared to other substances. It was found that the selection ratio could be 20 or more.

It was thought that the etching mechanism of single crystal silicon by hydrofluoric acid and nitric acid was due to the oxidation process by nitric acid and its removal process by hydrofluoric acid. Etching of amorphous silicon containing impurities and its mechanism are not clear, and there is a 20% difference between single-crystal silicon containing solid-phase growth and high concentration of conductive impurities and the amorphous silicon.
It was clarified for the first time that the selection ratio can be obtained by the experiment of the applicant.

In the present reference example , the composition ratio is hydrofluoric acid (50
%): Nitric acid (70%): pure water = 1:50:75 has been described, but the composition ratio is not limited to the above ratio.

Reference Example 10 Reference Example 10 uses a mixed solution of hydrofluoric acid, nitric acid, and acetic acid as an etchant for wet etching.

According to the experiment of the applicant, the amorphous silicon
For example, phosphorus is 1 × 10 in the con¹⁹/cm ³Included above
In case of amorphous silicon, single crystal silicon, silicon
Example in a system in which con oxide film and silicon nitride film are mixed
For example, hydrofluoric acid (50%): nitric acid (70%): acetic acid = 1:50:75
Amorpha after etching for 5 minutes
The etching rate of silicon is 20 or more compared to other materials
It is clear that the selection ratio can be 20 or more.

Reference Example 11 Reference Example 11 is characterized in that the hydrofluoric acid / nitric acid molar ratio is 2/9 or less.

The chemical formula for etching single crystal silicon with a mixed solution of hydrofluoric acid and nitric acid is considered to be 3Si + 4HNO ₃ + 18HF → 3H ₂ SiF ₆ + 4NO + 8H ₂ O.

According to the same experiment, the inventor of the present invention, when the hydrofluoric acid / nitric acid molar ratio was 2/9 or less, amorphous silicon containing a high concentration of conductive impurities of 1 × 10 ¹⁹ / cm ³ or more, single crystal It has been found that amorphous silicon can be selectively removed in a system in which silicon and an insulating material including a silicon nitride film and a silicon oxide film are mixed. For example, when an etching solution having a composition of hydrofluoric acid: nitric acid: pure water = 1: 50: 75 is used, amorphous silicon can be removed with a selection ratio of 20 or more.

FIG. 30 is a diagram showing the ternary composition ratio of the etching solution used in Reference Example 11 of the present invention. Normally used hydrofluoric acid is 50% and nitric acid is 70%, but the range in which the amorphous silicon can be selectively etched well is that the composition ratio of the hatched portion in FIG. It turned out by experiment. Therefore, it is desirable to select the composition ratio of the shaded portion in FIG. 30 as the etchant.

Reference Example 12 In Reference Example 12 , the selective etching step of Reference Example 7 includes an oxidizing step and a removing step thereof. After depositing amorphous silicon containing conductive impurities in the LPCVD furnace,
The source / drain regions are solid-phase grown into a single crystal between 00 ° C and 850 ° C, the amorphous silicon remaining on the insulating film is oxidized in an atmosphere containing oxygen, and the source / drain regions of the source / drain regions are processed by diluted hydrofluoric acid treatment. The oxide film is removed. Thereby, selective etching can be performed relatively easily.

[0100] (First Embodiment) FIGS. 31 and 32 are sectional views showing a manufacturing process of the MOS transistor is a first embodiment of the present invention. The present embodiment is characterized in that carbon is used as a mask material when forming a CMOS in Reference Examples 1 to 12 . For example, as in the case of Reference Example 1 , a carbon film 1507 is formed on the entire surface of a semiconductor substrate having a gate electrode region formed as shown in FIG.

Then, a lithography process is performed (see FIG.
(b)), the solid phase growth assumed region, in this case the nMOS region, is etched with high selectivity to the silicon oxide film by an etching device using plasma, and processed into a shape as shown in FIG. 31 (c). However, the resist is removed with a solution containing hydrogen peroxide.

A solid phase growth step is performed as shown in FIG. 31 (d) to oxidize a solid phase growth film (not shown), and then the carbon film 1507 is removed by plasma etching (FIG. 31 (e)).

Next, the same steps as described above are performed for the pMOS region to form the carbon film 1512 (FIG. 32 (a)), and then the reference.
As in Example 1 , an elevated source / drain structure is obtained (FIG. 32 (d)).

However, the above-mentioned carbon mask material is nMOS.
It may be used when forming at least one of a pMOS and a pMOS.

[0105] (Second Embodiment) FIG. 33 is a sectional view showing a manufacturing process of the MOS transistor which is a second embodiment of the present invention. Reference Example 1 to Reference Example 1
2. Elevated device formed according to the first embodiment
In the source / drain structure (FIG. 33A), titanium 1612 which is a refractory metal film is deposited. 600 ℃, 20 seconds,
Heat treatment is performed to form a titanium silicide film 1613, and unreacted titanium is selectively removed with a sulfuric acid-based solution.

The silicide of the present invention is not limited to titanium silicide, but Co, Ni, Zr, V, and Hf may be deposited instead of titanium in the deposition step to form the silicide. When the gate electrode is exposed, the present invention can be applied to the case where the gate electrode is also silicidized.

In the silicide for the elevated source / drain, since the silicide interface is separated from the pn junction, leakage can be reduced, and the low resistance in the source / drain, which is a characteristic of the silicide, can be achieved. The electrical characteristics are improved.

[0108]

As described in detail above, according to the present invention, the n-type MOS transistor and the p-type MOS transistor are formed by forming the source / drain regions by solid phase epitaxial growth.
Since you as the shape and thickness of the source / drain regions can be set individually by the transistors, together with possible reduce the resistance of the source / drain regions, the parasitic capacitance can be reduced, a semiconductor device having excellent electrical characteristics can give et al is, As mask material
Since carbon is used, selective etching is performed accurately
be able to.

[0109]

[0110]

[0111]

[0112]

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of Reference Example 1 .

FIG. 2 is a sectional view showing a manufacturing process that follows FIG. 1;

FIG. 3 is a sectional view showing a manufacturing process that follows FIG. 2;

FIG. 4 is a sectional view showing a manufacturing process that follows FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing process when a gate sidewall is not formed.

FIG. 6 is a sectional view showing a manufacturing process that follows FIG. 5;

FIG. 7 is a sectional view showing a manufacturing process that follows FIG. 6;

FIG. 8 is a cross-sectional view showing the manufacturing process following FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process when the upper surface of the gate electrode is not covered with an insulating material.

FIG. 10 is a cross-sectional view showing the manufacturing process when the upper surface of the gate electrode is not covered with an insulating material, following FIG. 9;

11 is a cross-sectional view showing the manufacturing process when the upper surface of the gate electrode is not covered with an insulating material, following FIG. 10;

FIG. 12 is a cross-sectional view showing the manufacturing process when the upper surface of the gate electrode is not covered with an insulating material, following FIG. 11;

FIG. 13 is a cross-sectional view showing the manufacturing process when the oxide film on the upper surface of the gate electrode is removed by plasma etching.

FIG. 14 is a sectional view showing a manufacturing process that follows FIG. 13;

FIG. 15 is a sectional view showing the manufacturing process that follows FIG. 14;

16 is a sectional view showing a manufacturing process that follows FIG. 15;

FIG. 17 is a cross-sectional view showing a manufacturing process when a second solid phase growth layer is formed.

FIG. 18 is a sectional view showing the manufacturing process that follows FIG. 17;

FIG. 19 is a sectional view showing a manufacturing process that follows FIG. 18;

20 is a sectional view showing a manufacturing process that follows FIG. 19; FIG.

FIG. 21 is a cross-sectional view showing the manufacturing process of Reference Example 4 .

22 is a sectional view showing the manufacturing process that follows FIG. 21. FIG.

FIG. 23 is a cross-sectional view showing a manufacturing process of removing the gate insulating film before the gate sidewall forming process.

FIG. 24 is a cross-sectional view showing the manufacturing process that follows FIG. 23.

FIG. 25 is a cross-sectional view showing the manufacturing process when an insulating material is not formed on the gate electrode.

FIG. 26 is a cross-sectional view showing the manufacturing process that follows FIG. 25.

FIG. 27 is a cross-sectional view showing the manufacturing process when an insulating material is not formed on the gate electrode.

FIG. 28 is a cross-sectional view showing the manufacturing process of the MOS transistor according to the fifth reference example .

29 is a cross-sectional view showing the manufacturing process of Reference Example 7. FIG.

FIG. 30 is a diagram showing a three-dimensional composition ratio of the etching solution used in Reference Example 11 .

FIG. 31 is a cross-sectional view showing the manufacturing process of the first embodiment of the present invention.

32 is a sectional view showing the manufacturing process that follows FIG. 31. FIG.

FIG. 33 is a cross-sectional view showing the manufacturing process of the second embodiment of the present invention.

[Explanation of symbols]

101 semiconductor substrate 102 element isolation region 103 gate insulating film 104 gate electrode 105 Insulating material 106 gate sidewall 107 Mask material 108 amorphous silicon 109 Epitaxial growth film 110 amorphous silicon film 112 Silicon nitride film 113 amorphous silicon 114 Solid phase epitaxial growth film 115 Amorphous silicon film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/78 (56) References JP-A-9-148535 (JP, A) JP-A-8-18049 (JP, A) Special Kaihei 8-153688 (JP, A) JP 4-167529 (JP, A) JP 10-12879 (JP, A) JP 8-167718 (JP, A) JP 8-37300 ( JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/085-27/092 H01L 21/8234-21/8238 H01L 29/78

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a MOS transistor formed on a semiconductor substrate, the method comprising: depositing an amorphous silicon film containing conductive impurities on an upper surface of the semiconductor substrate; The amorphous silicon film is grown by solid phase epitaxial growth while inheriting the crystal orientation of the source / drain diffusion layer so that the upper surface of the source / drain region is higher than the interface between the gate insulating film and the semiconductor substrate. And a step of forming a CMOS composed of an n-type MOS transistor and a p-type MOS transistor each having the elevated source / drain diffusion layers, the n-type MOS transistor and the p-type Form the amorphous silicon film on one side of the MOS transistor Prior to forming, the n-type MOS transistor region and p-type M
Forming a carbon mask material covering the OS transistor region,
Etching away the carbon mask material over the MOS transistor region forming the amorphous silicon film,
A method of manufacturing a semiconductor device, comprising forming a carbon mask covering the other MOS transistor region of the n-type MOS transistor and the p-type MOS transistor. 2. The n-type MOS transistor and the p-type
Elevated source / source of MOS transistor
The method for manufacturing a semiconductor device according to claim 1, wherein the shape and the thickness of the rain diffusion layer are individually set. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of selectively removing amorphous silicon or polycrystalline silicon which has not been single-crystallized by wet etching. 4. A step of forming a refractory metal layer on the upper surface of the elevated source / drain diffusion layer, and a step of converting the refractory metal layer into a refractory silicide layer by heat treatment. The method for manufacturing a semiconductor device according to claim 1, wherein