JP3490314B2 - Multi-chip type semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention generally relates to a multi-chip module (MCM) and a multi-chip package (M
The present invention also relates to a multi-chip type semiconductor device, also referred to as CP), in which a plurality of semiconductor chips are arranged side by side on a substrate in order to reduce the size and weight of an electronic device.
More specifically, the present invention relates to a ball grid array (hereinafter, referred to as appropriate) for electrically connecting a semiconductor chip and the outside.
The present invention relates to a BGA type multi-chip type semiconductor device having a BGA) .

[0002]

2. Description of the Related Art Conventionally, a memory chip has a SOP (Small O
It was generally mounted in a package such as utline Package) or QFP (Quad Flat Package).

In recent years, mobile phones and portable information devices (PD
A: Portable devices such as Personal Digital Assistants) and electronic still cameras (digital cameras) are in widespread use. These portable devices are equipped with a memory chip for storing data, and while the memory chip is required to have a large capacity, it is required to make the package thin and compact. .

Therefore, in recent years, as a semiconductor device capable of further miniaturizing a package of a memory chip, CS has been used.
P (Chip Size Package) type semiconductor devices and high density multi-chip type semiconductor devices have been used.
Particularly, in the CSP type semiconductor device, a thin substrate of about 0.1 mm is used as a substrate on which a memory chip is mounted in order to reduce the thickness.

Further, recently, since it is easy to narrow the pitch of the external connection terminals, a plurality of semiconductor chips are mounted on the front surface side of the substrate, and a plurality of spherical bump electrodes as external connection terminals are provided on the back surface of the substrate. BGA type semiconductor devices on the side have been proposed, and BGA type multi-chip type semiconductor devices have also been proposed.

However, since the BGA type multi-chip type semiconductor device has a large area, it is much more easily warped than a semiconductor device having a single semiconductor chip.
Therefore, conventionally, when ceramic is used as the material of the substrate, or when resin is used as the material of the substrate, the thickness of the substrate is relatively large, for example, 0.5 mm or more.

A semiconductor device mounted on a portable device is lightweight and
Since thinness is essential, when mounting a BGA type multi-chip type semiconductor device on a mobile device, the thickness of the substrate must be CSP.
It is required to reduce the thickness to 0.2 mm or less, which is the same level as in the case of the semiconductor device of the type.

[0008]

However, since the substrate used for the BGA type multi-chip type semiconductor device has a relatively large area so that a plurality of semiconductor chips can be mounted side by side in a plane, the substrate has a large thickness. If it is made extremely thin, such as 0.2 mm or less, the following problems are brought about.

First, when the thickness of the substrate made of ceramic is 0.2 mm or less, the substrate is easily broken and the handling becomes difficult. Further, in the case of a substrate made of an insulating resin material such as polyimide, polyester, glass epoxy, etc., even if the thickness of the substrate is 0.2 mm or less, the flexibility is high and the problem that it is easily broken does not occur.

However, the substrates made of these insulating resin materials have low rigidity and are weak against bending stress. for that reason,
In the conventional BGA type multi-chip type semiconductor device, if the thickness of the substrate is 0.2 mm or less, warpage is likely to occur.
According to the consideration of the inventor of the present application, this is the conventional BGA.
This is because the semiconductor chips are not arranged on the center line of the substrate in the multi-chip type semiconductor device of the type in which the semiconductor chips are aligned and arranged or only the wiring layout is taken into consideration. Do you get it.

Hereinafter, this point will be described in more detail with reference to specific examples shown in FIGS. Conventional B
As the GA type multi-chip type semiconductor device, for example,
As shown in FIGS. 6 and 7, four semiconductor chips 1 are arranged in two rows on the surface of a rectangular substrate 2,
There is known a multi-chip type semiconductor device 10 or 10 'in which a BGA 6 is provided as an external connection terminal on the back surface of the substrate 2.

In the multi-chip type semiconductor devices 10 and 10 ', although not shown, a wiring layer (conductor layer) formed by patterning a conductor such as copper is formed on the substrate 2, and the BGA 6 is It is electrically connected to the wiring layer. Further, in the multi-chip type semiconductor device 10, each semiconductor chip 1 is electrically connected to the wiring layer of the substrate 2 via the thin wire 3, and the semiconductor chip 1, the substrate 2, and the thin wire 3 are entirely covered by the sealing resin 4. Is covered. on the other hand,
In the multi-chip type semiconductor device 10 ′, each semiconductor chip 1 is electrically connected to the wiring layer of the substrate 2 via the bump 5, and the bump 5 is covered with the sealing resin 4.

Multi-chip type semiconductor devices 10 and 1
In 0 ′, since the semiconductor chip 1 is not arranged on the center line X and the center line Y of the substrate 2, the semiconductor chip 1 is not arranged near the center line X and the center line Y of the substrate 2. There is only a part. Therefore, particularly when the substrate 2 made of an insulating resin having a thickness of 0.2 mm or less is used, the portion near the center line X and the portion near the center line Y of the substrate 2 have low rigidity and are easily bent by a small external stress.

As a result, the multi-chip type semiconductor device 10
And 10 ', as shown in FIGS. 6 (c) and 7 (c), the center line Y direction (direction shown by an arrow in FIGS. 6 (c) and 7 (c)) is apt to warp, and Figure 6
As shown in (d) and FIG. 7 (d), a warp in the center line X direction (direction shown by an arrow in FIG. 6 (d) and FIG. 7 (d)) is also likely to occur.

Further, as a conventional BGA type multi-chip type semiconductor device, as shown in FIGS. 8 and 9, four semiconductor chips 1 are arranged in a line on the surface of a rectangular substrate 2, Multi-chip type semiconductor devices 20 and 20 'in which a BGA 6 is provided as an external connection terminal on the back surface of the substrate 2 are also known.

The multi-chip type semiconductor device 20 is
It is the same as the multi-chip type semiconductor device 10 except that the arrangement of the semiconductor chip 1 is different. Similarly, the multi-chip type semiconductor device 20 'is the same as the multi-chip type semiconductor device 10' except that the arrangement of the semiconductor chips 1 is different.

Multi-chip type semiconductor devices 20 and 2
In 0 ′, since the semiconductor chip 1 is not arranged on the center line X of the substrate 2, there is only the portion of the substrate 2 where the semiconductor chip 1 is not arranged in the vicinity of the center line X of the substrate 2. Therefore, particularly when the substrate 2 made of an insulating resin having a thickness of 0.2 mm or less is used, the portion near the center line X of the substrate 2 has low rigidity and is easily bent by a small external stress.

As a result, the multi-chip type semiconductor device 20
8 and 20 ', as shown in FIGS. 8 (c) and 9 (c), a warp in the center line Y direction (directions indicated by arrows in FIGS. 8 (c) and 9 (c)) is likely to occur.

Further, in the multi-chip type semiconductor devices 20 and 20 ', since the semiconductor chips 1 are arranged in a line along the direction of the center line Y of the substrate 2, the length of the entire device along the direction of the center line Y is increased. Saga multi-chip type semiconductor device 1
Longer than 0 and 10 '. Therefore, the warp in the center line Y direction is more likely to occur.

A conventional BGA type multi-chip type semiconductor device 1 in which the semiconductor chips 1 are aligned and arranged in this manner.
With 0, 10 ', 20, and 20', warp is likely to occur in the central portion of the substrate 2. When the substrate 2 is warped, the flatness of the BGA 6, which is an electrode portion for connecting the multi-chip semiconductor device to the outside, deteriorates. Therefore, when the multi-chip type semiconductor device is connected to the external semiconductor device, for example, the mother board forming the circuit of the final device by the BGA 6, there is a problem that a connection failure is likely to occur.

The present invention has been made in view of the above conventional problems.
And its purpose is multi-chip with BGA
Type semiconductor device is less likely to warp and
Multi-chip type semiconductor device with high reliability of electrical connection
To provide.

[0022]

In order to achieve the above-mentioned object, the inventor of the present invention has made earnest studies on a BGA type multi-chip type semiconductor device which is hard to warp. It has been found that it is effective to prevent warpage by consciously devising the chip and providing it in a specific arrangement.

[0023] The present onset Ming Ma Ruchichippu type semiconductor device, in order to solve the above problems, to the substrate of a quadrilateral comprising a conductor layer, the three or more semiconductor chips on one side of the substrate is planarly aligned electrical conductor layer together are arranged connected, multi-ball grid array of electrodes for connecting the conductor layer to an external electrical formed on the other surface of the substrate A chip-type semiconductor device, wherein the semiconductor chip group connects two midpoints of opposite sides of a substrate.
At least one semiconductor chip is arranged so as to straddle each of the two center lines.
Is placed between the adjacent semiconductor chips and the substrate.
If you draw all parallel straight lines, at least one of these straight lines
While passing through other semiconductor chips,
The above semiconductor chips are separated from each other
It is characterized in that that.

According to the above structure, in the semiconductor chip, at least one semiconductor chip extends over each of two center lines (hereinafter, appropriately referred to as “opposite side center lines”) connecting midpoints of opposite sides of the substrate. Are arranged as follows. In other words, the semiconductor chip is arranged so that the two opposite center lines of the substrate pass through the inside of the semiconductor chip.

In general, a semiconductor chip mainly composed of silicon and having a high bending elasticity is arranged so that at least one semiconductor chip straddles each of the two opposite side centerlines of the substrate in this manner, so that a warp is likely to occur. A thin and flexible portion only on the substrate is reduced from the center line of the two opposite sides of the substrate, and the center line of the two opposite sides of the substrate is reinforced by the semiconductor chip. As a result, the rigidity of the multi-chip semiconductor device on the center lines of the two opposite sides of the substrate is increased, so that the warp of the multi-chip semiconductor device is reduced. Therefore, the Borg which is the electrode section for electrical connection with the outside
The flatness of the lid array is improved. As a result, the reliability of electrical connection between the semiconductor device and an external component, for example, a peripheral component such as a motherboard that constitutes the final device is improved.

Further , according to the above configuration, electrical connection with the outside is possible.
Multiple electrodes for connection as a ball grid array
As compared to QFP that uses a lead frame,
Easy to increase the number of pins per unit area, and mounting surface
The product can be reduced.

In the present specification, "ball grip"
"Dreary" (or "BGA") means at least four
The above spherical bump electrodes are arranged in a grid on the same plane.
Refers to the electrode part for electrical connection with the outside arranged in a line
I shall.

Further, in the gap between two adjacent semiconductor chips, the semiconductor device is composed of only the substrate and is thin and easily bent, so that warpage is likely to occur. However, according to the above configuration, since another semiconductor chip is arranged on the extension line of the gap, the warp in the gap between the semiconductor chips can be reduced. As a result, the flatness of the ball grid array
Can be improved to al, a semiconductor device, an external component, for example, the reliability of electrical connection between the peripheral components such as a motherboard which constitutes the final device can be further improved.

Further , the multi-chip type semiconductor device of the present invention
Is a semiconductor chip of an insulating substrate.
All straight lines passing through the center on the side face are at least 1
It should be arranged so that it passes through two semiconductor chips.
More preferable. This allows for all directions in the center
The warpage is reduced and the flatness of the ball grid array is further improved.
Improve to. As a result, semiconductor devices and external parts, such as
For example, peripheral parts such as motherboards that make up the final device
The reliability of the electrical connection between and is further improved.

Further , the multi-chip type semiconductor device of the present invention
Then, it is preferable that the above-mentioned substrate is a substrate provided with a conductor layer on an insulating substrate made of at least one resin material selected from the group consisting of polyimide, polyester, and glass epoxy.

According to the above structure, since the substrate is made of a highly flexible resin material, the multi-chip type semiconductor device is easy to handle even if the thickness of the substrate is 0.2 mm or less and the substrate is not easily damaged. Can be provided.

Further , the multi-chip type semiconductor device of the present invention
Then, the thickness of the substrate is preferably in the range of 0.1 to 0.2 mm.

According to the above structure, it is possible to provide a thin multi-chip type semiconductor device in which the substrate is not easily damaged and is easy to handle.

In the multi-chip type semiconductor device of the present invention, the method of electrical connection between the semiconductor chip and the conductor layer may be a wire bonding (wire bonding) method using thin wires (wires), or flipping. Chip (F
The method C) may be used, or a method in which a wire bond method and a flip chip method are mixed may be used.

Further, in the multi-chip type semiconductor device of the present invention, at least one surface mounting selected from the group consisting of a capacitor, a coil and a resistor is provided in the empty area of the insulating substrate where the semiconductor chip is not arranged. It is preferable to mount one or a plurality of die passive components together. As a result, the area of the motherboard can be reduced. Therefore, the area of the final product when the semiconductor device is connected to the motherboard to form the final product can be reduced.

Further, a stacked semiconductor chip formed by stacking a plurality of semiconductor chips in the thickness direction may be mounted. Thereby, the area of the multi-chip type semiconductor device can be reduced.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION A surface mount type multi-chip type semiconductor device in which four semiconductor chips are mounted on the same substrate (hereinafter, simply referred to as a semiconductor device in the [embodiment of the invention]) will be described below. It will be described with reference to the drawings.

The following will describe one embodiment of the present invention with reference to FIG. In the semiconductor device of this embodiment, as shown in FIG. 1, four rectangular semiconductor chips 1 are arranged in a plane on the surface of the substrate 2 with respect to a square substrate 2 provided with a wiring layer (conductor layer). A BGA (ball grid array) 6 is formed on the back surface of the substrate 2 and is electrically connected to the wiring layer and is composed of a plurality of electrodes for electrically connecting the wiring layer to the outside.
Then, the semiconductor chip 1 is configured such that at least one semiconductor chip 1 straddles each of two center lines X and Y connecting midpoints of opposite sides of the substrate 2 and between two adjacent semiconductor chips 1. All straight lines A to D parallel to the substrate 2 are arranged so as to pass through the semiconductor chip 1.

The semiconductor chips 1 are arranged at the four corners of the substrate 2 so that a square empty region (a region where the semiconductor chip 1 is not arranged) is formed in the central portion of the substrate 2, and the semiconductor chip 1 has a so-called tongue-like shape. Has become. Explaining on the plane of FIG. 1, the upper left semiconductor chip 1 is arranged such that its long side is parallel to the center line Y of the substrate 2 and the lower end portion of the semiconductor chip 1 passes through the center line X of the substrate 2. , The upper right and lower left semiconductor chips 1 can be rotated by 90 ° around the center of the substrate 2 (the intersection of the center line X and the center line Y).
Is placed so that it completely overlaps with the semiconductor chip 1 on the lower right.
Are arranged so as to be point-symmetrical to the upper left semiconductor chip 1 with respect to the center of the substrate 2.

The substrate 2 is a package substrate in which a conductor such as copper is patterned as a wiring layer on a thin insulating substrate made of an insulating resin such as polyimide, polyester and glass epoxy. The glass epoxy is a fiber reinforced plastic composed of an epoxy resin (including a modified epoxy resin) and a glass cloth. For example, the glass epoxy is manufactured by impregnating the glass cloth with the epoxy resin and then curing the glass cloth.

The substrate 2 is composed of, for example, a thin insulating substrate having a thickness of about 0.1 mm and a wiring layer made of a thin conductor having a thickness of about 0.05 mm, and the total thickness is about 0.15 mm. The thickness of the substrate 2 is preferably 0.1 mm or more so as to obtain sufficient strength to prevent damage, but is preferably 0.2 mm or less in consideration of thinning of the semiconductor device, and 0 The range of 0.1 mm to 0.2 mm is more preferable. The semiconductor device of this embodiment is a CSP.
In the case of being mixedly mounted on a mother board with a semiconductor device, the thickness of the substrate 2 is particularly preferably about 0.2 mm.
The dimension of the substrate 2 in the plane direction is several tens of times or more the thickness, for example, a dimension close to 10 mm × 10 mm square or 10 mm
The dimensions are 10 mm square or more.

The semiconductor chip 1 has a semiconductor circuit formed on the front surface of a silicon substrate and electrode pads provided on the back surface of the surface on which the semiconductor circuit is formed. It is about 0.5 mm.

The semiconductor chip 1 is particularly a DRAM.
(Dynamic Random Access Memory), SRAM (Static Ra
ndom Access Memory), MROM (Mask Read Only Memo)
ry), a memory such as a flash memory is preferably used. Moreover, different types of memories may be used as the semiconductor chip 1, and thus a composite memory semiconductor device can be obtained. Further, the memory and another semiconductor chip such as a microcomputer (CPU), a gate array, and a standard cell may be mounted in combination, whereby a combined semiconductor device can be obtained.

The semiconductor chip 1 is attached on the surface of the substrate 2 with the surface on which the semiconductor circuit is formed facing upward with an adhesive or the like, and the electrode pads of the semiconductor chip 1 have wiring layers (not shown) of the substrate 2. ) Is electrically connected by a thin wire 3. Therefore, the electrical connection between the electrode pad of the semiconductor chip 1 and the wiring layer of the substrate 2 is of the wire bond type.

The thin wire 3 is a conductor wire made of a conductor such as gold or aluminum and having a wire diameter of about 0.03 mm. The semiconductor chip 1, the substrate 2, and the thin wire 3 are not deteriorated due to chemical deterioration due to the external environment or physical deterioration such as scratches.
In order to protect the circuit formation surface of the above, it is protected by a sealing resin 4 such as an epoxy resin.

The BGA 6 is composed of a spherical bump electrode such as a solder ball, and functions as an external connection terminal (electrode) for electrically connecting the wiring layer of the substrate 2 to an external semiconductor device (for example, a mother board). is there. BGA6
Is formed below the wiring layer on the back surface of the substrate 2 with respect to the semiconductor chip 1 so as to contact the wiring layer.

As described above, the substrate 2 is mainly made of an insulating resin, and the dimension in the thickness direction is extremely smaller than the dimension in the plane direction. Therefore, the substrate 2 alone has a low rigidity against bending and a small external force. Bending occurs.

However, in the semiconductor device of this embodiment, since the semiconductor chip 1 and the substrate 2 are securely fixed to each other with an adhesive, the substrate 2 is supported by the semiconductor chip 1. Therefore, the rigidity of the semiconductor device in the portion where the semiconductor chip 1 is mounted on the substrate 2 is
The rigidity of the semiconductor chip 1 is added to the rigidity of. The semiconductor chip 1 is mainly made of silicon having high bending elasticity and has a thickness of 0.3 to 0.5 mm.
It is relatively thick and has high rigidity against bending. Therefore, the semiconductor device in the portion where the semiconductor chip 1 is mounted on the substrate 2 is less likely to bend due to the semiconductor chip 1.

Further, in the semiconductor device of this embodiment, the substrate 2 is formed so that a thin portion consisting only of the substrate 2 does not exist continuously along the center line X and the center line Y of the substrate 2. Two semiconductor chips 1 are arranged on the center lines X and Y of the two semiconductor chips 1, respectively. As a result, the semiconductor device is less likely to bend in the vicinity of the center line X and the center line Y of the substrate 2 where the warp is likely to occur, and the warp of the semiconductor device is reduced. Therefore, the flatness of the BGA 6, which is an electrode portion for connection with the outside, is improved. For example, when the external dimensions of the substrate 2 are 15 mm square or less, BG
The flatness of A6 can be 0.1 mm or less. As a result, the reliability of the electrical connection between the semiconductor device and external components, for example, peripheral components such as a motherboard constituting the final device is improved.

Further, in the gap between two adjacent semiconductor chips 1, since the semiconductor device is composed of only the substrate 2, warpage is likely to occur. However, in the semiconductor device of this embodiment, the semiconductor chip 1 is composed of two adjacent semiconductor chips 1.
When all the straight lines A to D parallel to the substrate 2 are drawn through
The straight lines A to D are arranged so as to pass through one semiconductor chip 1, respectively. As a result, the warp of the substrate 2 between two adjacent semiconductor chips 1 can be reduced. As a result, the flatness of the BGA 6 can be further improved,
It is possible to further improve the reliability of the electrical connection between the semiconductor device and an external component, for example, a peripheral component such as a motherboard that constitutes the final device.

Further , the semiconductor device of this embodiment is shown in FIG.
It may be configured as shown in. This semiconductor device is the same as the semiconductor device shown in FIG. 1 except that the method of electrically connecting the semiconductor chip 1 and the substrate 2 is different. In the semiconductor device of FIG. 2 , instead of the thin wire 3 in the configuration shown in FIG. 1, bumps (projections) 5 made of a conductor such as gold or solder are provided on the electrodes on the circuit formation surface of the semiconductor chip 1. The electrical connection between the electrode pad of the semiconductor chip 1 and the wiring layer of the substrate 2 formed in the above is realized by the flip chip bonding method via the bump 5. Further, in the semiconductor device of FIG. 2 , the bumps 5 are not covered with the sealing resin 4 but are covered with the sealing resin 4.
I try to cover only.

Also in the semiconductor device of FIG . 2 , since the semiconductor chip 1 is located on the center line X and the center line Y of the semiconductor device which is particularly susceptible to warpage, warpage is unlikely to occur.
Therefore, the BGA6 which is the electrode part for connection to the outside
Improves the flatness of. As a result, the reliability of the electrical connection between the semiconductor device and external components, for example, peripheral components such as a motherboard constituting the final device is improved.

When the semiconductor device shown in FIG. 2 is compared with the semiconductor device shown in FIG. 1, the structure shown in FIG. 1 is covered with the sealing resin 4 in order to protect the thin wires 3, so that warpage occurs. Hateful. However, even in the configuration of FIG. 2, if the sealing resin 4 is formed so as to cover the entire structure , warpage is unlikely to occur to the same extent as in the configuration of FIG .

Further, the semiconductor device of this embodiment is shown in FIG.
It may be configured as shown in. This semiconductor device is shown in FIG.
Only the arrangement of the semiconductor chip 1 in the semiconductor device shown in is changed. In the semiconductor device shown in FIG.
The semiconductor chip 1 is arranged so that at least one semiconductor chip 1 straddles each of two center lines X and Y connecting midpoints of opposite sides of the substrate 2. Explaining on the plane of FIG. 3, the two rectangular semiconductor chips 1 have their long sides parallel to the center line X, and the center thereof is the center line Y.
Are arranged at the upper and lower ends of the substrate 2 so that
Between the semiconductor chips 1 arranged at the upper end portion and the lower end portion of the substrate 2, the other two rectangular semiconductor chips 1 have their long sides parallel to the center line Y, and the center of the center line X is the center line X. They are arranged on the substrate 2 side by side so as to pass through.

Also in the arrangement of FIG . 3 , since the semiconductor chip 1 is located on the center line X and the center line Y of the semiconductor device which is particularly susceptible to warpage, warpage is unlikely to occur. Therefore, the flatness of the BGA 6, which is an electrode portion for connection with the outside, is improved. As a result, the semiconductor device and external parts,
For example, the reliability of electrical connection with peripheral components such as a mother board constituting the final device is improved.

In the semiconductor device of FIG . 3 , when all straight lines parallel to the substrate 2 penetrating the gap between the semiconductor chips 1 adjacent to each other, that is, the straight line E, the straight line F, and the center line Y are drawn. , There are two semiconductor chips 1 on the center line Y passing between the two semiconductor chips 1 in the center,
The semiconductor chip 1 is on the straight line E passing between the upper semiconductor chip 1 and the two central semiconductor chips 1 and on the straight line F passing between the lower semiconductor chip 1 and the two central semiconductor chips 1. not exist. Therefore, comparing the semiconductor device of FIG . 3 with the semiconductor device of FIG. 1 , in the configuration of FIG. 3, the portions along the straight lines E and F are easily bent,
Since the warp in the center line Y direction is likely to occur, the configuration of FIG. 1 is more preferable.

Further, the semiconductor device of this embodiment is shown in FIG.
It may be configured as shown in. This semiconductor device is the same as the semiconductor device shown in FIG. 3 except that the method of electrically connecting the semiconductor chip 1 and the substrate 2 is different. Shown in Figure 4
In the semiconductor device, a bump (projection) 5 made of a conductor such as gold or solder is used instead of the thin wire 3 in the configuration shown in FIG.
Are formed on the electrodes on the circuit forming surface of the semiconductor chip 1, and the electrical connection between the electrode pads of the semiconductor chip 1 and the wiring layer of the substrate 2 is realized by the flip chip bonding method via the bumps 5. In addition, in the semiconductor device of FIG.
Instead of covering the whole with the sealing resin 4, only the bumps 5 are covered with the sealing resin 4.

Also in the semiconductor device of FIG . 4 , since the semiconductor chip 1 is located on the center line X and the center line Y of the semiconductor device in which warpage is particularly likely to occur, warpage is unlikely to occur.
Therefore, the BGA6 which is the electrode part for connection to the outside
Improves the flatness of. As a result, the reliability of the electrical connection between the semiconductor device and external components, for example, peripheral components such as a motherboard constituting the final device is improved.

It should be noted, when compared with the semiconductor device of FIG. 3 the semiconductor device of FIG. 4, the minute the direction of arrangement of FIG. 3 covers the whole sealing resin 4 in order to protect the thin line 3, warped Hateful. However, even in the configuration of FIG. 4, if the sealing resin 4 is formed so as to cover the entire structure , warpage is unlikely to occur to the same extent as in the configuration of FIG .

Further, the semiconductor device of this embodiment is shown in FIG.
It may be configured as shown in. This semiconductor device is shown in FIG.
4 is the same as the semiconductor device of FIG. 4 except that the shape of each semiconductor chip 1 in the configuration of FIG. 4 is changed to a square.

Also in the semiconductor device of FIG . 5 , since the semiconductor chip 1 is located on the center line X and the center line Y of the semiconductor device which is particularly susceptible to warpage, the warpage is unlikely to occur.
Therefore, the BGA6 which is the electrode part for connection to the outside
Improves the flatness of. As a result, the reliability of the electrical connection between the semiconductor device and external components, for example, peripheral components such as a motherboard constituting the final device is improved.

In the semiconductor device of FIG . 5 , center lines X and Y are used.
Since the semiconductor chip 1 is arranged on the upper side, the semiconductor chip 1 is not closest packed, and there is an empty area on the substrate 2 where the semiconductor chip 1 is not present. Therefore, the size of the semiconductor device is larger than that in the case where the semiconductor chips 1 are aligned and packed.

However, by arranging the surface mount type passive components 7 such as capacitors, coils and resistors, which are conventionally mounted on the motherboard, in this empty area,
The area of the motherboard can be reduced. Therefore, when the semiconductor device is connected to the motherboard to form the final product, the increase in the total area of the final product can be minimized. In the semiconductor device of FIGS. 1 to 4 , it is possible to arrange the passive component 7 in the empty area, and the same effect can be obtained in that case as well.

As described above, in the semiconductor device according to the present invention, with respect to the semiconductor chips 1 having various shapes, by disposing the semiconductor chips 1 on the center line X and the center line Y of the opposite side of the substrate 2, the warpage is caused. It can be seen that can be reduced. Further, it is understood that the warp can be further reduced by disposing the semiconductor chips 1 on all the straight lines (A to D) drawn so as to penetrate the gap between the two adjacent semiconductor chips 1.

Although the semiconductor chips 1 do not overlap in the thickness direction in the configurations shown in FIGS. 1 to 5, the stacked semiconductor chips are stacked in the thickness direction for higher density packaging. May be mounted. As a result, the area of the semiconductor device can be reduced. In this case, the electrical connection method of each semiconductor chip 1 to the wiring layer of the substrate 2 may be the flip chip bond method as the lower semiconductor chip and the wire bond method as the upper semiconductor chip. Alternatively, the electrical connection method of both semiconductor chips may be a wire bond method.

If it is not required to reduce the thickness of the semiconductor device, it is possible to use a thick plate material made of a ceramic or an organic resin that is hard to warp as the substrate 2, and in that case, the semiconductor chip 1 of the present invention is also used. The warp can be further reduced by the arrangement.

[0067]

This onset Ming Ma Ruchichippu type semiconductor device according to the present invention is,
As described above, for a quadrilateral substrate including a conductor layer, 3
Pieces or more semiconductor chips are electrically connected to the conductor layer while being arranged side by side in a plane on one surface of the substrate, it a plurality of electrodes for connecting the conductor layer to the outside electrically
Is a multi-chip type semiconductor device in which a ball grid array is formed on the other surface of the substrate, and the semiconductor chip group has at least one semiconductor chip on each of two center lines connecting midpoints of opposite sides of the substrate. Placed so that
The semiconductor chips are arranged in two adjacent
Draw all straight lines that pass between the semiconductor chips and are parallel to the substrate
And these straight lines connect at least one other semiconductor chip
It is designed to pass through, and
In this configuration, the lions are separated from each other .

Therefore, the above structure is less likely to warp,
Thus, it is possible to provide a multi-chip type semiconductor device having high reliability of electrical connection between the rugrid array and the outside.

Further , the multi-chip type semiconductor device of the present invention
Is preferably a structure in which a conductor layer is provided on the insulating substrate made of at least one resin material selected from the group consisting of polyimide, polyester, and glass epoxy.

According to this, even if the thickness of the substrate is 0.2 mm or less, it is possible to provide a multi-chip type semiconductor device in which the substrate is less likely to be damaged and is easy to handle.

Further , the multi-chip type semiconductor device of the present invention
The thickness of the substrate is preferably in the range of 0.1 to 0.2 mm. According to this, there is an effect that it is possible to provide a thin multi-chip semiconductor device in which the substrate is not easily damaged and which can be easily handled.

[Brief description of drawings]

FIG. 1 is a diagram showing a multi-chip type semiconductor device according to an embodiment of the present invention, in which (a) is a top view and (b) is a side view.

2A and 2B are views showing a multi-chip type semiconductor device according to another embodiment of the present invention, in which FIG. 2A is a top view and FIG.
Is a side view.

FIG. 3 is a diagram showing a multi-chip type semiconductor device according to still another embodiment of the present invention, in which (a) is a top view,
(B) is a side view.

FIG. 4 is a diagram showing a multi-chip type semiconductor device according to still another embodiment of the present invention, FIG.
(B) is a side view.

FIG. 5 is a top view showing a multi-chip type semiconductor device according to still another embodiment of the present invention.

FIG. 6 is a diagram showing an example of a conventional multi-chip type semiconductor device, (a) is a top view of the multi-chip type semiconductor device, (b) is a side view of the multi-chip type semiconductor device,
(C) is a side view of the multi-chip type semiconductor device in a warped state, and (d) is a front view of the multi-chip type semiconductor device in a warped state.

FIG. 7 is a diagram showing another example of a conventional multi-chip type semiconductor device, (a) is a top view of the multi-chip type semiconductor device, (b) is a side view of the multi-chip type semiconductor device,
(C) is a side view of the multi-chip type semiconductor device in a warped state, and (d) is a front view of the multi-chip type semiconductor device in a warped state.

8A and 8B are views showing still another example of a conventional multichip type semiconductor device, FIG. 8A is a top view of the multichip type semiconductor device, FIG. 8B is a side view of the multichip type semiconductor device, and FIG. 8A is a side view of the multi-chip type semiconductor device in a warped state, and FIG. 8D is a front view of the multi-chip type semiconductor device.

9A and 9B are views showing still another example of a conventional multi-chip type semiconductor device, FIG. 9A is a top view of the multi-chip type semiconductor device, FIG. 9B is a side view of the multi-chip type semiconductor device, and FIG. 8A is a side view of the multi-chip type semiconductor device in a warped state, and FIG. 8D is a front view of the multi-chip type semiconductor device.

[Explanation of symbols]

1 semiconductor chip 2 substrates 3 thin lines 4 Sealing resin 5 bumps 6 BGA (ball grid array) 7 Passive components X center line Y center line

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Claims (3)

(57) [Claims] 1. A quadrilateral substrate having a conductor layer, in which three or more semiconductor chips are arranged side by side on one surface of the substrate and are electrically connected to the conductor layer. comprising a plurality of electrodes for external electrical connection
A multi-chip type semiconductor device in which a ball grid array is formed on another surface of a substrate, wherein the semiconductor chip group has at least one semiconductor chip on each of two center lines connecting midpoints of opposite sides of the substrate. The semiconductor chips are arranged so as to straddle each other.
If you draw all the straight lines parallel to the substrate through
So that the straight line passes through at least one other semiconductor chip
And the above semiconductor chips are separated from each other.
Multi-chip type semiconductor device, characterized in that that. 2. The substrate is polyimide, polyester,
And at least one selected from the group consisting of glass epoxy
Also has a conductive layer on an insulating substrate made of one type of resin material.
The machine according to claim 1, wherein the machine is provided.
Multi-chip type semiconductor device. 3. The substrate has a thickness of 0.1 to 0.2 mm.
It is within the range, The claim 1 or 2 characterized by the above-mentioned.
Multi-chip type semiconductor device.