JP3488074B2 - Digital recording and playback device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording / reproducing apparatus for reproducing information of digital signals recorded on a recording medium such as a tape or a disc.

[0002]

2. Description of the Related Art In a digital video tape recorder (hereinafter referred to as a digital VTR), a video signal is digitized and a partial response class IV is applied.
It is considered to be recorded by. FIG. 21 is a block diagram showing a reproducing system of a conventional digital video tape recorder. The reproducing system of this digital VTR includes a magnetic head 1 for reading digital signals from a magnetic tape 1, a head amplifier 2, a waveform equalizing circuit 5, 1 + D circuit 6,
A / D conversion circuit 7, Viterbi decoding circuit 8, error correction circuit 1
0, PLL circuit 11.

A digital signal reproduced from the magnetic tape 1 by the magnetic head 2 and the head amplifier 3 is equalized by a waveform equalizing circuit 5 into a waveform that facilitates data detection. And
The data input to the 1 + D circuit 6 and precoded at the time of recording is restored. The reproduced signal is converted from an analog signal to a digital signal at a predetermined sampling rate by the A / D conversion circuit 7, and the Viterbi decoding circuit 8 performs Viterbi decoding using the data converted to the digital signal. In such a case, if the clock phase generated by the PLL circuit 11 is not proper, the A / D conversion circuit 7 cannot accurately convert analog data. Particularly in the case of Viterbi decoding, the signal demodulated by the demodulator 9 is subjected to error correction in the error correction circuit 10 by discriminating the data based on the amplitude level, and the phase of the clock is deviated to correctly convert the amplitude level. If not possible, a code error occurs.

For example, in FIG. 22, when the recording signal is "0, 1, 0, 1, 0, 0, 1, 0" ((a) in the same figure)
And the reproduced waveform (see (b) in the same figure) is simply detected with threshold values of "1" and "-1". That is, |
When the reproduced waveform | <1, it is set to "0", and when | reproduced waveform | ≥1, it is set to "1". When this waveform is detected at timings A to H, the detection signals are "0, 1, 1, 1, 1, 1, 1.
1, 0 "(see FIG. 7C).

When this is detected by Viterbi decoding, considering the "reproduced waveform" in FIG. 2B, after exceeding the threshold value "1" at the point B, after the point C, The data is determined when the "mountain" whose DC level is higher than the point B or the "valley" which is lower than "-1". As shown in FIG.
At point C, the DC level is higher than the threshold value "1" but lower than point B, so the data cannot be determined. It becomes lower than "-1" at the next D point, and it can be determined that the B point is "1" and the C point is "0" for the first time. (However, point D cannot be determined) D
In order to determine the point, a valley whose DC level is lower than the threshold value of "-1" or a "mountain" higher than "1" is searched for after the point E. Since point E does not exceed "1", point D cannot be determined. Since point F is not lower than point D, point D cannot be determined. It is understood that the D point is "-1", the E point is "0", and the F point is "0" only after the G point exceeds "1".

As described above, in the Viterbi decoding circuit 8, the DC
Since the waveform detection is performed at the level, the DC level detection accuracy is very important. Also, regarding the clock phase, if the clock is delayed, the point E may exceed "1". In that case, point E is set to "1" and F
The point is set to "-1" and false detection is performed. Therefore, D
As with the C level, proper clock control is essential.

[0007]

In the conventional apparatus, the clock phase is adjusted at the stage of manufacturing the reproducing apparatus, so that there is a problem that the adjustment takes time.
Also, after adjusting at the time of manufacture, it is fixed at that value,
Due to differences in characteristics between tape manufacturers and lot variations,
When tapes having different characteristics are reproduced, accurate data may not be detected in some cases. This is because the magnetic domains of the tape are inclined with respect to the normal direction of the tape, and this inclination changes between manufacturers and from lot to lot, resulting in a characteristic difference. Further, the optimum point of the clock phase changes due to the change over time of the characteristics of the magnetic tape or the magnetic head (the inclination of the magnetic domain changes due to wear, etc.). Data could not be detected in some cases.

In addition to this, a method of automatically searching for the optimum point of the clock phase by using the error rate of the reproduced data during normal use has been considered (Japanese Patent Laid-Open No. 6-25989).
No. 1). In this case, when the error rate is 10 ^-5 , 1
One error occurs in every 100,000, but in order to accurately count the number of errors, it is necessary to read 1 million data and use the average value thereof. Further, when the error rate becomes 10 ⁻⁶ , there is one error per one million, so it is necessary to calculate the average value from 10 million data. In this way, as the adjustment approaches the appropriate value, the error decreases and the time required for measurement increases exponentially. Therefore, there has been a problem that the more time it takes to attain the optimum state, the longer the measurement time is required.

Although the above problem describes the case where the recording medium is a tape, the recording medium is a magneto-optical disk or a DVD.
-There is a similar problem in the case of RAM and the like.

The present invention has been made in view of the above circumstances, and provides a digital recording / reproducing apparatus capable of detecting data correctly and promptly by promptly finding an optimum point of a clock phase. The purpose is to

[0011]

According to the present invention, there is provided reproducing means for reproducing information recorded on a recording medium, a waveform equalizing circuit for correcting inter-waveform interference of a signal reproduced by the reproducing means, and A digital data conversion circuit for converting a signal output from the waveform equalization circuit into digital data , and a "1" frequency is counted for each predetermined period of digital data output from the digital data conversion circuit to count the frequency of the previous period.
A frequency analysis circuit for detecting an increase / decrease in the "1" frequency compared with the "1" frequency, and a phase of the clock signal corresponding to the increase / decrease in the "1" frequency obtained by the frequency analysis circuit. And a clock phase adjusting circuit that adjusts so as to match the digital recording / reproducing apparatus.

Further, the present invention reduces the C / N before SL digital data conversion circuit, erasure error or insertion
A feature is that the clock phase is adjusted by increasing the error .

Further, the present invention changes the threshold for performing digital data conversion in the digital data converting circuit, by increasing the erasure error or insertion errors,
It is characterized in that the clock phase is adjusted.

Further, the present invention is characterized in that the phase of the sampling clock in the digital data conversion circuit is changed to increase the disappearance error or the insertion error to adjust the clock phase.

Further, the present invention is further comprising a noise adding circuit adding noise to the reproduced signal by the reproducing means, said waveform equalizer, by correcting the waveform interference of the reproduction signal noise is added Missing error or insertion
It is characterized by increasing the input error and adjusting the clock phase.

Further, the present invention is characterized in that the waveform equalization circuit reduces the equalization amount and increases the erasure error or the insertion error to perform the clock phase adjustment.

The digital recording / reproducing apparatus of the present invention analyzes the reproduction data loss error and the insertion error in order to set the phase of the clock necessary for performing the Viterbi decoding to the optimum value. A frequency analysis of insertion errors is performed to minimize the percentage detected as data. In particular, by intentionally increasing the noise level or reducing the amount of waveform equalization, it is possible to automatically control to the optimum point of the clock phase at high speed, and even when replacing with a magnetic tape with different characteristics, The reproduced data can always be read with an appropriate clock phase.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a digital VTR according to the present invention. This digital V
The TR has a configuration in which the noise adding circuit 4 and the waveform analyzing circuit 12 are added to the digital VTR shown in FIG.

Since the signal converted into an electric signal by the magnetic head 2 is a weak signal of about 1 mV, it has to be raised to a level necessary for signal processing, and is amplified by the head amplifier 3. Then, the reproduction output from the head amplifier 3 is input to the noise adding circuit 4 which adds noise in order to perform highly accurate clock phase adjustment.

FIG. 2 is a block diagram showing the noise adding circuit and the waveform equalizing circuit. The signal from the head amplifier 3 is
First, the input level switching circuit 26 is entered and the signal level is attenuated. Then, after that, it is amplified by the amplifier 28. The amplifier gain of the amplifier 28 is the amplifier gain switching circuit 2
Determined by 7. That is, during normal reproduction, the input level switching circuit 26 allows the signal to pass without being attenuated, and the amplifier gain switching circuit 27 also does not increase the amplifier gain of the amplifier 28. On the other hand, when the clock phase is adjusted with high accuracy, the signal is attenuated by the input level switching circuit 26 and the amplifier 2 is switched by the amplifier gain switching circuit 27.
Increase the amplifier gain of 8 to add noise.

The output of the noise adding circuit 4 is the waveform equalizing circuit 5
Entered in. The waveform equalizing circuit 5 is composed of an amplitude compensating circuit 5a and a phase compensating circuit 5b in order to equalize the reproduced data into a waveform in which the data can be easily detected. Amplitude compensation circuit 5a
2 is as shown in FIG. 2 and suppresses the influence of inter-waveform interference. The reproduced waveform of the digital data recorded at high density on the recording medium is output as a waveform with a wide skirt, and the respective waveforms interfere with each other. As shown in FIG. 3, there is no inter-waveform interference (isolated wave). When adjacent, the peak value (amplitude level of the reproduction signal) becomes low. The effect of the amplitude compensation circuit (transversal filter) 5a suppresses the spread of the bottom of the reproduced waveform,
As shown in FIG. 4, the waveform width (half-amplitude value waveform width W50) is narrowed.

That is, in FIG. 2, the signal output from the noise adding circuit 4 is input to the level adjusting means 31 composed of a variable resistor and the delay circuit 29, and the level adjusting means 3 is supplied.
The signal input to 1 is attenuated and input to the inverting input terminal of the amplifier 33 (point a in FIG. 4). The signal input to the delay circuit 29 is delayed by a bit interval (τ), and the amplifier 33
4 is divided into a signal input to the non-inverting input terminal (point b in FIG. 4) and a signal input to the delay circuit 30. Delay circuit 3
The signal input to 0 is further delayed by the bit interval (τ), attenuated by the level adjusting means 32, and input to the inverting input terminal of the amplifier 33 (point c in FIG. 4). In this way, from the signal (point b) delayed by one bit, the signal (a
Point) and the signal delayed by 2 bits
It suppresses the swelling of the skirt and shapes the waveform to suppress interference between waveforms.

The signal whose waveform has been shaped is the waveform equalization circuit 5
Is input to the phase compensation circuit 5b (not shown in FIG. 2).
Due to the magnetic anisotropy (inclination of magnetic domains) of the tape, the phase compensation circuit 5b compensates for a reproduced waveform whose front and rear are asymmetrical with respect to the time axis, into a symmetrical waveform as shown in FIG.

From the waveform equalized data, the PLL circuit 1
1 generates clocks for the A / D conversion circuit 7, the Viterbi decoding circuit 8, and the demodulation circuit 9. The output of the waveform equalization circuit 5 is input to the 1 + D circuit 6 and the precoded data at the time of recording is restored.

The output of the 1 + D circuit 6 is input to the waveform analysis circuit 12. FIG. 6 is a block diagram showing the waveform analysis circuit 12. The waveform analysis circuit 12 includes a data detection circuit 19
And a frequency analysis circuit 20 and an addition circuit 21. The data detection circuit 19 includes resistors R ₁ , R ₂ and R ₃ connected in series between Vcc and GND, and comparison circuits 13 and 14.
And an OR circuit 15. The output of the 1 + D circuit 6 is input to the non-inverting input terminal of the comparison circuit 13 and the inverting input terminal of the comparison circuit 14. At the inverting input terminal of the comparator circuit 13,
The voltage Vh between the resistors R ₁ and R ₂ is input, and the voltage Vl between the resistors R ₂ and R ₃ is input to the non-inverting input terminal of the comparison circuit 14. The frequency analysis circuit 20 has a counter 1
6, a latch 18, and a comparison circuit 17. The output of the OR circuit 15 and HSW (head switching pulse) are input to the counter 16. The output of the counter 16 is input to the non-inverting input terminal of the comparison circuit 17 and the latch 18, and the output of the latch 18 is input to the inverting input terminal of the comparison circuit 17.

In the comparison circuits 13 and 14, the DC levels of the input analog data (1 + D circuit output) and the reference voltage (threshold voltage Vh, Vl) are compared, and the comparison circuit 13 is compared.
Then, if the DC level is higher than the threshold voltage (Vh), "1" is output, and if it is low, "0" is output. Further, in the comparison circuit 14, the threshold voltage (Vl)
If the level is high, "0" is output, and if it is low, "-1"
Is output. The outputs of the comparison circuits 13 and 14 are the OR circuit 1
5 is input, both "1" and "-1" are converted into "1", and "0" becomes "0". FIG. 7 shows an output example of the comparison circuit and the OR circuit.

The output of the OR circuit 15 is input to the counter 16 and reset by HSW (head switching pulse) to count the number of "1" for one track. HSW is a pulse for switching the reproduction signal output from the magnetic head 2 according to the rotation angle of the magnetic head 2, and if the "High" period is the magnetic head 2, the signal of the magnetic head 2 is the "Low" period. Input to the head amplifier. Therefore, by operating the counter 16 only during the "High" period, "1" data for one track can be counted.

The output of the counter 16 is input to the latch 18. The signal input to the latch 18 is output with a delay of one track, and the comparison circuit 17 compares the output (pulse number) of the counter 16 and the output (pulse number) of the latch 18 and outputs from the latch 18. If the number of pulses is large, it is "High", and if it is small, it is "Low". The determined data is input to the adder circuit 21.

FIG. 8 is a block diagram of the adder circuit 21.
First, the data is input to the addition / subtraction changeover switch 27.
The addition / subtraction changeover switch 27 is an inverting input terminal of the addition / subtraction circuit 28 when the output signal of the comparison circuit 30 is “High”, and a non-inversion input of the addition / subtraction circuit 28 when the output signal of the comparison circuit 30 is “Low”. Switch the signal to input to the terminal. Then, it is input to the integration circuit 29, and is input to the non-inverting input terminal when it is added, and is input to the inverting input terminal when it is subtracted. Then, it is output as a clock phase adjustment voltage of the PLL 11. This output is input to the inverting input terminal of the comparison circuit 30 and the latch 31. In the latch 31, it is delayed by one track and input to the non-inverting input terminal terminal of the comparison circuit 30. Then, the comparison circuit 3
The output of 0 becomes a control signal of the addition / subtraction changeover switch 27.

The operation of this circuit will be described with reference to FIG.
First, the clock phase is delayed (point α in FIG. 9), and the output of the integrating circuit 29 rises (the direction in which the adjustment voltage is increased and the clock phase is delayed, the direction from α to β).
In the case of 1, the output of the latch 31 and the integration circuit 2 are delayed by one track because the clock phase adjustment voltage is increased.
When the outputs of 9 are compared, the output of the comparison circuit 30 becomes "Low" because the voltage from the integration circuit 29 is higher. Then, the result of the frequency analysis input from the comparison circuit 17 is input to the subtraction circuit. As a result, the output of the integrating circuit 29 falls (the adjustment voltage is lowered and the clock phase is advanced), and the output moves to the γ point (the clock phase is advanced toward the optimum point). Further, in the comparison circuit 30, since the output of the integration circuit 29 is in the downward direction, it becomes "High". As a result, the addition / subtraction switch 27 is switched and the signal of the comparison circuit 17 is input to the addition side of the addition / subtraction circuit 28. Since the frequency of the comparison circuit 17 decreases, "Lo
w ”, and the integration circuit 29 continues to fall.

When this state changes and the optimum point is passed (point "0" in FIG. 9), the frequency analysis result from the frequency analysis circuit 20 changes in an increasing direction. Then, since the addition / subtraction circuit 28 is adding, the integration circuit 29
Output switches to the rising side (clock delay). As a result, the comparison circuit 30 switches to "Low". The addition / subtraction changeover switch 27 is used for the addition / subtraction circuit 2
8 is switched to the subtraction side, and the output of the comparison circuit 17 is "Lo
w ”, and the output of the integrating circuit 29 falls (clockwise advancing direction). In this way, the optimum clock phase is adjusted.

Next, the erasure error and the insertion error will be described. When the threshold voltage (Vh) in FIG. 6 is lowered, not only the original data but also the foot of the reproduced waveform is detected as data (insertion error) as shown in FIG. 10, and the data detected as “1” becomes To increase. Also, as shown in FIG.
Although it will not be erroneously detected if it is correctly equalized, as shown in Fig. 11, if waveform equalization is performed too much, that is, if the amount of pulling of the skirt portion is too large, it bounces to the negative side. Will end up. In such an excessive waveform equalization state, the rebound on the negative side may be discriminated as "-1". This results in increased insertion error.
On the other hand, as shown in FIG. 10, when the threshold voltage becomes high, the detection circuit often determines that the signal having the low crest value is “0” due to the inter-waveform interference, and thus the detection circuit becomes “1”. Less frequent (increased lost errors).

Next, the clock phase adjustment will be described. FIG. 12 is a waveform diagram showing the outputs of the comparison circuit and the OR circuit of the waveform analysis circuit in the case of the optimum clock phase. On the other hand, FIG. 13 shows the case where the clock phase is delayed,
The points a and b are erroneously detected. Although the tendency of occurrence changes slightly depending on the waveform of data and the timing of the clock, the waveform of which the skirt has widened due to the inter-waveform interference causes the clock phase to shift, and thus the data of "0" is mistaken as "1". When it is further deviated, "1" may be mistaken for "0", but the frequency of "0" and the frequency of "1" are high, and the frequency of "0" is high. Generally tends to spread due to inter-waveform interference, so in general, there are more insertion errors than erasure errors, and the frequency of "1" is more frequent.

The relationship with the dropout is that the reproduction waveform is as shown in FIG. 14 when the dropout occurs. That is, the entire area where the dropout has occurred becomes "0". Therefore, no error occurs in the data that is originally “0”, and only the data that is originally “1” becomes an error (disappearing error). Therefore, the number of "1" s detected as data is reduced.

As shown in FIG. 15, the disappearance error and the insertion error when there is a noise jump are as follows.
When there is data near the threshold value, the detection output changes depending on whether the amplitude level becomes higher or lower due to noise. What is wrong with "0" as "1" is an insertion error, and "1". Is a lost error.
However, the frequency of "0" and "1" in the data is "0"
However, since the inter-waveform interference is significant, the insertion error increases. This is because the probability of erroneous data of "0" such as b as "1" is higher than that of data of "1" which is erroneous as "0", such as point a in FIG. Therefore, when noise is increased, the number of insertion errors is larger than the number of erasure errors.

Regarding the effect of inter-waveform interference, as shown in FIG. 16, when the waveform equalization amount becomes insufficient from the optimum value, the insertion error increases and the frequency of "1" increases. When the tap coefficient increases, the waveform equalization amount (the amount subtracted from the delay signal)
It is understood that the frequency of “1” increases as the tap coefficient of the amplitude compensating circuit 5a of the waveform equalizing circuit 5 decreases. The frequency deviation of "1" with respect to the clock phase "0" is shown in FIG. The smaller the tap coefficient, the larger the inclination amount of the increase of "1". Therefore, the smaller the waveform equalization, the larger the amount of data detected by "1", and the higher the accuracy of optimizing the clock phase,
Moreover, the optimization time can be shortened. The amount of waveform equalization can be adjusted by the level adjusting means 31 and the level adjusting means 32 shown in FIG. Level adjusting means 31,
If the attenuation amount of 32 is increased, the amount of waveform equalization decreases and the interference between waveforms increases. Therefore, the adjustment accuracy can be improved by increasing the attenuation amount only during the adjustment.

By using the result of detecting the frequency change as described above, the delay time is changed by switching the serially connected delay elements of the clock phase adjusting circuit 23 of the PLL circuit 11 shown in FIG. Can be adjusted to.

The signal output from the waveform equalization circuit 4 is
The phase is compared with the clock input to the phase comparator 24 and output from the VCO 22. The charge pump 25 removes only the low frequency component based on the error voltage output from the phase comparator 24 to generate a VCO control voltage. VC
O22 controls the oscillation frequency based on this VCO control voltage.

In this way, the reproduction data input from the waveform equalization circuit 4 and the phase of the clock oscillated by the VCO 22 are matched. Since this clock is not at the optimum timing for detecting data, the clock phase adjusting circuit 23 adjusts the clock phase based on the frequency change information input from the frequency analyzing circuit 20 .
The clock adjusted to the optimum clock phase is input to the A / D conversion circuit 7 (FIG. 1). In the A / D conversion circuit 7,
The reproduced data is converted from an analog signal to a digital signal.

The clock phase adjustment circuit 33 of the PLL circuit 11 shown in FIG. 19 adjusts the clock phase. FIG. 19 is a block diagram showing another example of the clock phase adjustment circuit, and FIG. 20 is a waveform diagram of each part of the clock phase adjustment circuit. First, the output of the VCO 22 is N
It is input to the AND circuit 34. Assume that the waveform is a (the actual clock is a continuous signal, but only one pulse is shown to clarify the operation of clock adjustment). N
The output signal of the AND circuit 34 is as shown in b. The falling timing is deviated by the signal of d. Next, it is input to an integrating circuit composed of a variable grinding machine (electronic VR) 35 and Cd, and a waveform like c is obtained. The dullness of the waveform of the integrating circuit changes with a time constant determined by the variable resistor (electronic VR) 35 and Cd. The output of the integration circuit is inverted by the NAND circuit 36 and becomes the clock for the A / D conversion circuit 6, the Viterbi decoding circuit 7, and the demodulation circuit 8. Therefore, the frequency analysis circuit 2
The variable resistor (electronic V
The clock phase can be adjusted by changing the resistance value of R).

The Viterbi decoding circuit 8 detects data by utilizing the regularity of digital recording based on the peak value of the reproduced data. The demodulator 9 restores the data converted into a signal having a spectrum suitable for the characteristics of the recording medium at the time of recording. The error correction circuit 10 corrects a code error generated when recording / reproducing from a recording medium.

Although the digital recording / reproducing apparatus in which the recording medium is a tape has been described above, the present invention can be applied to a recording medium such as a magneto-optical disk or a DVD. That is, when high-density recording is performed, inter-waveform interference occurs, and disk characteristics change due to changes over time, so the present invention is an effective means for such clock phase optimization.

[0044]

As described above, according to the present invention, by analyzing the digital signal output from the waveform equalization circuit by the frequency analysis circuit, the "1" frequency, that is, the error frequency.
Detecting the increase and decrease of, and responding to the increase and decrease of this error frequency,
The clock phase adjustment circuit adjusts the phase of the clock signal so that it matches the phase of the reproduced data, eliminating the need for phase adjustment at the time of manufacture. Even when the type of recording medium is changed, the data is always in the optimum state. Can be played with. In particular, when there is a lot of noise or the like and the error frequency is high, the amount of data for clock phase adjustment increases, so the time required to acquire the amount of data required to optimize the clock phase can be greatly shortened, and the phase adjustment speed can be increased. It has the advantage of being faster.

Furthermore, according to the present invention, the disappearance error
Since the insertion error is increased, the time required to acquire the amount of data necessary for optimizing the clock phase can be significantly shortened, and high-speed and accurate clock adjustment can be performed.
In particular, when the clock adjustment is performed and the error frequency is reduced, the error frequency is intentionally increased to enable high-speed and accurate clock adjustment.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a playback system of a digital VTR according to the present invention.

FIG. 2 is a block diagram showing a noise adding circuit and a waveform equalizing circuit.

FIG. 3 is a waveform diagram showing a state in which there is no interference between waveforms and a state in which there is.

FIG. 4 is a waveform diagram showing an input waveform and an output waveform of the amplitude compensation circuit.

FIG. 5 is a waveform diagram showing an input waveform and an output waveform of the phase compensation circuit.

FIG. 6 is a block diagram showing a waveform analysis circuit.

FIG. 7 is a waveform diagram showing the outputs of the comparison circuit and the OR circuit of the waveform analysis circuit.

FIG. 8 is a block diagram showing an adder circuit of a waveform analysis circuit.

FIG. 9 is a graph showing changes in a loss error and an insertion error due to noise.

FIG. 10 is a waveform chart showing a change in output according to a threshold value of the waveform analysis circuit.

FIG. 11 is a waveform diagram when waveform equalization is performed too much.

FIG. 12 is a waveform diagram showing the outputs of the comparison circuit and the OR circuit of the waveform analysis circuit in which the optimum clock phase adjustment is performed.

FIG. 13 is a waveform diagram showing the outputs of the comparison circuit and the OR circuit of the waveform analysis circuit when the clock phase adjustment is delayed.

FIG. 14 is a waveform diagram showing the occurrence of dropout.

FIG. 15 is an explanatory diagram showing the occurrence of a loss error and an insertion error at a detection point.

FIG. 16 is a graph showing changes in an erasure error and an insertion error depending on the amount of waveform equalization.

FIG. 17 is a graph showing frequency deviation between an erasure error and an insertion error due to waveform equalization.

FIG. 18 is a block diagram showing an example of a clock phase adjustment circuit.

FIG. 19 is a block diagram showing another example of the clock phase adjustment circuit.

FIG. 20 is a waveform diagram of each part of the clock phase adjustment circuit.

FIG. 21 is a block diagram showing an example of a reproduction system of a conventional digital VTR.

FIG. 22 is a waveform diagram of a conventional waveform equalization circuit.

[Explanation of symbols]

2 magnetic head 3 head amplifier 4 Noise addition circuit 5 Waveform equalization circuit 11 PLL 12 Waveform analysis circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10 G11B 20/18

Claims (6)

(57) [Claims] 1. A reproducing means for reproducing information recorded on a recording medium, a waveform equalizing circuit for correcting interference between waveforms of a signal reproduced by the reproducing means, and a signal outputted from the waveform equalizing circuit. A digital data conversion circuit for converting the data into digital data , and counting the "1" frequency for each digital data of the predetermined period output from the digital data conversion circuit.
A frequency analysis circuit for detecting an increase / decrease in the "1" frequency in comparison with the "1" frequency in the period, and a phase of the clock signal corresponding to the increase / decrease in the "1" frequency obtained by the frequency analysis circuit for reproducing data. And a clock phase adjusting circuit that adjusts so as to match the phase of the digital recording / reproducing apparatus. 2. The C / N of the digital data conversion circuit.
The clock phase adjustment is performed by reducing the clock error and increasing the loss error or the insertion error.
The digital recording and reproducing apparatus described. 3. The erase error is changed by changing a threshold value for performing digital data conversion in the digital data conversion circuit.
2. The digital recording / reproducing apparatus according to claim 1, wherein the clock phase is adjusted by increasing the insertion error or insertion error . 4. The erasure error is corrected by changing the phase of the sampling clock in the digital data conversion circuit.
2. The digital recording / reproducing apparatus according to claim 1, wherein the clock phase is adjusted by increasing the insertion error . 5. A noise adding circuit for adding noise to the signal reproduced by said reproducing means is further provided, wherein said waveform equalizing circuit corrects inter-waveform interference of the reproduced signal to which noise has been added, thereby eliminating or inserting an erasure error. D
2. The digital recording / reproducing apparatus according to claim 1, wherein the clock phase is adjusted by increasing the error rate. 6. The waveform equalization circuit reduces the equalization amount and eliminates
2. The digital recording / reproducing apparatus according to claim 1, wherein the clock phase is adjusted by increasing the loss error or the insertion error .