JP3485786B2 - Audio data compression / decompression device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a voice data compression / decompression device for compressing voice data during voice recording and for decompressing the compressed data during voice reproduction, and to this compression / decompression device. Regarding digital filters.

[0002]

2. Description of the Related Art In a digital audio device capable of recording and reproducing, a voice signal is digitized, and compressed data is generated to generate compressed data, and the compressed data is recorded on a recording medium. It And
The compressed data read out from the recording medium is subjected to decompression processing that is the reverse of that used during recording, and the audio data is reproduced.

FIG. 8 is a block diagram showing a configuration of a voice data compression / decompression device for compressing voice data to generate compressed data and decompressing the compressed data to generate voice data. At the time of recording operation, that is, compression processing,
The attenuator 1, the digital filter 2, the improved discrete cosine transform circuit 3, and the quantization circuit 4 operate to compress the audio data input to the attenuator 1 to generate compressed data.

The attenuator 1 receives voice data obtained by A / D converting a voice signal, and attenuates the voice data as necessary. The digital filter 2 separates the audio data input through the attenuator 1 into predetermined frequency bands to generate a plurality of band data. A modified discrete cosine transform (MDCT) circuit 3 performs a discrete cosine transform on the band data input from the digital filter 2 to generate coefficient data corresponding to each band data. Then, the quantization circuit 4
Compressed data is generated by quantizing coefficient data input from the DCT circuit 3 according to a predetermined quantization table. The arithmetic processing in the MDCT circuit 3 and the quantization circuit 4 is usually performed on a plurality of band data in a time division manner.

In the reproducing operation, that is, in the expansion processing, the inverse quantization circuit 5, the improved discrete cosine inverse conversion circuit 6, the digital filter 7 and the attenuator 8 operate to read out from a predetermined recording medium and perform the inverse quantization 5. The compressed data input to is expanded and reproduced as audio data. Inverse quantization circuit 5
Refers to the same quantization table as the quantization circuit 4 of the compression processing system, and generates coefficient data corresponding to the coefficient data generated in the MDCT circuit 3. IMDCT: Inverse Modified Discrete Cosine Tra
The nsform) circuit 6 performs a conversion process reverse to that of the MDCT circuit 3 to generate band data corresponding to the band data generated in the digital filter 2. The digital filter 7 synthesizes band data for each frequency band input from the IMDCT circuit 6 to generate audio data. And
The attenuator 8 attenuates the audio data input from the digital filter 7 as needed, and supplies the attenuated audio data to a next-stage circuit including a D / A converter and an amplifier. The MDCT circuit 3 operates in the inverse quantization circuit 5 and the IMDCT circuit 6.
Similarly to the quantization circuit 4, the time division is performed on a plurality of band data. As a result, a plurality of band data are input to the digital filter 7 in a time division manner.

[0006]

The digital filter 2,
7 is usually composed of a combination of a plurality of registers and various arithmetic units. In addition, each digital filter 2,
The data processing in 7 is continuously performed while holding the time-series data for a predetermined period. Therefore, even after the processing of the predetermined data is completed, the various types of data temporarily held in the respective processing steps remain in the registers incorporated in the respective units. Such residual data is irrelevant to the data input next, and is a factor that causes a calculation error in the calculation processing of each unit. Therefore, noise is likely to occur at the start of recording or reproduction.

Normally, noise generated at the start of recording or reproduction is suppressed by operating the attenuators 1 and 8 at that timing. However, in the digital filter 2 in which the attenuator 1 is connected to the input side, even if the data on the input side is suppressed, unnecessary data is output due to the data left in the register incorporated in the digital filter 2. May be

Therefore, it is an object of the present invention to prevent unnecessary data from being output in each process of compressing or expanding audio data while each unit is initialized at the start of each operation.

[0009]

The present invention has been made to solve the above-mentioned problems, and has a first feature in that audio data is separated for each predetermined frequency band and each band is separated. Encoding processing is performed for each to generate compressed data, and a plurality of compressed data for each frequency band read from the recording medium is subjected to decoding processing, respectively, and is synthesized to generate audio data. A decompression device, wherein the audio data is separated into a plurality of frequency bands to generate a plurality of band data;
An encoding circuit for encoding the plurality of band data generated by the first digital filter in time series to generate compressed data, and a plurality of band for decoding the plurality of compressed data read from a predetermined recording medium. A decoding circuit that generates data, and a second digital filter that combines the plurality of band data generated by the decoding circuit to generate voice data, and the first digital filter includes:
A replacement unit that selectively replaces the plurality of band data with “0” is provided, and “0” is supplied to the encoding circuit during the initialization operation of the compression process, and the second digital filter is , Attenuating means for attenuating and outputting the audio data, and attenuating the audio data to “0” during the initialization operation of the expansion processing.

A second feature is that a digital filter for separating the audio data into a plurality of frequency bands to generate a plurality of band data and synthesizing the plurality of band data to generate a sound data. And an encoding circuit that encodes the plurality of band data generated by the digital filter in time series to generate compressed data, and a plurality of band data that decodes the plurality of compressed data read from a predetermined recording medium. And a decoding circuit that supplies the digital data to the digital filter, the digital filter attenuates the audio data to be output and a replacement unit that selectively replaces the plurality of band data to be output with “0”. And outputting "0" to the encoding circuit during the initialization operation of the compression process.
During the initialization operation of the expansion processing, the audio data is attenuated to "0".

According to the audio data compression / expansion circuit of the present invention, during the audio data compression process, the output of the digital filter for performing the separation process is independent of the circuit operation of the digital filter during the initialization operation. , All are replaced with “0”. Further, during the decompression process of the compressed data, all the audio data generated by the synthesizing process is suppressed to "0" during the initialization operation.

[0012]

1 is a block diagram showing a first embodiment of an audio data compression / expansion apparatus according to the present invention. The MDCT circuit 12, the quantization circuit 13, the inverse quantization circuit 14, and the IMDCT circuit 15 are the same as the MDCT circuit 3, the quantization circuit 4, the inverse quantization circuit 5, and the IMDCT circuit 6 shown in FIG. 8, respectively. That is, the MDCT circuit 12 is converted from the band data generated by the digital filter 11.
And the quantization circuit 13 generates compressed data, and the inverse quantization circuit 14 and the IMDCT circuit 15 generate band data to be input to the digital filter 16 from the compressed data.

A feature of the present invention is that a replacement circuit 11c as replacement means is provided on the output side of the first digital filter 11, and the output of a QMF circuit 11b described later is forcibly set to "0". I have replaced it with. Then, by the attenuator 16b as an attenuator provided on the output side of the second digital filter 16,
This is because the output of the QMF circuit 16a, which will be described later, is all attenuated to "0" in a predetermined period.

The first digital filter 11 has an attenuation circuit 11a, a QMF circuit 11b and a replacement circuit 11c. The attenuating circuit 11a is connected to the audio data input terminal and attenuates the incoming audio data to a desired level. The QMF circuit 11b takes in the audio data input via the attenuating circuit 11a, separates it into predetermined frequency bands, and generates a plurality of band data. Replacement circuit 11
c selects either the band data input from the QMF circuit 11b or "0" and supplies it to the MDCT circuit 12. The replacement circuit 11c is a normal QMF circuit 11b.
The side is selected, and "0" is selected only while the initialization operation is performed in the QMF circuit 11b. Therefore, no matter what data is output from the QMF circuit 11b when the recording operation is started,
Since all “0” s are supplied, the generation of noise is suppressed.

The second digital filter 16 has a QMF circuit 16a and an attenuation circuit 16b. QMF circuit 16
a is the QMF circuit 11b of the first digital filter 11
The reverse processing is performed, and a plurality of band data input from the IMDCT circuit 15 are combined to generate voice data. The attenuator circuit 16b is the same as the attenuator circuit 11a of the first digital filter 11, and attenuates the audio data input from the QMF circuit 16a to a desired level. The attenuator circuit 16b is a multiplier that multiplies the audio data by a predetermined coefficient, and when the output of the data from the QMF circuit 16a is stopped, that is, the QMF circuit 16a.
While the initialization operation is being carried out, the output is set to "0" by setting the multiplier to "0". Therefore, when the reproduction operation is started, all the audio data output from the QMF circuit 16a is suppressed to "0".

In the above audio data compression / decompression device, unnecessary data is not output at the start of the recording operation or the start of the reproducing operation, so that the generation of noise can be prevented. Also, comparing the circuit scales of the first and second digital filters 11 and 16 with the device shown in FIG. 8, only the replacement circuit 11c is substantially increased, and the circuit scale is hardly increased.

The first and second digital filters 11, 1
In describing the configuration of No. 6, first, the arithmetic operation of the digital filter will be described. FIR type (Finite Impuls
The e Response digital filter is configured to obtain the output data Y (n) by convolving the input data X (n) and the impulse response, as shown in equation (1).

[0018]

[Equation 1]

Here, h (k) is a filter coefficient, and N is the number of taps. Then, when Z-transforming equation (1),

[0020]

[Equation 2]

## EQU3 ## From this equation (2),

[0022]

[Equation 3]

Thus, the frequency response is known. And ω
= 2πk / N, equation (3) becomes

[0024]

[Equation 4]

[0025] This equation (4) can be regarded as a discrete Fourier transform (DFT) equation. Therefore, the filter coefficient h (k) is the inverse transform (IDFT: Invers) of the frequency characteristic given by the equation (4).
e Discrete Fourier Transform).

By the way, for the digital filter having the first filter coefficient h1 (n),

[0027]

[Equation 5]

The second filter coefficient h2 given by
The digital filter having (n) is called a mirror filter because of its frequency response. The relationship of Z conversion in such a mirror filter is

[0029]

[Equation 6]

It is Here, considering the frequency response,

[0031]

[Equation 7]

Therefore, the equation (6) is

[0033]

[Equation 8]

It becomes This shows that the frequency response of the mirror filter is symmetric at π / 2. Here, since π / 2 is 1/4 of the sampling period, this mirror filter uses a QMF (Quadrature Mirror).
Filter). Such a QMF is known as IEE Transactions on Acoustics Speech and Signal Processing, ISSP Vol. 32, No. 3, June 1984, (IEEE Tr.
ans. Acoust., Speech, Signal Process., Vol.ASSP-32,
No. 3, June 1984) pages 522-531.

When the separation filter is constructed by the above QMF, the expression is obtained by the convolution process of the input data X (n) and the impulse response and the addition or subtraction process of them.
As shown in (9) and the equation (10), two output data Ya (n) and Yb (n) which are band data of the input data X (n) are obtained.

[0036]

[Equation 9]

[0037]

[Equation 10]

The QMF circuit 11b of the first digital filter 11 is constructed so as to execute the calculation according to the equations (9) and (10). Further, in the case of configuring the synthesis filter, the convolution process of the impulse response with respect to the addition value or the subtraction value of the first input data Xa (n) and the second input data Xb (n) is performed, and the expression (11) and the expression As shown in (12),
Output data Y (n) which is a composite data of the input data Xa (n) and Xb (n) is obtained.

[0039]

[Equation 11]

[0040]

[Equation 12]

The QMF circuit 16a of the second digital filter 16 is constructed so as to execute the calculation according to the equations (11) and (12). FIG. 2 is a block diagram showing the configuration of the first digital filter 11b. RAM21 is
The attenuation input data x (n) input from the multiplier 25 is connected to a multiplier 25, which will be described later, for a predetermined period of time, and sequentially read and output for each step of the arithmetic processing. RO
M22 stores a plurality of filter coefficients h (k) in advance and stores 1
A predetermined filter coefficient h (k) is read corresponding to the value of k that increases at each step and repeatedly output. This k
Corresponds to k shown in the above equations (9) to (10). The first selector 23 has an encode input and a RAM.
21 and is connected to the time series input data X (n) or R
One of the attenuation input data x (n) read from the AM 21 is selected and output. The second selector 24 is connected to the attenuation input and the ROM 22, and selects and outputs either the attenuation coefficient g (m) or the filter coefficient h (k) read from the ROM 22. The first and second selectors 23 and 24 are selectively controlled in response to a common selection control signal SC.

The multiplier 25 is connected to the first selector 23 and the second selector 24, and one of the input data X (n) or the attenuated input data x (n) selected by the first selector 23, One of the attenuation coefficient g (m) and the filter coefficient h (k) selected by the second selector 24 is multiplied. Here, when the first selector 23 selects the input data X (n), the second selector 24 selects the attenuation coefficient g (m), and the first selector 23 selects the attenuated input data x (n). When doing so, the second selector 24 operates so as to select the filter coefficient h (k). Thus, the multiplier 25 multiplies the input data X (n) by the attenuation coefficient g (m) or multiplies the attenuated input data x (n) by the filter coefficient h (k). Then, the multiplication data of the input data X (n) and the attenuation coefficient g (m) is stored in the RAM.
21 and the multiplication data of the attenuation input data x (n) and the filter coefficient h (k) is supplied to the cumulative adder 26.

The cumulative adder 26 including the adder 27 and the register 28 is connected to the multiplier 25 and cumulatively adds the multiplication data input from the multiplier 25 according to the tap number. That is, the data read from the register 28 and the multiplication data input from the multiplier 25 are added by the adder 27, and the added data is stored in the register 28 again,
The multiplication data of the multiplier 25 is cumulatively added.

First register 29 and second register
The numeral 30 is connected to the cumulative adder 26, alternately fetches and stores the cumulative addition data continuously input from the cumulative adder 26, and outputs each at a predetermined timing. For example, the intermediate data A output from the cumulative adder 26 at an odd number
(N) is stored in the first register 29, and the intermediate data B (n) output at an even number is stored in the second register 30. The adder / subtractor 31 is connected to the first register 29 and the second register 30, and the intermediate data A (n) and B read from the registers 29 and 30 are read.
(N) is subtracted or added.

The output register 32 is connected to the adder / subtractor 31, stores the add / subtract data input from the adder / subtractor 31 for each arithmetic processing, and outputs it as output data Ya (n) and Yb (n). For example, the subtraction data corresponds to the adder / subtractor 31 which alternately repeats the subtraction operation and the addition operation, and outputs the subtraction data as the output data Ya.
(n), and the added data is output as output data Yb (n). The third selector 33 has the output register 32.
Also, the output data Ya (n) and Yb (n) are connected to the fixed data "0", and the output data Ya (n) and Yb (n) are replaced with "0" and output. The output of this third selector 33 is
It will be the final encoded output.

In the above digital filter, the multiplier 25 performs the multiplication of the attenuation coefficient g (m) and the multiplication of the filter coefficient h (k) in a time division manner to separate the input data X (n) from the attenuation processing. The processed output data Ya (n),
Yb (n) is generated. The attenuation circuit 11a is realized by multiplication of the attenuation coefficient g (m), and QMF is performed from multiplication of the filter coefficient h (k) to addition / subtraction of the intermediate data A (n) and B (n).
The circuit 11b is realized. Then, the third selector 33
Thus, the replacement circuit 11c is realized.

FIG . 3 is a timing chart for explaining the operation of the digital filter shown in FIG. 1 when the number of taps N is "4", and shows when n = 4. First, the first selector 23 selects the input data X (n), and the second selector 24 selects the attenuation coefficient g (m).
Is selected. In this state, input data X
When (8) is input, the multiplier 25 multiplies the input data X (8) by the attenuation coefficient g (1), and the multiplied data x (8) (= X (8) · g ( 1))
Is written in the RAM 21 as attenuation input data. Here, the attenuation coefficient g (1) determines the degree of attenuation with respect to the input data X (n).
Usually, it is fixed to a fixed value. Then, when the writing of the attenuation input data x (8) to the RAM 21 is completed, the first selector 23 is switched to the attenuation input data x (8) side (RAM 21 side), and at the same time, the second selector 24. Is the filter coefficient h (k) side (ROM 22 side)
Is switched to.

The data separation process by the digital filter is performed on the attenuated input data x (8) stored in the RAM 21. That is, the input data X (n) is replaced with the attenuation input data x (n), the number of taps N = 4, and the equation (9) and the equation
The arithmetic processing according to the following equations (13) and (14) obtained by calculating (10) is executed.

[0049]

[Equation 13]

[0050]

[Equation 14]

In FIG. 3, input data X (0) to X (7)
Although not shown in the drawing for writing, the input data X (0) to X (7) are input before the input data X (8) and are multiplied by the attenuation coefficient g (1). The attenuation input data x (0) to x (7) are stored in the RAM 21. Regarding the first and second selectors 23 and 24, input data X (0) to X (7) and attenuated input data x (0) to
It is switched according to the multiplication processing with x (7).

First, the RAM 21 to the first selector 2
When the attenuated input data x (8) is read out through 3 and the corresponding filter coefficient h (0) is read out from the ROM 22 through the second selector 24, these are multiplied by the multiplier 25, and the multiplied data Is cumulative adder 2
6 is supplied. At this time, the data of the cumulative adder 26 has been cleared, and the multiplication value of the attenuation input data x (8) and the filter coefficient h (0) becomes A (1) = h (0) x (8). The data is stored in the register 28 as it is.
Then, from the RAM 21, the attenuation input data x (6), x
(4) and x (2) are sequentially read, and the ROM 2
The filter coefficients h (2), h (4), and h (6) are sequentially read from 2 and multiplied by the multiplier 25, and the respective multiplication data are sequentially supplied to the cumulative adder 26. In the cumulative adder 25, the input multiplication data are cumulatively added, and A (2) = h (2) · x (6) + A (1) A (3) = h (4) · x (4) + Data of A (2) A (4) = h (6) · x (2) + A (3) are sequentially stored in the register 28. And
Finally stored, A (4) = h (0) .x (8) + h (2) .x (6) +
The data of h (4) · x (4) + h (6) · x (2) is stored in the first register 29.

Subsequently, when the attenuation input data x (7) is read from the RAM 21 through the first selector 23 and the filter coefficient h (1) is read from the ROM 22 through the second selector 24 correspondingly, These are multiplied by the multiplier 25, and the multiplication data is supplied to the cumulative adder 26. At this time, the register 28 of the cumulative adder 26 is cleared, and the multiplication value of the attenuation input data x (7) and the filter coefficient h (1) is B (1) = h (1) · x (7) Data is stored in the register 28 as it is.
Then, from the RAM 21, the attenuation input data x (5), x
(3) and x (1) are sequentially read, and the ROM 2
The filter coefficients h (3), h (5), and h (7) are sequentially read from 2, and the respective multiplication data are sequentially supplied to the cumulative adder 26. Therefore, B (2) = h (3) * x (5) + B (1) B (3) = h (5) * x (3) + B (2) B (4) = h (7) * The data x (1) + B (3) is sequentially stored in the register 28. And
Finally stored, B (4) = h (1) .x (7) + h (3) .x (5) +
The data h (5) · x (3) + h (7) · x (1) is stored in the second register 30 .

Then, the data A (4) and B (4) are input to the adder / subtractor 31 from the first register 29 and the second register 30 , respectively, and the data A (4) and the data B are input.
(4) is added, and further, data B (4) is subtracted from data A (4). The addition data of the adder / subtractor 31, that is, A (4) + B (4) = h (6) · X (2) + h (4) ·
X (4) + h (2) ・ X (6) + h (0) ・ X (8) +
h (7) ・ X (1) + h (5) ・ X (3) + h (3) ・
X (5) + h (1) · X (7) is stored in the output register 32 as output data Yb (4). In addition, subtraction data, that is, A (4) −B (4) = h (6) · X (2) + h (4) ·
X (4) + h (2) ・ X (6) + h (0) ・ X (8)-
h (7) .X (1) -h (5) .X (3) -h (3).
X (5) -h (1) · X (7) are stored in the output register 32 as output data Ya (4). As a result, the arithmetic processing represented by the equations (13) and (14) is completed.

FIG. 4 is a block diagram showing the configuration of the second digital filter 16a. The adder / subtractor 41 is connected to the decode input and performs a subtraction process and an addition process on the first input data Xa (n) and the second input data Xb (n) input in time series. That is, the first input data Xa (n)
By subtracting the second input data Xb (n) and further adding the first input data Xa (n) and the second input data Xb (n), the addition / subtraction data {Xa (n) ± Xb (n)} is generated. The RAM 42 is connected to the adder / subtractor 41, stores the addition / subtraction data {Xa (n) ± Xb (n)} for a predetermined period of time, and sequentially reads and outputs the data at each step of the arithmetic processing. The ROM 43 stores a plurality of filter coefficients h (k) in advance, reads out a predetermined filter coefficient h (k) corresponding to the value of k that increases for each step, and repeatedly outputs it.
This k matches the k shown in the above equations (11) to (12).

The first selector 44 is connected to the RAM 42 and a register 50 to be described later, and either one of the addition / subtraction data {Xa (n) ± Xb (n)} read from the RAM 42 or the combined data held in the register 50. To output. The second selector 45 is connected to the attenuation input and the ROM 43 and has an attenuation coefficient g
Either (m) or the filter coefficient h (k) read from the ROM 43 is selected and output. The attenuation coefficient g (m) is selected as "0" during the initialization operation of the digital filter 16b. The first and second selectors 44 and 45 are selectively controlled in response to a common selection control signal SC.

The multiplier 46 is connected to the first selector 44 and the second selector 45, and the addition / subtraction data {Xa (n) ± Xb (n)} or the combined data Y (selected by the first selector 44. n) is multiplied by one of the attenuation coefficient g (m) or the filter coefficient h (k) selected by the second selector 45. Here, when the first selector 44 selects the addition / subtraction data {Xa (n) ± Xb (n)}, the second selector 45 selects the filter coefficient h (k), and the first selector 44 selects the composite data. When selecting Y (n), the second selector 45 operates so as to select the attenuation coefficient g (m). Thereby, the multiplier 46 multiplies the addition / subtraction data {Xa (n) ± Xb (n)} by the filter coefficient h (k) or the composite data Y (n) by the attenuation coefficient g (m). I do. Then, the addition / subtraction data {Xa (n) ± Xb (n)}
The multiplication data of the filter coefficient h (k) is supplied to the cumulative adder 47, and the multiplication data of the composite data Y (n) and the attenuation coefficient g (m) is supplied to the output register 51.

The cumulative adder 47 including the adder 48 and the register 49 is connected to the multiplier 46 and cumulatively adds the multiplication result of the multiplier 46 according to the tap number. That is, register 4
The data read from 9 and the multiplication data input from the multiplier 46 are added by the adder 48, and the added data is stored again in the register 49, whereby the multiplication results of the multiplier 46 are cumulatively added. The register 50 is connected to the cumulative adder 47, stores the cumulative addition data of the cumulative adder 47, and supplies it as the combined data Y (n) to the first selector 44. Then, the output register 51 is connected to the multiplier 46, stores the composite data Y (n) and the multiplication data corresponding to the attenuation coefficient g (m), and outputs it as the output data y (n).
The output of this output register 51 is the input data Xa (n), X
Decoded output for b (n).

The above digital filter is based on the multiplier 46.
Is the multiplication of the filter coefficient h (k) and the attenuation coefficient g
The multiplication of (m) and the input data Xa
(N) and Xb (n) are subjected to separation processing and attenuation processing to generate output data y (n). The QMF circuit 16a is realized from addition / subtraction processing of the input data Xa (n) and Xb (n) to cumulative addition of multiplication data, and the attenuation circuit 16b is realized by multiplication of the attenuation coefficient g (m).

FIG. 5 shows that the digital filter shown in FIG.
FIG. 11 is a timing diagram for explaining an operation in the case where the number of taps N is “4” and the filter works as a synthesizing filter, where n = 4. The data synthesizing process by the digital filter is performed by the first and second input data Xa input in time series.
(n), Xb (n). That is, the number of taps N = 4
(11) and (12) are calculated as
5) and the arithmetic processing according to the equation (16) is executed.

[0061]

[Equation 15]

[0062]

[Equation 16]

Input data Xa (4), Xb (4) to the adder / subtractor 41
Is input, first, the input data Xb (4) is subtracted from the input data Xa (4), and the subtracted data {Xa (4) −Xb
(4)} is written in the RAM 42. Although illustration of the subtraction processing of the input data Xa (1) to Xa (3) and Xb (1) to Xb (3) is omitted in FIG. 5, the input data Xa (1) to Xa (3),
Xb (1) to Xb (3) are respectively subtracted by the adder / subtractor 41 in the same manner as the input data Xa (4), Xb (4), etc., and subtracted data {Xa (1) -Xb (1)} to { RA as Xa (3) -Xb (3)}
It is stored in M42.

First, the first selector 44 selects the subtraction data {Xa (n) -Xb (n)}, and the second selector 45 selects the filter coefficient h (k). Here, subtraction data {Xa (4) -Xb from the RAM 42
(4)} is read out, and when the filter coefficient h (0) is read out from the ROM 43 correspondingly, these are multiplied by the multiplier 46 and the multiplication data is supplied to the cumulative adder 47. At this time, the register 49 of the cumulative adder 47 is cleared, and the multiplication value of the subtraction data {Xa (4) -Xb (4)} and the filter coefficient h (0) is A (1) = h (0 ) * {Xa (4) -Xb (4)} is stored as it is. Then RAM
42 subtracted data {Xa (3) -Xb (3)}, {Xa
a (2) -Xb (2)}, {Xa (1) -Xb (1)}
When the filter coefficients h (2), h (4), and h (6) are sequentially read from the ROM 43 while being sequentially read, the multipliers 46 multiply each and the multiplication data is input to the sequential cumulative adder 47. To be done. In the cumulative adder 47,
The input multiplication data is cumulatively added, and A (2) = h (2) · {Xa (3) −Xb (3)} + A
(1) A (3) = h (4) · {Xa (2) -Xb (2)} + A
(2) A (4) = h (6) · {Xa (1) -Xb (1)} + A
The data (3) is sequentially stored in the register 49. And
Finally stored, A (4) = h (0) · {Xa (4) −Xb (4)} + h
(2) · {Xa (3) −Xb (3)} + h (4) · {X
a (2) -Xb (2)} + h (6) · {Xa (1) -X
b (1)} is registered in the register 50 as the composite data Y (8).
Stored in. As a result, the arithmetic processing represented by the above equation (15) is completed.

In the multiplier 46, the subtracted data {Xa (1)
When the multiplication of −Xb (1)} and the filter coefficient h (6) is completed, the first selector 44 is switched to the combined data Y (n) (register 40) side, and the second selector 45 is attenuated. It is switched to the coefficient g (m) side. Then, the combined data Y (8) stored in the register 50 is input to the multiplier 46 through the first selector 44 and is multiplied by the attenuation coefficient g (1) input through the second selector 45. As a result, the multiplication data g (1) · Y (8) is stored in the output register 51 as the output data y (8).

Subsequently, the first input data Xa (4) and the second input data Xb (4) are added by the adder / subtractor 41, and the added data {Xa (4) + Xb (4)} is stored in the RAM 42. Written in. In FIG. 5, input data Xa (1) -Xa (3), Xb (1)-
Although illustration of the addition processing regarding Xb (3) is omitted, the input data Xa (1) to Xa (3), Xb (1) to Xb (3) are input data Xa (4), Xb (4). And the like, the addition data is added by the adder / subtractor 41, and addition data {Xa (1) + Xb (1)} to {Xa (3)
It is stored in the RAM 42 as + Xb (3)}. At this time, the first selector 44 adds the addition data {Xa (n) + Xb
(n)} side (RAM 42 side), and the second selector 4
5 is returned to the filter coefficient h (k) side (ROM 43 side).

Addition data {Xa (4) from RAM 42
+ Xb (4)} is read, and the ROM 4 is correspondingly read.
When the filter coefficient h (1) is read from 3, the multiplier 46 multiplies them and the multiplication data is added to the cumulative adder 4
Input to 7. At this time, the data of the cumulative adder 47 has been cleared, and the addition data {Xa (4) + Xb
The multiplication data of (4)} and the filter coefficient h (1) is stored in the register 49 as it is as data of B (1) = h (1) · {Xa (4) + Xb (4)}.
Then, the addition data {Xa (3) + Xb
(3)}, {Xa (2) + Xb (2)}, {Xa (1)
+ Xb (1)} is read in order and the ROM 43
From which filter coefficients h (3), h (5), and h (7) are sequentially read out, and the respective multiplication data are sequentially accumulated in the adder 46.
Is supplied to. Therefore, B (2) = h (3) · {Xa (3) + Xb (3)} + B
(1) B (3) = h (5) · {Xa (2) + Xb (2)} + B
(2) B (4) = h (7) · {Xa (1) + Xb (1)} + B
The data (3) is sequentially stored in the register 49. Finally stored, B (4) = h (1) · {Xa (4) + Xb (4)} + h
(3) ・ {Xa (3) + Xb (3)} + h (5) ・ {X
a (2) + Xb (2)} + h (7) · {Xa (1) + X
The data b (1)} is stored in the register 50 as the combined data Y (9). As a result, the arithmetic processing represented by the above formula (12) is completed.

In the multiplier 46, the addition data {Xa (1)
When the multiplication of + Xb (1)} and the filter coefficient h (7) is completed, the first selector 44 is switched to the combined data Y (n) (register 40) side, and the second selector 45 is changed to the attenuation coefficient. It is switched to the g (m) side. Then, the combined data Y (9) stored in the register 50 is input to the multiplier 46 through the first selector 44 and is multiplied by the attenuation coefficient g (1) input through the second selector 45. As a result, the multiplication data g (1) · Y (9) is stored in the output register 51 as the output data y (9).

FIG . 6 is a block diagram showing a second embodiment of the audio data compression / expansion apparatus of the present invention. In this figure, the MDCT circuit 12 and the quantization circuit 1
3, the inverse quantization circuit 14 and the IMDCT circuit 15 are shown in FIG.
The same description is omitted here. The second embodiment is different from the first embodiment in that the digital filter 17 operates so as to switch between the audio data separating process and the band data synthesizing process. That is, most of the arithmetic units in the audio data separation process and the band data synthesis process are the same, and only the arithmetic order thereof is different. Therefore, the processes can be switched by the selector switching operation. There is.

The digital filter 17 is the attenuation circuit 17
a, a QMF circuit 17b and a replacement circuit 17c. The attenuating circuit 17a attenuates the input audio data by switching the input and the output, and the QMF circuit 1
The audio data output from the QMF circuit 17b is attenuated and output to the outside. QMF circuit 1
During compression processing, 7b separates audio data input through the attenuation circuit 17a into predetermined frequency bands to generate a plurality of band data, and synthesizes a plurality of band data input from the IMDCT circuit 15. Generate audio data.
The replacement circuit 17c is connected to the band data output of the QMF circuit 17b, and is used during the initialization operation of the QMF circuit 17b.
The band data input from the F circuit 17b is replaced with "0" and output.

In the above audio data compression / decompression device, the attenuation circuit 17 in the digital filter 17 is used.
Since the a and QMF circuits 17b are commonly used for compression processing and separation processing, the circuit scale is significantly reduced. FIG. 7 is a block diagram showing the configuration of the digital filter 17 .

The RAM 61 is connected to a second selector 74, which will be described later, stores time-series data input from the second selector 74 for a predetermined period, and sequentially reads and outputs the data for each step of the arithmetic processing. The ROM 62 stores a plurality of filter coefficients h (k) in advance, and a predetermined filter coefficient h (k) corresponding to the value of k that increases for each step.
Is read and repeatedly output. This k matches the k shown in the above equations (9) to (12).

The third selector 63 is connected to the encode input and the RAM 61, and selects and outputs either the time-series audio data X (n) or the data read from the RAM 61. The fourth selector 64 is connected to the attenuation input and the ROM 62 and has an attenuation coefficient g
(m) or the filter coefficient h read from the ROM 62
Either one of (k) is selected and output. The fifth selector 65 is connected to the third selector 63 and the cumulative adder 67, and is selected by the third selector 63 or the cumulative adder 6
Either one of the cumulative addition data of 7 is selected and output. These third to fifth selectors 63 to 65 are selectively controlled in response to common selection control signals SC1 and SC2.

The multiplier 66 is connected to the fifth selector 65 and the fourth selector 64, and multiplies the selection data of the fifth selector 65 and the selection data of the fourth selector 64. Here, the third selector 63 determines that the audio data X (n)
When selecting, the fourth selector 64 selects the attenuation coefficient g (m), and the third selector 63 selects the RAM 61.
When selecting the data from, the fourth selector 64 operates so as to select the filter coefficient h (k). When the fifth selector 65 selects cumulative addition data, the fourth selector 64 selects the attenuation coefficient g (m), and when the fifth selector 65 selects the selection data of the third selector 63, the fourth selector 64 selects the attenuation coefficient g (m). The fourth selector 64 operates so as to follow the selection operation of the third selector 63. As a result, the multiplier 66 multiplies the data read from the RAM 61 by the filter coefficient h (k), and supplies the multiplication data to the cumulative adder 67. In addition, the multiplier 66
The audio data X (n) input from the encode input is multiplied by the attenuation coefficient g (m) to generate attenuated audio data x (n), and the attenuated audio data Y (n) generated from the cumulative adder 67 is attenuated. Attenuated voice data y by multiplying with coefficient g (m)
generates (n).

The cumulative adder 67 comprises an adder 68 and a register 69, and cumulatively adds the multiplication data input from the multiplier 66 according to the tap number. This cumulative adder 67 is the same as the cumulative adder 26 of FIG. First selector 70
Is connected to the cumulative adder 67 and the decode input, and selects and outputs either the cumulative addition data input from the cumulative adder 67 or the time series band data Xa (n) and Xb (n). First
Register 71 and second register 72 are connected to the first selector 70, and cumulative addition data or band data Xa (n), Xa continuously input from the first selector 70.
b (n) is alternately fetched and stored, and each is output at a predetermined timing. For example, the odd-numbered data A (n) output from the first selector 67 is stored in the first register 71, and the even-numbered data B (n) is stored in the second register 72. The adder / subtractor 73 is connected to the first register 71 and the second register 72, and subtracts or adds the intermediate data A (n) and B (n) read from the registers 71 and 72. The second selector 74 is connected to the adder / subtractor 73 and the multiplier 66, and selects and outputs either the adder / subtractor data input from the adder / subtractor 73 or the multiplication data input from the multiplier 66.

The first output register 75 includes the adder / subtractor 7
3, the addition / subtraction data input from the adder / subtractor 73 is stored every time a predetermined calculation process is completed, and the addition / subtraction data is output as band data Ya (n) and Yb (n). For example, the subtraction data is output as the first band data Ya (n) and the addition data is output as the second band data Yb (n) corresponding to the adder / subtractor 73 that alternately repeats the subtraction operation and the addition operation. The sixth selector 76 is connected to the first output register 75 and the fixed value “0”, and replaces “0” during the initialization operation of the digital filter 17. The output of the sixth selector 76 becomes the final encoded output. The second output register 77 is connected to the multiplier 66, stores the multiplication data output from the multiplier 66 each time a predetermined arithmetic process is completed, and outputs it as the attenuated audio data y (n). The output of the second output register 77 becomes the decode output.

The above digital filter functions as a separation filter when the first selector 70 selects the cumulative addition data of the cumulative adder 67 and the fifth selector 65 selects the selection data of the third selector 63. . As a result, band data Ya (n) and Yb (n) corresponding to the attenuated audio data x (n) obtained by attenuating the audio data X (n) are output from the first output register 75. At this time, the multiplication of the attenuation coefficient g (m) realizes the attenuation circuit 17a, and the multiplication of the filter coefficient h (k) to the addition / subtraction of the intermediate data A (n) and B (n) realizes the QMF circuit 17b. Then, the replacement circuit 17c is realized by the sixth selector 76. Further, when the first selector 70 selects the band data Xa (n) and Xb (n) and the third selector 63 selects the data read from the RAM 61, it functions as a synthesis filter, and the band data Xa
Attenuated voice data y (n) obtained by attenuating the voice data Y (n) for (n) and Xa (n) is output. At this time, the QMF circuit 17b is realized from the addition / subtraction of the band data Xa (n) and Xb (n) to the cumulative addition of the multiplication data, and the multiplication of the attenuation coefficient g (m) is realized as the attenuation circuit 17a.

The separation operation of the digital filter described above matches the operation of the digital filter shown in FIG. In the synthesizing operation, the band data Xa input in time series is used.
After (n) and Xb (n) are stored in the first and second registers 71 and 72, they match the operation of the digital filter shown in FIG.

[0079]

According to the present invention, "0" is output from the digital filter while the digital filter is being initialized. Therefore, it is possible to prevent noise from occurring when the recording operation or the reproducing operation of the audio data is started. Moreover, since the multiplier is commonly used in the QMF circuit and the attenuation circuit, the circuit scale can be reduced, and as a result, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an audio data compression / decompression device of the present invention.

FIG. 2 is a block diagram showing a configuration of a first digital filter shown in FIG.

FIG. 3 is a timing diagram illustrating an operation of the first digital filter of FIG.

FIG. 4 is a block diagram showing a configuration of a second digital filter shown in FIG.

5 is a timing diagram illustrating the operation of the second digital filter of FIG.

FIG. 6 is a block diagram showing a second embodiment of the audio data compression / decompression device of the present invention.

FIG. 7 is a block diagram showing a configuration of the digital filter shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional audio data compression / decompression device.

[Explanation of symbols]

1, 8 Attenuator 2, 7, 11, 16, 17 Digital filter 3, 12 MDCT circuit 4, 13 Quantization circuit 5, 14 Inverse quantization circuit 6, 15 IMDCT circuit 11a, 16b, 17a Attenuation circuit 11b, 16a, 17b QMF circuit 11c, 17c Substitution circuit 21, 42, 61 RAM 22, 43, 62 ROM 23, 24, 33, 44, 45, 63, 64, 65, 7
4, 76 selector 25, 46, 66 multiplier 26, 47, 67 cumulative adder 27, 48, 68 adder 28, 29, 30, 49, 50, 69, 71, 72 register 31, 41, 73 adder / subtractor 32 , 51, 75, 77 output registers

Continuation of the front page (56) Reference JP-A-7-28494 (JP, A) JP-A-2-140020 (JP, A) JP-A-9-27751 (JP, A) JP-A-7-13599 (JP , A) JP 11-220359 (JP, A) JP 11-220403 (JP, A) JP 11-220356 (JP, A) JP 11-220358 (JP, A) JP 11-220357 (JP, A) JP-A-6-216716 (JP, A) JP-A-7-131295 (JP, A) JP-A-6-216715 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 3/00-11/00 H03H 17/02

Claims (4)

(57) [Claims] 1. Audio data is separated for each predetermined frequency band.
Then, encode processing is performed for each band to generate compressed data.
Of the frequency band read from the recording medium.
Each of the compressed data is decrypted and combined with each other.
Audio data compression / decompression device for generating audio data
A location, a plurality of bands by separating the audio data into a plurality of frequency bands
A first digital filter for generating band data, and
The multiple band data generated by one digital filter
Encoding time that encodes data in time series to generate compressed data.
Channel and multiple compressed data read from a given recording medium.
Decoding circuit for decoding data to generate multiple band data
And the plurality of band data generated by the decoding circuit
Second digital file that synthesizes audio to generate audio data
And the first digital filter is
Replacement means for selectively replacing a number of band data with "0"
, And the above encoding circuit during the initialization operation of the compression process.
In addition to supplying “0” to the second digital flag,
The filter is an attenuator that attenuates and outputs the audio data.
During the initialization operation of the decompression process,
A sound data compression / decompression device that attenuates to "0"
In the first digital filter, time-series input data and attenuation input data generated based on the time-series input data are input together with a predetermined attenuation coefficient and a filter coefficient corresponding to the attenuation input data. A selector that selects either one of the set of time-series input data and the predetermined attenuation coefficient or the set of attenuation input data and the filter coefficient, and a multiplier that multiplies the set of selection data of the selector with each other. A RAM for storing the operation result of the multiplier for the set of the time series input data and the predetermined attenuation coefficient and supplying it to the selector as the attenuated input data, and the RAM corresponding to the set of the attenuated input data and the filter coefficient. The accumulator that sequentially accumulates the calculation results of the multiplier and the calculation result of the above accumulator are alternately taken. No first and second registers, the first
And an adder / subtractor for adding or subtracting two operation results fetched from the second register, wherein the operation result of the adder / subtractor is the separated data of the input time series data. To output as data
Characteristic audio data compression / decompression device. 2. Audio data is separated for each predetermined frequency band.
Then, encode processing is performed for each band to generate compressed data.
Of the frequency band read from the recording medium.
Each of the compressed data is decrypted and combined with each other.
Audio data compression / decompression device for generating audio data
A location, a plurality of bands by separating the audio data into a plurality of frequency bands
A first digital filter for generating band data, and
The multiple band data generated by one digital filter
Encoding time that encodes data in time series to generate compressed data.
Channel and multiple compressed data read from a given recording medium.
Decoding circuit for decoding data to generate multiple band data
And the plurality of band data generated by the decoding circuit
Second digital file that synthesizes audio to generate audio data
And the first digital filter is
Replacement means for selectively replacing a number of band data with "0"
, And the above encoding circuit during the initialization operation of the compression process.
In addition to supplying “0” to the second digital flag,
The filter is an attenuator that attenuates and outputs the audio data.
During the initialization operation of the decompression process,
A sound data compression / decompression device that attenuates to "0"
Te, the second digital filter includes a subtracter for adding or subtracting the first and second time series input data, a RAM for storing the subtraction data obtained from the adder-subtracter, read out from the RAM Addition / subtraction data and composite data corresponding to each addition / subtraction data are input together with a filter coefficient corresponding to the addition / subtraction data and a predetermined attenuation coefficient, and a set of the addition / subtraction data and the filter coefficient or a combination of the combination data and the attenuation coefficient is input. A selector that selects one of the sets, a multiplier that multiplies the selection data set of the selector with each other, and a cumulative data that sequentially adds the multiplication data of the multiplier corresponding to the addition / subtraction data and the filter coefficient set. The adder and the calculation result of this cumulative adder are fetched and supplied to the selector as the combined data. It includes a register, and a being to output the multiplication data of the multiplier corresponding to said set of synthetic data and the attenuation coefficient as output data to be the first and second time series input data combined data An audio data compression / decompression device for performing. 3. Audio data is separated for each predetermined frequency band, compression processing is performed for each band to generate compressed data, and the compressed data is decoded into a plurality of compressed data for each frequency band read from a recording medium. An audio data compression / decompression device that performs audio processing and synthesizes each other to generate audio data, wherein the audio data is separated into a plurality of frequency bands to generate a plurality of band data, and a plurality of band data is generated. A digital filter for synthesizing audio data to generate audio data, an encoding circuit for time-sequentially encoding the plurality of band data generated by the digital filter to generate compressed data, and a plurality of data read from a predetermined recording medium. A decoding circuit which decodes the compressed data of to generate a plurality of band data and supplies the band data to the digital filter, , A replacement means for selectively replacing the plurality of band data to be output with “0” and an attenuating means for attenuating and outputting the audio data to be output, and to the encoding circuit during the initialization operation of the compression process. An audio data compression / decompression device which supplies "0" to the audio data and attenuates the audio data to "0" during the initialization operation of the expansion process. 4. The digital filter comprises a RAM for sequentially storing time-series data, a multiplier for multiplying the data read from the RAM by a predetermined filter coefficient, and a cumulative sum for accumulating operation results of the multiplier. Alternately, an adder, a first selector for selecting the calculation result of the cumulative adder in the separation process, and a first selector for selecting the first and second band data in the combining process, and the selection data of the selector alternately. First to capture
And a second register, an adder / subtractor for adding or subtracting two data fetched from the first and second registers, a calculation result of the adder / subtractor at the time of separation processing, and at the time of synthesis processing. Select voice data and select RA
A second selector for supplying to M, the audio data is multiplied by a predetermined attenuation coefficient by the multiplier and stored in the RAM, and the calculation result of the adder / subtractor is output as band data for the audio data. 5. The audio according to claim 3 , wherein the multiplication result of the cumulative adder is multiplied by a predetermined attenuation coefficient by the multiplier, and the result is output as audio data for the first and second band data. Data compression / decompression device.