JP3485498B2 - CDMA receiver and path search method therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDMA (Code Division Multiple A) using a spread spectrum communication system.
TECHNICAL FIELD The present invention relates to a receiver for code division multiple access) and a path search method thereof, and more particularly to a receiver for CDMA and a path search method thereof that can reduce power consumption.

[0002]

2. Description of the Related Art CDM using spread spectrum communication system
2. Description of the Related Art A (Code Division Multiple Access) receivers have become widespread and are applied to mobile telephone devices and the like. In the spread spectrum communication method, information symbols indicating information to be transmitted are PN (Pseudo Noise) series or Go.
Direct spread (DS) that spreads the power spectrum by being multiplied by a spread code such as an ld code.
uence) method. The signal spread by this direct spreading method is sent to the CDMA receiver by a radio signal, and the CDMA receiver demodulates the baseband signal from the radio signal and then performs a correlation calculation between the baseband signal and the spread code. By executing (despreading), the transmitted information is extracted.

At this time, when a multipath having a plurality of radio signal propagation paths occurs due to reflection of the radio signal on a mountain or a building, fading occurs and the waveform of the radio signal is distorted and transmitted. Information may not be retrieved correctly. In order to cope with such fading due to multipath, some CDMA receivers are equipped with a device called a RAKE receiver.

The RAKE receiver obtains the timing for starting the correlation calculation and the reception level for each path of the received radio signal, and performs despreading according to each path using a plurality of correlators. The RAKE receiver amplifies (rakes) a data signal obtained by despreading using a plurality of correlators according to the reception level of each path.
Thus, the transmitted information is taken out.

As a technique for obtaining the timing for starting the correlation calculation and the reception level, a technique using pilot symbols spread by a known spreading code is known and is called a pilot system. The pilot symbol is transmitted from the base station of the wireless communication system using a communication channel different from the communication channel for transmitting normal information symbols.

In this pilot method, the RAKE receiver obtains a large number of correlation values between pilot symbols and spread codes while changing the start position of the correlation calculation, and creates a delay profile showing variations in received signal power. And RA
The KE receiver specifies the delay time at which the received signal power indicated by the delay profile becomes a value larger than a predetermined reference value, as the position of an effective path.

As a technique using such a pilot method, Japanese Patent Laid-Open No. 10-112673 discloses a technique for operating a matched filter only when a pilot symbol is received to obtain a correlation value, thereby reducing power consumption. Is disclosed.

In situations where multipath occurs, CDMA
Since the propagation path of each path changes as the position of the reception device moves, it is necessary to identify the position of the effective path periodically.

[0009]

However, the above-mentioned Japanese Unexamined Patent Application Publication No.
In the technique disclosed in Japanese Patent Laid-Open No. 0-112673, a delay profile of one symbol time is created every time a pilot symbol is received.

Here, assuming that the diameter of the range covered by one cell is about 5 to 10 km, when a delay profile of one symbol time is created, up to the correlation value in the range where no path is considered to exist. It seems that they are also seeking. For example, so-called W-CDMA (Wideband Cod)
In the e Division Multiple Access system, the chip rate is 4.096 megachips per second, and the delay corresponding to one chip time is caused by the propagation path length difference of about 70 m. Further, according to this W-CDMA system, the spreading ratio is 256. That is, one symbol is spread by the spreading code of 256 chips. From this, the delay corresponding to one symbol time is about 18k.
This is caused by the difference in the propagation path length of m.

Therefore, when the position of the effective path is specified periodically, the timing at which the correlation between the baseband signal and the spread code starts is changed unless the CDMA receiver changes the position very rapidly. do not do. That is, in many cases, in order to create a delay profile of one symbol time, it is considered that a correlation value in a wide range where no path exists is obtained.

A matched filter is used to obtain the correlation value between the baseband signal and the spread code. However, since the matched filter consumes a lot of power,
Obtaining the correlation value in the range where no path exists consumes a large amount of power unnecessarily.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a CDMA receiver and a path search method therefor capable of reducing power consumption.

[0014]

In order to achieve the above object, a CDMA receiver according to a first aspect of the present invention uses a pilot symbol while delaying a baseband signal obtained by receiving and demodulating a radio signal. Correlation calculation executing means for executing a correlation calculation with a spreading code to be spread, integration means for calculating a received signal power by integrating a result of the correlation calculation executed by the correlation calculation executing means, and a reception signal calculated by the integrating means. Profile storing means for storing a delay profile created from electric power; and, when creating the delay profile, causes the correlation operation executing means to execute a correlation operation within a delay time width shorter than one symbol time, and the integrating means It is determined whether or not the obtained received signal power is higher than a predetermined reference value. Means for storing the delay profile, stopping the operation of the correlation calculation executing means, and determining that the received signal power is equal to or less than the reference value, the correlation calculation executing means for performing the correlation calculation in a longer delay time range. And an operation control means for executing the delay profile to create a delay profile.

According to the present invention, the operation control means, when creating the delay profile, causes the correlation operation executing means to execute the correlation operation in the range of the delay time width shorter than one symbol time to create the delay profile. If there is a valid path within the range, the delay profile is stored in the profile storage means and the operation of the correlation calculation execution means is stopped.
As a result, the operation of the correlation calculation executing means can be suppressed and power consumption can be reduced.

Further, it is desirable that the operation control means creates a delay profile of one symbol time when the power is turned on. Thereby, when receiving information from the base station thereafter, it is possible to cause the correlation calculation executing means to execute the correlation calculation within a delay time width shorter than one symbol time based on the delay profile.

There is a high possibility that there is an effective path in the vicinity of the delay time at which the received signal power shown in the delay profile becomes maximum. Therefore, the operation control means reads the delay profile stored in the profile storage means, and performs the correlation calculation within a predetermined delay time width range centered on the delay time at which the received signal power becomes maximum. The correlation calculation execution means is caused to execute, and it is judged whether or not the received signal power obtained by the integration means is larger than the reference value. If it is judged that it is larger, the delay profile is stored in the profile storage means and the correlation calculation is executed. When the operation of the means is stopped and it is determined that the received signal power is less than or equal to the reference value, the range in which the correlation calculation executing means executes the correlation calculation is extended by delaying by the same time width as the predetermined delay time width. You may create a profile. As a result, it is possible to efficiently detect an effective path, suppress the operation of the correlation calculation executing means, and reduce the power consumption.

Further, the operation control means reads the delay profile stored in the profile storage means, and within a delay time width range defined by a plurality of delay times at which the received signal power becomes larger than the reference value. Correlation calculation is executed by the correlation calculation execution means, and it is judged whether or not the received signal power obtained by the integration means is larger than the reference value. If it is judged that it is larger, the delay profile is stored in the profile storage means. When the operation of the correlation calculation executing means is stopped and it is determined that the received signal power is equal to or lower than the reference value, the range in which the correlation calculation executing means executes the correlation calculation may be extended to create the delay profile. Even in this case, the effective path can be detected efficiently, the operation of the correlation calculation executing means can be suppressed, and the power consumption can be reduced.

More specifically, when the operation control means determines that the received signal power obtained by the integration means is equal to or less than the reference value, the operation control means reads the delay profile stored in the profile storage means and receives the received signal. Within the delay time range specified by the delay time when the power is not zero,
You may make the said correlation calculation execution means perform a correlation calculation.

When the operation control means determines that the received signal power obtained by the integration means is less than or equal to the reference value, the operation control means reads the delay profile stored in the profile storage means, and the delay profile is smaller than the reference value. The correlation calculation execution means may execute the correlation calculation within a delay time width range defined by the delay time at which the received signal power becomes larger than the reference value of 2.

It is considered that a path having a large number of reflections has a large attenuation, and a delay time amount becomes larger than that of a path having the largest received signal power. Therefore, the operation control means reads the delay profile stored in the profile storage means, and executes the correlation calculation in the range from the delay time at which the received signal power becomes maximum to a time delayed by a predetermined time. The means may be executed to create the delay profile. As a result, it is possible to efficiently detect an effective path, suppress the operation of the correlation calculation executing means, and reduce the power consumption. Further, it is preferable that the correlation calculation executing means executes the correlation calculation by a matched filter.

A CD according to the second aspect of the present invention
The path search method of the MA receiver uses a matched filter to perform a correlation calculation with a spreading code that spreads pilot symbols while delaying a baseband signal within a delay time width shorter than one symbol time. And an integration step of integrating the calculation result in the correlation calculation step to obtain a received signal power to create a delay profile, and a check is made as to whether the received signal power obtained in the integration step is larger than a predetermined reference value. If it is determined that the received signal power is higher than the reference value in the determination step and the determination step, the despreading for extracting the data signal is executed because there is an effective path, and the delay created in the integration step is executed. Store the profile in memory and stop the matched filter operation to end the path search. And flop, receiving signals at said determination step
If it is determined that the signal power is less than the reference value, the correlation
Correlation over longer delay time due to computational steps
An arithmetic control switch that performs arithmetic to create a delay profile.
And a step .

According to the present invention, in the correlation calculation step, the correlation calculation is executed within the delay time width shorter than one symbol time, and the calculation result is integrated in the integration step to obtain the received signal power. The determining step determines whether or not the received signal power is higher than a predetermined reference value, and the search end step determines that the received signal power is higher than the reference value in the determining step, and determines that there is an effective path. The despreading is performed to extract the delay profile and the delay profile is stored in the memory to stop the operation of the matched filter. Further, the arithmetic control step is the determination step.
Determines that the received signal power is less than or equal to the reference value.
With the correlation calculation step,
Create a delay profile by performing a range correlation operation.
Let This makes it possible to suppress the operation of the matched filter and reduce the power consumption.

The correlation calculation step may also include a step of reading the delay profile stored in the memory and executing a correlation calculation within a predetermined range centered on the delay time at which the received signal power becomes maximum. Good.
As a result, it is possible to efficiently detect an effective path, suppress the operation of the matched filter, and reduce power consumption.

In the correlation calculation step, the delay profile stored in the memory is read, and the correlation calculation is executed within a delay time width range defined by a plurality of delay times at which the received signal power becomes larger than the reference value. Steps may be included. As a result, it is possible to efficiently detect an effective path, suppress the operation of the matched filter, and reduce power consumption.

The correlation calculation step may also include a step of reading the delay profile stored in the memory and executing a correlation calculation within a range from a delay time at which the received signal power becomes maximum to a time delayed by a predetermined time. Good.
As a result, it is possible to efficiently detect an effective path, suppress the operation of the matched filter, and reduce power consumption.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION A CDMA (Code Division Multiply) according to an embodiment of the present invention will be described below with reference to the drawings.
le Access; code division multiple access) will be described in detail. FIG. 1 shows a C according to an embodiment of the present invention.
It is a figure which shows the structure of the receiver 100 for DMA typically. As shown, this CDMA receiver 100
Is composed of a radio demodulation unit 10, a RAKE processing unit 11, a data processing unit 12, and an antenna 13.

The radio demodulation unit 10 includes a quadrature detector and an LPF.
(Low Pass Filter) and the like, and is for demodulating a baseband signal from a radio signal received by the antenna 13.

The RAKE processing unit 11 is for despreading the baseband signal demodulated by the radio demodulation unit 10 while compensating for the phase and the amplitude according to the situation of multipath generation, and as shown in FIG. A matched filter 20, a level adjuster 21, an integrator 22, a control circuit 23, a plurality of PN (Pseudo Noise) correlators 24, a RAKE combiner 25, and a memory 26.

Matched filter 20 is composed of a delay element, a weighting tap, an adder and the like, and is for performing a correlation calculation between the baseband signal received from radio demodulation section 10 and the spread code for pilot symbols. . here,
The pilot symbol is a predetermined code pattern that is spread by a known spreading code and sent, and the matched filter 20 uses the same spreading code as that used for spreading the pilot symbol on the transmission side of the radio signal. keeping. Then, the matched filter 20 performs a correlation operation between the pilot symbol and the spread code while delaying the baseband signal by a predetermined time (for example, 1 chip time), and outputs the pulse train obtained as the operation result to the level adjuster 21. send.

The level adjuster 21 is composed of a delay element, a multiplier and the like, and is for adjusting the signal level of the pulse train received from the matched filter 20, and the pulse train having the adjusted signal level is supplied to the integrator 22. send.

The integrator 22 is for cyclically integrating the pulse train received from the level adjuster 21 to obtain the received signal power, and notifies the control circuit 23 of the obtained received signal power.

The control circuit 23 is composed of a microprocessor or the like and controls the operation of each part of the RAKE processing section 11. More specifically, the control circuit 23
Receives the notification of the received signal power from the integrator 22, creates a delay profile, and stores it in the memory 26. The delay profile indicates the power characteristic of the received signal when the start position of the correlation calculation between the pilot symbol and the spread code is changed. As illustrated in FIG. 3, the delay time of the pilot symbol and the integrator are used. 22 is the received signal power obtained by performing cyclic integration.

Further, the control circuit 23 compares the received signal power received from the integrator 22 with a predetermined reference value L1 and receives the delay time when the received signal power becomes a value larger than the reference value L1 on the reception of the effective path. It is determined that it is timing. And
The control circuit 23 specifies the delay time indicating the timing at which the matched filter 20 executes the correlation calculation to obtain the value of the received signal power, and the received signal power at that time.
Further, the control circuit 23 creates a parameter for performing despreading of the baseband signal received by one of the plurality of PN correlators 24 from the valid path from the specified delay time and the received signal power. This parameter is PN
The data includes a delay time for the correlator 24 to temporally compensate the phase of the baseband signal and a weighting factor (amplification factor) according to the reliability of the effective path.

Further, the control circuit 23 switches between starting and stopping the matched filter 20. Here, the control circuit 2
When the CDMA receiver 100 is powered on or moves from the outside of the communication service area to the inside of the communication service area 3, the matched filter 20 is provided until a delay profile of one symbol time is created.
To operate the correlation calculation. On the other hand, the control circuit 2
3 is the matched filter 20 periodically when the CDMA receiver 100 receives information symbols from the base station.
To operate the correlation calculation. At this time, the control circuit 23 checks the received signal power in units of delay time width shorter than one symbol time, and if an effective path is found in this range, stops the operation of the matched filter 20 at that time.

The plurality of PN correlators 24 is composed of a shift register, a PN sequence generator, a multiplier, etc., and inverses the baseband signal received from the radio demodulation unit 10 according to the parameter set by the control circuit 23. The data signal is extracted by spreading. Here, the PN correlator 24 temporally phase-compensates and despreads the baseband signal received from the wireless demodulation unit 10 with the delay time indicated by the parameter set by the control circuit 23. Further, the PN correlator 24 adjusts the data signal obtained by despreading to a signal level according to the weighting frequency (amplification factor) indicated by the parameter set by the control circuit 23, and sends it to the RAKE combiner 25.

The RAKE combiner 25 is composed of an adder and the like, and is for combining the data signals received from the plurality of PN correlators 24, and sends the combined data signals to the data processing unit 12.

The memory 26 is composed of a semiconductor memory or the like, and is a profile storage unit for storing the delay profile created by the control circuit 23.

The data processing unit 12 of FIG. 1 is composed of a decoder, a speaker, etc., decodes the data signal received from the RAKE processing unit 11, and outputs a voice signal in accordance with the information obtained by the decoding. It is for executing various processes.

The CD according to the embodiment of the present invention will be described below.
The operation of the MA receiver 100 will be described. This CDMA
The receiver device 100 is applied to a mobile telephone device or the like and functions as a device for receiving a downlink signal, and when searching for a position of a cyclically effective path, a delay time width shorter than one symbol time is used. By creating a delay profile for each range of and suppressing the operation of the matched filter 20,
Power consumption can be reduced.

The CDMA receiver 100 is controlled by the control circuit 2 when the power is turned on by pressing a power key (not shown).
3 creates a delay profile of 1 symbol time.
Here, since it is immediately after the power is turned on, a delay profile of one symbol time is created.

More specifically, when the power is turned on, the control circuit 23 starts the power-on search process shown in the flowchart of FIG. When the power-on search process is started, the control circuit 23 activates the matched filter 20 (step S1) and executes the correlation calculation between the baseband signal demodulated by the radio demodulation unit 10 and the spread code for pilot symbols. (Step S2). At this time, the matched filter 20 executes the correlation calculation while sequentially delaying the baseband signal by one chip time until the pilot symbol is despread and a pulse train of one symbol time is obtained. The matched filter 20 sends the pulse train obtained by the correlation calculation to the level adjuster 21.

The level adjuster 21 includes the matched filter 2
Adjust the signal level of the pulse train received from 0 to integrator 2
Send to 2. The integrator 22 cyclically integrates the signal level received from the level adjuster 21 to obtain the received signal power (step S3), and notifies the control circuit 23.

The control circuit 23 receives the notification of the received signal power from the integrator 22, creates a delay profile, compares the received signal power with a predetermined reference value L1, and determines that the received signal power is larger than the reference value L1. Is determined (step S4).

In the control circuit 23, the received signal power is the reference value L.
If it is determined that the value is larger than 1 (YES in step S4), it is determined that there is a valid path, and the value indicates the position of the valid path (step S5). And
The control circuit 23 determines a plurality of Ps from the delay time and the received signal power at which the value of the received signal power indicating the position of the effective path exists.
A parameter for despreading the baseband signal of the effective path is created in one of the N correlators 24. This parameter is data including a delay time for the PN correlator 24 to compensate the phase of the baseband signal and a weighting factor (amplification factor) according to the reliability of the effective path.

The control circuit 23 sets the created parameter in one of the plurality of PN correlators 24 to prepare for despreading the baseband signal demodulated by the radio demodulation unit 10 (step S6).

On the other hand, when the control circuit 23 determines in step S4 that there is no value larger than the reference value L1 (NO in step S4), it determines that there is no valid path (step S7), and the steps S5 and S6 are performed. Processing is skipped and the processing proceeds to step S8.

The control circuit 23 determines whether or not the delay profile of one symbol time is completed (step S
8) If it is determined that the delay profile is not completed (NO in step S8), the process returns to step S2 to continue creating the delay profile.

On the other hand, when the control circuit 23 determines that the delay profile for one symbol time is completed (step S
8 is YES), the operation of the matched filter 20 is stopped (step S9), and the created delay profile is stored in the memory 26 (step S10). The delay profile stored in the memory 26 is used to specify the position of the path thereafter when receiving information from the base station, and the control circuit 23 uses the delay profile based on this delay profile. It is possible to execute the correlation calculation in units of delay time width shorter than 1 symbol time.

After that, the control circuit 23 controls the PN correlator 24.
To despread the baseband signal received from the wireless demodulation unit 10 to extract a data signal (step S
11). The PN correlator 24 extracts the data signal
The signal is amplified to a signal level according to the parameter set by the control circuit 23 and sent to the RAKE combiner 24.

The RAKE combiner 25 combines the data signals received from the PN correlator 24 (step S12) and sends them to the data processor 12. As a result, the CDMA receiver 100 despreads and collects the baseband signal for each path even in the situation where multipath occurs (RA
By performing KE), an appropriate information symbol can be extracted.

In this way, the CDMA receiver 10
0 can take out information symbols such as call symbols from the base station and receive information from the base station.

Next, when the CDMA receiver 100 starts to receive information from the base station, the control circuit 23 repeats the flowchart of FIG. 5 every time a predetermined time elapses (time interval for receiving pilot symbols). The 1 / M symbol search process shown in is started.

In this 1 / M symbol search processing, a delay profile is created in units of 1 / M symbol time, and if there is no valid path in this range, the range in which the delay profile is created is sequentially incremented by 1 / M symbol time. This is an expanding process. Here, M that defines the unit of the range in which the delay profile is created is a predetermined constant value.

When the control circuit 23 starts the 1 / M symbol search processing, it initializes a variable i defining the range in which the delay profile is created as 1 (step S20).
The matched filter 20 is activated (step S21).

Next, the control circuit 23 controls the matched filter 20 to execute the correlation operation between the baseband signal of the i / M symbol time defined by the variables i and M and the spread code (step S21). S22). At this time, the control circuit 2
3 reads the delay profile stored in the memory 26, and executes the correlation calculation within the range of i / M symbol time with the path having the largest received signal power in the delay profile as the center.

For example, when the variable i is 1, it is assumed that the delay profile stored in the memory 26 indicates the maximum value P1 of the received signal power at the delay time t1, as shown in FIG. Since the received signal power is the largest at the delay time t1, the control circuit 23 causes the matched filter 20 to perform the correlation calculation within the range of 1 / M symbol time centering on the delay time t1.

The matched filter 20 sends the pulse train generated by performing the correlation calculation to the level adjuster 21, and the level adjuster 21 adjusts the signal level of the pulse train and sends it to the integrator 22. The integrator 22 cyclically integrates the signal level received from the level adjuster 21 to obtain the received signal power, and notifies the control circuit 23 of the received signal power.

The control circuit 23 receives the notification of the received signal power from the integrator 22, creates a delay profile, compares the received signal power with a predetermined reference value L1, and determines that the received signal power is larger than the reference value L1. Is determined (step S23).

The control circuit 23 determines that the received signal power is the reference value L.
If it is determined that the value is larger than 1 (YES in step S23), it is determined that there is an effective path, and the baseband signal of the effective path is detected by the PN correlator 24 from the delay time and the received signal power in which the value exists. Create parameters for despreading.

The control circuit 23 sets the created parameter in one of the PN correlators 24 and despreads the baseband signal demodulated by the radio demodulation unit 10 (step S24).

After that, the control circuit 23 stops the operation of the matched filter 20, stores the created delay profile in the memory 26, and ends the 1 / M symbol search process (steps S25 and S26).

On the other hand, when the control circuit 23 determines in step S23 that there is no value larger than the reference value L1 (NO in step S23), the variable i is incremented by 1 (step S27), and the variable i becomes larger than M. It is determined whether it is larger (step S28).

When the control circuit 23 determines that the variable i is equal to or less than M (NO in step S28), the process returns to step S22 and continues to create the delay profile.

On the other hand, when the control circuit 23 determines that the variable i is larger than M (YES in step S28), it determines that the delay profile of one symbol time is completed,
The process proceeds to step S25, the operation of the matched filter 20 is stopped, the created delay profile is stored in the memory 26, and the 1 / M symbol search process is ended.

According to this 1 / M symbol search processing, the control circuit 23 creates a delay profile in units of the delay time width of 1 / M symbol time, and there is an effective path within the range in which the delay profile is created. If it is determined that the operation of the matched filter 20 is stopped. This suppresses the operation of the matched filter 20. Since the matched filter 20 consumes a large amount of power, by suppressing the operation of the matched filter 20, the CDMA receiver 100 can reduce the power consumption.

When the control circuit 23 determines that there is an effective path within the range in which the delay profile is created, the control circuit 23 stores the delay profile in the memory 26 and ends the 1 / M symbol search process. The process for searching can be shortened, and information from the base station can be quickly received.

The CDMA receiver 100 according to the first embodiment described above creates a delay profile in units of 1 / M symbol time, but creates a delay profile according to the delay profile stored in the memory. The range may be changed. Hereinafter, the CDMA according to the second embodiment of the present invention in which the range for creating the delay profile is changed according to the delay profile stored in the memory.
The reception device for use will be described.

CDM according to the second embodiment of the present invention
The A receiver is the CDMA according to the first embodiment.
The receiver has the same configuration as the receiver 100.

When the power is turned on, the control circuit 23 executes the power-on search processing as in the first embodiment, creates a delay profile of one symbol time, and stores it in the memory 26. To do. After this, the control circuit 23
When the CDMA receiver 100 starts receiving information from the base station, the flexible search process shown in the flowchart of FIG. 7 starts every time a predetermined time elapses.

When the flexible search process is started, the control circuit 23 reads the delay profile stored in the memory 26 and predicts the range in which a valid path exists (step S30). At this time, the control circuit 23 predicts the range of the delay time width defined by a plurality of delay times in which the received signal power indicated by the delay profile becomes larger than the reference value L1 as the range in which an effective path exists.

For example, in the delay profile shown in FIG. 8, if the value of the received signal power generated at the delay times t10, t11, and t12 is larger than the reference value L1, the control circuit 23 determines that the delay time is t10. The range between t12 and t12 is predicted as a range in which a valid path exists.

The control circuit 23 activates the matched filter 20 (step S31), and executes the correlation calculation between the baseband signal and the spread code in the range predicted to have an effective path in step S30 (step S32). ).

The matched filter 20 sends the pulse train generated by performing the correlation calculation to the level adjuster 21, and the level adjuster 21 adjusts the signal level of the pulse train and sends it to the integrator 22. The integrator 22 cyclically integrates the signal level received from the level adjuster 21 to obtain the received signal power, and notifies the control circuit 23 of the received signal power.

The control circuit 23 receives the notification of the received signal power from the integrator 22, creates a delay profile, compares the received signal power with a predetermined reference value L1, and determines that the received signal power is larger than the reference value L1. Is determined (step S33).

The control circuit 23 determines that the received signal power is the reference value L.
If it is determined that the value is greater than 1 (YES in step S33), it is determined that there is an effective path, and the baseband signal of the effective path is determined by the PN correlator 24 from the delay time and the received signal power in which the value exists. Create parameters for despreading.

The control circuit 23 sets the created parameter in one of the plurality of PN correlators 24 and despreads the baseband signal demodulated by the radio demodulation unit 10 (step S34).

After that, the control circuit 23 stops the operation of the matched filter 20, stores the created delay profile in the memory 26, and ends the flexible search process (steps S35 and S36).

On the other hand, when the control circuit 23 determines in step S33 that there is no value larger than the reference value L1 (NO in step S33), a new valid path is generated within the range in which the delay profile has not been created yet. The range in which is present is predicted (step S37). At this time, the control circuit 23
Read the delay profile stored in the memory 26,
A range in which a path is predicted to exist is defined outside the range in which the delay profile has already been created in step S33.

For example, the control circuit 23 uses the above step S
The range in which an effective path exists is defined based on the delay time in which the received signal power is larger than the second reference value L2 smaller than the reference value L1 outside the range in which the delay profile is already created in 33. And specify the effective path delay time. Then, the control circuit 23 predicts the delay time width from the specified delay time to the delay time that is the end of the range in which the delay profile has already been created in step S33 described above as the range in which a new effective path exists. May be. More specifically, in the delay profile shown in FIG. 8, if the value of the received signal power at the delay time t13 is less than or equal to the reference value L1 and greater than the reference value L2,
The control circuit 23 predicts the range R1 defined by the delay times t12 and t13 as the range in which a new valid path exists.

Further, for example, the control circuit 23 delays the delay time (the delay time is large) of the delay times in which the received signal power is not zero outside the range in which the delay profile has already been created in step S33. Specify. Then, the control circuit 23 determines from the specified delay time,
The delay time width up to the delay time at the end of the range in which the delay profile has already been created in step S33 may be predicted as the range in which a new valid path exists. More specifically, in the delay profile shown in FIG. 8, the control circuit 23 identifies the delay time t14 having the longest delay (largest delay time) among the delay times in which the received signal power is not zero, and the delay time t12. And the range R2 defined by t14 is predicted as a range in which a new valid path exists.

At this time, the control circuit 23 determines whether or not the range in which a valid path exists can be predicted (step S38). When the control circuit 23 determines that the range in which the valid path exists can be predicted (YES in step S38).
S), the process is returned to step S32, and the matched filter 20 is caused to execute the correlation calculation between the baseband signal and the spread code within the predicted range.

On the other hand, the control circuit 23 determines that the range in which an effective path exists cannot be predicted because the read delay profile does not have an appropriate value (for example, a value larger than the predetermined reference value L2) ( N in step S38
O), the power-on search process is executed, and the flexible search process ends (step S39).

According to this flexible search processing, the control circuit 23 reads the delay profile stored in the memory 26, preferentially creates the delay profile from the range in which it is predicted that a valid path exists, and the delay profile If it is determined that there is a valid path in the range created by, the operation of the matched filter 20 is stopped. As a result, the operation of the matched filter 20 can be suppressed, and the CDMA receiver 100 can reduce power consumption.

Generally, it is considered that a radio signal of a path which is reflected by a building or a building to generate a multipath is attenuated each time it is reflected. Therefore, from the base station to C
A radio signal having a large number of reflections before reaching the DMA receiver 100 has a lower signal level than a radio signal having a small number of reflections. A path having a large number of reflections and a low signal level has a longer propagation path length and a larger delay time than a path having a small number of reflections and having a low signal level. Therefore, it is preferable that the delay profile in the range in which the amount of delay time is larger than that at the time when the received signal power is maximum is preferentially created in the delay profile because there is a possibility that an effective path exists. Therefore, a CDMA receiver according to a third embodiment of the present invention, which preferentially creates a delay profile in a range in which the delay time amount is larger than when the received signal power is maximum, will be described below. .

CDM according to the third embodiment of the present invention
The A receiver has the same configuration as the CDMA receiver 100 according to the first and second embodiments.

Then, when the power is turned on, the control circuit 23 executes the power-on search processing as in the first and second embodiments, creates a delay profile of one symbol time, and stores it in the memory. 26. After that, when the CDMA receiving device 100 starts receiving information from the base station, the control circuit 23 performs control as shown in FIG.
The backward priority search process shown in the flowchart of FIG.

When the backward priority search process is started, the control circuit 23 reads the delay profile stored in the memory 26 and specifies the delay time at which the received signal power becomes maximum (step S40).

The control circuit 23 activates the matched filter 20 (step S41), and within the range from the delay time specified in step S40 to a time delayed by a predetermined time, for example, 100 chip time, to the baseband. The correlation calculation between the signal and the spread signal is executed (step S4).
2).

The matched filter 20 sends the pulse train generated by performing the correlation calculation to the level adjuster 21, and the level adjuster 21 adjusts the signal level of the pulse train and sends it to the integrator 22. The integrator 22 cyclically integrates the signal level received from the level adjuster 21 to obtain the received signal power, and notifies the control circuit 23 of the received signal power.

The control circuit 23 receives the notification of the received signal power from the integrator 22 and creates a delay profile, compares the received signal power with a predetermined reference value L1, and determines that the received signal power is larger than the reference value L1. Is determined (step S43).

The control circuit 23 determines that the received signal power is the reference value L.
If it is determined that the value is larger than 1 (YES in step S43), it is determined that there is an effective path, and the baseband signal of the effective path is detected by the PN correlator 24 from the delay time and the received signal power in which the value exists. Create parameters for despreading.

The control circuit 23 sets the created parameter in one of the plurality of PN correlators 24, and despreads the baseband signal demodulated by the radio demodulation unit 10 (step S44).

After that, the control circuit 23 stops the operation of the matched filter 20, stores the created delay profile in the memory 26, and finishes the backward priority search process (steps S45 and S46).

On the other hand, when the control circuit 23 determines in step S43 that there is no value larger than the reference value L1 (NO in step S43), it executes the power-on search process to delay one symbol time. Create a profile
The backward priority search process ends (step S47).

Also by this backward priority search processing, the control circuit 23 can read the delay profile stored in the memory 26 and preferentially create the delay profile from the range in which it is predicted that a valid path exists. .
Then, when the control circuit 23 determines that there is an effective path within the range in which the delay profile is created, the control circuit 23 stops the operation of the matched filter 20. As a result, the operation of the matched filter 20 can be suppressed, and the CDMA receiver 100 can reduce power consumption.

As described above, this CDMA receiver 100 can suppress the operation of the matched filter 20 by creating a delay profile for each range shorter than one symbol time, and reduce power consumption. .

The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, the control circuit 23 is the same as the control circuit 23 described in the first to third embodiments.
The / M symbol search process, the flexible search process, and the backward priority search process may be alternately executed every time a predetermined time elapses. Further, the processing may be selectively used depending on the multipath environment.

[0099]

As described above, according to the present invention, by suppressing the operation of the matched filter when creating a delay profile, it is possible to reduce the power consumption and the CDMA receiver and its path. A search method can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a CDMA receiver according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a RAKE processing unit.

FIG. 3 is a diagram illustrating a delay profile.

FIG. 4 is a flowchart for explaining a power-on search process.

FIG. 5 is a flowchart for explaining 1 / M symbol search processing.

FIG. 6 is a diagram illustrating a delay profile for explaining a range in which a matched filter executes a correlation operation in the 1 / M symbol search process.

FIG. 7 is a flowchart illustrating a flexible search process.

FIG. 8 is a diagram illustrating a delay profile for explaining a range in which a matched filter executes a correlation calculation in a flexible search process.

FIG. 9 is a flowchart illustrating a backward priority search process.

[Explanation of symbols]

10 Wireless demodulator 11 RAKE processing section 12 Data processing unit 13 antennas 20 matched filters 21 Level adjuster 22 Integrator 23 Control circuit 24 PN correlator 25 RAKE synthesizer 26 memory 100 CDMA receiver

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-112673 (JP, A) JP-A-9-321667 (JP, A) JP-A-11-8606 (JP, A) JP-A-11- 27180 (JP, A) JP 5-175935 (JP, A) JP 11-274982 (JP, A) JP 2000-22665 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H04J 13/00-13/06 H04B 1/69-1/713 H04B 1/10

Claims (12)

(57) [Claims] 1. A correlation calculation executing means for executing a correlation calculation with a spread code for spreading a pilot symbol while delaying a baseband signal obtained by receiving and demodulating a radio signal, and the correlation calculation executing means performs the correlation calculation. An integrating unit that integrates the executed results to obtain the received signal power, a profile storage unit that stores the delay profile created from the received signal power found by the integrating unit, and a 1-symbol time from the time of creating the delay profile. It is effective to make the correlation calculation execution means execute the correlation calculation in the range of the short delay time width, determine whether the received signal power obtained by the integration means is larger than a predetermined reference value, and to judge that the received signal power is larger than a predetermined reference value. Assuming that there is a path, the delay storing profile is stored in the profile storing means, the operation of the correlation calculation executing means is stopped, and the received signal power is When it is determined that the value is equal to or less than the reference value, an operation control unit that causes the correlation calculation execution unit to execute a correlation calculation in a longer delay time range to create a delay profile is provided. Receiver. 2. The operation control means is set to 1 when the power is turned on.
The CDMA receiver according to claim 1, wherein a delay profile of a symbol time is created. 3. The operation control means reads the delay profile stored in the profile storage means, and correlates within a predetermined delay time width range centered on the delay time at which the received signal power becomes maximum. The correlation calculation execution means is caused to execute a calculation, and it is judged whether or not the received signal power obtained by the integration means is larger than the reference value. When the operation of the correlation calculation executing means is stopped and it is determined that the received signal power is less than or equal to the reference value, the range in which the correlation calculation executing means executes the correlation calculation is expanded by the same time width as the predetermined delay time width. The CDMA receiver according to claim 1 or 2, wherein a delay profile is created. 4. The operation control means reads the delay profile stored in the profile storage means, and within a delay time width range defined by a plurality of delay times at which the received signal power becomes larger than the reference value. Correlation calculation is executed by the correlation calculation execution means, and it is judged whether or not the received signal power obtained by the integration means is larger than the reference value. If it is judged that it is larger, the delay profile is stored in the profile storage means. When the operation of the correlation calculation executing means is stopped and it is determined that the received signal power is equal to or lower than the reference value, the range in which the correlation calculation executing means executes the correlation calculation is expanded to create a delay profile. The CDMA receiver according to claim 1 or 2. 5. The operation control means determines that the received signal power obtained by the integration means is less than or equal to the reference value,
The delay profile stored in the profile storage unit is read, and the correlation calculation execution unit executes the correlation calculation within a delay time range defined by a delay time when the received signal power is not zero. The CDMA receiver according to claim 4. 6. The operation control means determines that the received signal power obtained by the integration means is less than or equal to the reference value,
The delay profile stored in the profile storage unit is read, and the correlation calculation execution unit is provided with a delay time range defined by a delay time at which the received signal power becomes larger than a second reference value smaller than the reference value. The CDMA receiver according to claim 4, wherein a correlation calculation is executed. 7. The operation control means reads the delay profile stored in the profile storage means, and performs a correlation calculation in a range from a delay time at which the received signal power becomes maximum to a time delayed by a predetermined time. The CDMA receiver according to claim 1 or 2, wherein the delay calculation is performed by causing the correlation calculation executing means to execute the delay profile. 8. The CDMA receiver according to claim 1, wherein the correlation calculation executing means executes the correlation calculation using a matched filter. 9. A correlation calculation step for executing a correlation calculation with a spreading code for spreading a pilot symbol while delaying a baseband signal within a delay time width shorter than one symbol time by a matched filter, and the correlation calculation. An integration step of integrating the calculation results of the steps to obtain a received signal power to create a delay profile, and a determination step of determining whether or not the received signal power obtained in the integration step is larger than a predetermined reference value. When the received signal power is determined to be larger than the reference value in the determination step, despreading for extracting the data signal is executed assuming that there is an effective path, and the delay profile created in the integration step is stored in the memory. and search end step for ending the search path by stopping the operation of said matched filter by said discriminating scan In the received signal power at-up following the reference value
If it is determined that there is, the correlation calculation step
Perform correlation calculation in the range of long delay time
And a calculation control step of creating a Airu, receiving radio signals in a CDMA system, wherein the C
A path search method for a DMA receiver. 10. The correlation calculation step comprises a step of reading a delay profile stored in a memory and executing a correlation calculation within a predetermined range centered on a delay time at which the received signal power becomes maximum. The path search method according to claim 9, wherein 11. The correlation calculation step reads a delay profile stored in a memory, and performs a correlation calculation within a delay time range defined by a plurality of delay times at which the received signal power becomes larger than the reference value. The path search method according to claim 9, further comprising a step of executing. 12. The correlation calculation step comprises a step of reading a delay profile stored in a memory and executing a correlation calculation in a range from a delay time at which the received signal power becomes maximum to a time delayed by a predetermined time. The path search method according to claim 9, wherein