JP3480963B2 - DMA transfer system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer system, and more particularly to a DMA transfer system in which a DMA transfer control unit and a plurality of devices are connected via an address bus and a data bus which are independent of each other, or an address and data transfer. The present invention relates to a DMA transfer system connected via a common bus for time-division transfer.

[0002]

2. Description of the Related Art In recent years, with the increasing number of functions of computers and the speeding up of data communication, there has been a demand for speeding up of data processing inside the computer. In particular, in order to perform high-speed data transfer between memories or between a memory and a device such as a codec for audio / image processing, a DMA for performing data transfer without a CPU controlling the entire computer.
Transfer is used.

FIG. 14 shows an example of a system configuration for performing conventional DMA transfer. The CPU 101 controls processing that realizes the functions of this system.
By the control program stored in the external ROM,
Processing including DMA transfer is executed.

The DMA transfer control unit (DMAC) 102 is a direct memory access controller, and
It is a device that controls MA transfer. Device A (10
3), device B (104), device C (105),
And the device D (106) is a RAM, a voice codec,
It is a functional device that executes a predetermined process such as an image codec or a signal conversion element.

In this example, the CPU 101, the DMA transfer control unit 102, and the devices 103 to 106 are
Address bus 107 and data bus 10 independent of each other
8 is connected. For example, a 32-bit address bus 107 composed of 32 signal lines A31 to A0 and D
A 16-bit data bus 108 including 16 signal lines 15 to D0 is separately provided.

Here, when performing normal DMA transfer,
First, the CPU 101 sets, in the DMA transfer control unit 102, information necessary for DMA transfer, such as address specification of a transfer source device, address specification of a transfer destination device, and the number of bytes of data to be transferred.

After this, the DMA transfer control unit 102 makes the CPU
Output a bus request BREQ signal to 101,
After that, when the response ACK signal is returned from the CPU 101 to the DMA transfer control unit 102, the DMA transfer control unit 102 monopolizes the address bus 107 and the data bus 108 and starts the DMA transfer control.

For example, when the DMA transfer control unit 102 outputs the address assigned to the device A (103) onto the address bus 107 and outputs the read (RD) signal, it is stored in the address output onto the address bus. Data is output from the device A onto the data bus 108.

After that, when the address assigned to the device B (104) is output on the address bus 107 and a write (WT) signal is output, the address of the device B output on the address bus is changed to the data bus. 10
The data on 8 is written.

By repeating such processing, the DMA transfer control unit 102 does not go through the CPU 101,
Data transfer control between two devices is directly performed at a relatively high speed.

[0011]

However, even in the DMA transfer, when the data transfer between two different sets of devices is required, it is necessary to perform the data transfer separately for each set. For example, device A (103) to device B
The DMA transfer to the device (104) and the DMA transfer from the device C (105) to the device D (106) cannot be performed simultaneously in time, and the DMA transfer from the device A (103) to the device B (104) cannot be performed. After going, device C
DMA transfer from (105) to device D (106) had to be performed.

Therefore, when such a plurality of different sets of data transfer are performed by the DMA transfer control unit, since the DMA transfers are performed separately in terms of time, image processing, etc., in which high speed data transfer is required, is particularly required. In the field of, there is a problem that data transfer takes too long.

The present invention has been made in consideration of such circumstances, and by simultaneously performing a plurality of different DMA transfers in parallel, the time required for a plurality of data transfers can be shortened and the data processing speed can be increased. DM that can be realized
It is intended to provide an A transfer system.

[0014]

SUMMARY OF THE INVENTION The present invention is a DMA transfer.
The controller and multiple devices are independent
Connected via Les Bus and Data Bus, DMA transfer
The control unit controls the data transfer between any two devices.
In a DMA transfer system to perform, a DMA transfer control unit
2n-bit address bus with one specific device
And m-bit data bus, and any other device
Address pin is the upper n bits of the address bus.
Upper address group or lower n bit address
Connected to a lower address group that represents the
Connect the data terminal of your device to the m-bit data bus.
From one particular device to any other two devices.
Characterized by transferring m-bit data to the device
A DMA transfer system is provided. FIG. 1 shows a block diagram of a basic configuration of an embodiment of the present invention. In the drawing, the present invention, DMA transfer control unit 5 and a plurality of devices (1, 2, 3, ...... i) is, luer exist <br/> independently address bus 6及beauty data bus 7 In a DMA transfer system in which the DMA transfer control unit 5 controls data transfer between two arbitrary devices, the address terminal of the arbitrary device is an upper address indicating an upper n-bit address of the address bus 6. Connected to a group 8 or a lower address group 9 indicating a lower n-bit address, and a data terminal of an arbitrary device connected to a higher data group 10 indicating a higher m bit data or a lower data group 11 indicating a lower m bit data,
The DMA transfer control unit 5 divides the n-bit addresses of the two transfer source devices into the upper address group 8 and the lower address group 9 of the address bus and outputs them simultaneously. After the two m-bit data stored at the specified addresses are divided into the upper data group 10 and the lower data group 11 of the data bus and read out at the same time, the n-bit addresses of the two transfer destination devices are read out from the upper address bus. Address group 8 and lower address group 9
The present invention provides a DMA transfer system characterized in that two m-bit data read out to the data bus are simultaneously output, and the two m-bit data read out to the data bus are simultaneously written into two transfer destination devices.

FIG. 2 shows a block diagram of the basic configuration of the second embodiment of the present invention. In the figure, the present invention is
DMA transfer control unit 5 and a plurality of devices (1, 2,
3, ...... i) are, independently to exist Rua dress bus 6及beauty
Are connected via a data bus 7, DMA of DMA transfer control unit performs control of data transfer between any two devices
In the transfer system, one specific device is connected to the 2n-bit address bus 6 and the m-bit data bus 7, and the address terminal of any other device indicates the upper n-bit address of the address bus. Or a lower address group 9 indicating a lower n bit address, and a data terminal of an arbitrary device is connected to the data bus 7 of m bits, and m bit data is transmitted from one specific device to any other two devices. The present invention provides a DMA transfer system which is characterized in that the transfer is performed.

FIG. 3 shows a block diagram of the basic configuration of the third embodiment of the present invention. In the figure, the present invention is
The DMA transfer control unit 5 and a plurality of devices (1, 2, 3 ... i) are connected via a 2n-bit common bus 12 to which addresses and data are transferred by time division, and DM
In a DMA transfer system in which the A transfer control unit 5 controls data transfer between any two devices, an address terminal of any device is used as an upper address bit of the common bus 12 and an n-bit upper address group 8 is used. Alternatively, a k-bit higher-order data group 10 connected to an n-bit lower-order address group 9 used as a lower-order address bit and having a data terminal of an arbitrary device satisfying k ≦ n used as a higher-order data bit of the common bus 12 is used. Or connected to a k-bit lower-order data group 11 used as a lower-order data bit,
The present invention provides a DMA transfer system characterized by transferring k-bit data between two devices.

FIG. 4 shows a block diagram of the basic configuration of the fourth embodiment of the present invention. In the figure, the present invention is
The DMA transfer control unit 5 and a plurality of devices (1, 2, 3 ... i) are connected via a 2n-bit common bus (12) to which addresses and data are transferred in a time division manner, and the DMA transfer control unit In the DMA transfer system, 5 controls the data transfer between any two devices.
An address terminal of one specific device is connected to a 2n-bit common bus 12 used as an address bus, and a data terminal of the device is connected to a k-bit common bus used as a data bus, which satisfies k ≦ 2n;
An address terminal of any other device is connected to an n-bit upper address group 8 used as an upper address bit or an n-bit lower address group 9 used as a lower address bit in the common bus 12, and another arbitrary device. Data terminal of device is common bus 1
DMA transfer characterized by being connected to a k-bit common bus satisfying k ≦ 2n, which is used as a data bus, and performing k-bit data transfer from one specific device to any other two devices. It provides a system.

Here, the DMA transfer control unit 5 is usually 1
It is supplied as one device and directly controls data transfer between the two devices. DMA transfer control unit 5
Is a CP that is normally used to control the entire system.
Information necessary for data transfer such as data transfer source, data transfer destination, and data transfer bit number is set from U.

The DMA transfer is a two-device operation performed without the intervention of the CPU by the DMA transfer control unit 5 outputting a data transfer request to the CPU after the necessary information is set in the DMA transfer control unit 5. A direct data transfer between. The device is a memory, such as SRAM or DRAM, a functional element that performs encoding / signaling and compression / expansion of digital image / audio data.

The address bus 6 is a signal line through which an address given in advance to a device connected to the address bus 6 flows. The number of bits is selected according to the scale of the system, and various buses such as 16 bits or 32 bits are used. is there.

The data bus 7 is a signal line for flowing data input / output to / from each device, and there are various buses such as 8-bit or 16-bit depending on the size of data handled by the system.

The common bus 12 is a signal for separately flowing addresses or data in a time division manner, and an appropriate number of bits is selected depending on the size of the addresses and data to be handled. When the address bus 6 is composed of 2n-bit signal lines, the upper address group 8 refers to n signal lines capable of designating an upper digit address indicated by n bits, and the lower address group 9 refers to It refers to n signal lines that can specify a lower digit address indicated by n bits.

When the data bus 7 is composed of a 2 m-bit signal, the upper data group 10 refers to m signal lines that can specify upper digit data represented by m bits, and is referred to as the lower data group 11. Indicates m signal lines capable of designating lower digit data represented by m bits.

[0024]

The DMA transfer control unit 5 outputs the addresses of two transfer source devices on the 2n-bit address bus. At this time, the address of one device of the transfer source is output to the upper n bits corresponding to the upper address group 8 of the 2n-bit address bus, and the address of the transfer source is set to the lower n bits corresponding to the lower address group 9. The address of the other device is output.

Thereafter, the DMA transfer control unit stores m in the address specified by the upper address group of the transfer source.
The bit data and the m-bit data stored at the address designated by the lower address group are simultaneously read to the upper data group 10 and the lower data group 11 of the data bus. At this time, the m-bit data read from one device of the transfer source and the m-bit data read from the other device of the transfer source are the upper data group 10 or the lower data group 11 connected to the respective devices. Is output on the data bus.

Next, the DMA transfer controller 5 outputs the addresses of the two transfer destination devices on the 2n-bit address bus. At this time, the address of one device of the transfer destination is output to the upper n bits corresponding to the upper address group 8, and the address of the other device of the transfer destination is output to the lower n bits corresponding to the lower address group 9. It

Thereafter, the DMA transfer control unit 5 simultaneously sets the two m-bit data read on the data bus to the address specified by the upper address group and the address specified by the lower address group of the transfer destination device. Write. At this time, one of the transfer destination devices to which the higher-order data group 10 is connected has a higher-order m on the data bus.
Bit data is written, and the lower m bits of data on the data bus are written to the other transfer destination device to which the lower data group 11 is connected.

According to the present invention, by simultaneously performing a plurality of different DMA transfers in parallel, the time required for a plurality of data transfers can be shortened and the speed of data processing can be increased.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the embodiments shown in the drawings. The present invention is not limited to this. FIG. 5 shows a block diagram of the basic configuration of the first embodiment of the present invention. Device 1 (1), device 2
(2), the device 3 (3), and the device 4 (4) are functional elements such as a memory and a codec that store or process data.

The DMA transfer control unit 5 is a DMA transfer controller that directly transfers data between two devices. In this embodiment, the address bus 6 and the data bus 7 are separately provided. Here, the address bus 6 is composed of 32 signal lines A31 to A0 and can transfer a 32-bit address. Is composed of 16 signal lines D15 to D0 and can transfer 16-bit data.

Further, the device 1 (1) and the device 2
In (2), A31 to A16 of the upper address group 8 of the address bus are connected, and D15 to D8 of the upper data group 10 of the data bus are connected. Also, the device 3 (3) and the device 4
In (4), A15 to A0 of the lower address group 9 of the address bus are connected, and D7 to D0 of the lower data group 11 of the data bus are connected.

A signal line RD for read control from the DMA transfer control unit 5 is connected to the device 1 (1) and the device (3), and the device 2 (2) and the device 4 (4) are connected to each other. It is assumed that the write control signal line WT from the DMA transfer control unit 5 is connected.

Next, in this first embodiment, two sets of D
An operation example of simultaneously performing MA transfer will be described. FIG. 6 shows the first
It is a time chart of an example. Here, device 1
An example is shown in which DMA transfer from (1) to device 2 (2) and DMA transfer from device 3 (3) to device 4 (4) are performed simultaneously.

First, the DMA transfer control unit 5 determines the transfer source 2
Specify the address of one device. That is, DMA
The transfer control unit 5 transfers the address assigned to the device 1 (1) to A 31 to A 16 of the address bus 6 and the device 3
The address given to (3) is set to A15 of the address bus 6.
Output to A0 at the same time.

After that, when the DMA transfer control unit 5 outputs the RD signal, the device 1 (1) and the device 3 (3) detect the falling edge of the RD signal and detect the specified address input from the address bus 6. The data is read from and output to the data bus 7.

That is, the device 1 (1) has A31-
The 8-bit data stored at the address designated by A16 is read and output to D15 to D8 of the data bus. Similarly, the device 3 (3) reads the 8-bit data stored at the addresses designated by A15 to A0 and outputs it to D7 to D0 of the data bus. The output of data from the device 1 (1) and the device 3 (3) is performed at the same timing, which is the same state that 16-bit data is output onto the data bus 7.

Next, the DMA transfer control unit 5 specifies the addresses of the two transfer destination devices. That is, the DMA transfer control unit 5 transfers the address given to the device 2 (2) to A 31 to A 16 of the address bus 6 and the device 4
The address given to (4) is set to A15 of the address bus 6.
Output to A0 at the same time.

Thereafter, when the DMA transfer control unit 5 outputs the WT signal, the device 2 (2) and the device 4 (4)
Detects the trailing edge of the WT signal and writes the data existing on the data bus to the specified address input from the address bus 6.

That is, the device 2 (2) has A31-
D15 on the data bus 7 at the address specified by A16
Write the 8-bit data output to D8. Similarly, the device 4 (4) writes the 8-bit data output to D7 to D0 on the data bus 7 at the addresses designated by A15 to A0. The device 2 (2) and the device 4 (4) write data at the same timing.

The above-described data read and write operations are continuously repeated by the DMA transfer control unit 5 for a predetermined number of data set in the DMA transfer control unit, so that the device 1 (1) to the device 2 Two sets of DMA transfer are executed, a data transfer to (2) and a data transfer from device 3 (3) to device 4 (4).

As described above, the addresses of two devices are simultaneously designated by using the 32-bit address bus, and two 8-bit data are simultaneously sent to the 16-bit data bus, so that two sets of DMA transfer can be performed at the same time. This is a feature of the first embodiment of the present invention.

The operation of the DMA transfer seen from the DMA transfer control unit is the same as the DMA transfer of transferring 16-bit data from the device designated by the 32-bit address to another device in this example. The transfer itself is a known technique.

Next, as a second embodiment, an operation example of simultaneously performing two sets of DMA transfer for the same data in a DMA transfer system having an address bus and a data bus separately will be described. FIG. 7 shows a block diagram of the basic configuration of the second embodiment of the present invention. The device 1 (1), the device 2 (2), the device 3 (3) and the DMA transfer control unit 5 are connected to the address bus 6 and the data bus 7 which are separately provided, as in FIG.

Here, the DMA transfer control unit 5 and the device 1
A 32-bit address bus of A31 to A0 and a 16-bit data bus of D15 to D0 are connected to (1), and a 16-bit upper address group 8 of A31 to A16 and D15 to D0 of device 2 (2). A 16-bit data bus is connected, and device 15 (3) has 1 of A15 to A0.
6-bit lower address group 9 and 1 of D15 to D0
It is assumed that 6-bit data is connected.

FIG. 8 shows a time chart of the second embodiment. Here, device 1 (1) to device 2 (2)
An example of two sets of DMA transfer for transferring the same data to the device 3 (3) will be described. First, the DMA transfer control unit 5
Outputs the address of the transfer source device 1 (1) onto the address bus 6 and outputs the RD signal which gives a data read instruction. As a result, the 16-bit data stored at the designated address is read from the device 1 (1) and output to D15 to D0 of the data bus 7.

Next, the DMA transfer control unit 5 specifies the addresses of the two transfer destination devices. That is, the DMA transfer control unit 5 transfers the address assigned to the device 2 (2) to A 31 to A 16 of the address bus 6 and the device 3
The address given to (3) is set to A15 of the address bus 6.
Output to A0 at the same time.

After that, when the DMA transfer control unit 5 outputs the WT signal, the device 2 (2) and the device 3 (3)
Detects the falling edge of the WT signal,
The 16-bit data existing on the data bus is written to the specified address input from. That is, at the same time,
The device 2 (2) writes 16-bit data to the addresses designated by A31 to A16, and the device 3 (3) writes 16-bit data to the addresses designated by A15 to A0.

The DMA transfer control unit 5 continuously repeats the above-described data read and write operations for a predetermined number of data set in the DMA transfer control unit 5, thereby allowing the device 1 (1) to operate. From the device to the device 2 (2) and the device 3 (3) are simultaneously executed.

As described above, the addresses of two transfer destination devices are simultaneously designated by using the 32-bit address bus, and 16-bit data stored in the transfer source device is simultaneously transferred to the two transfer destination devices. Is a feature of the second embodiment of the present invention.

Next, as a third embodiment, an operation example of simultaneously performing two sets of DMA transfers in a DMA transfer system having a common bus sharing an address bus and a data bus will be described. FIG. 9 shows a block diagram of the basic configuration of the third embodiment of the present invention. Unlike the first embodiment of FIG. 5, device 1 (1), device 2 (2), device 3 (3),
The device 4 (4) and the DMA transfer control unit 5 are connected via the common bus 12.

The common bus 12 in this embodiment is 1
A31 to A1 indicating the 6-bit upper address group 8
6 and 16-bit lower address group 9 or AD15-AD which functions as a 16-bit data bus
It consists of zero. That is, AD15 to AD0 are 16-bit lower address groups AD15 to AD in a time division manner.
16-bit data bus D when used as 0
Sometimes used as 15-D0. Further, the data bus is composed of an upper data group 10 of upper 8 bits D15 to D8 and a lower data group 1 of lower 8 bits D7 to D0.
Divided into 1.

In FIG. 9, the 16-bit upper address group 8 is connected to the address terminal of the device 1 (1), and the 8-bit upper data group 1 is connected to the data terminal.
0 is connected. Also in the figure, device 1 (1)
In order to temporarily hold the data read from the data buffer 14, the data buffer 14 and the upper data group 10 and the common bus A
It is provided between D15 and AD8.

In device 2 (2), device 1
Similar to (1), the upper address group 8 and the upper data group 10 are connected, but AD15 to A of the common bus.
It differs from device 1 (1) in that D8 is directly connected to device 2 (2). In the device 3 (3), the 16-bit lower address group 9 is connected to the address terminal, and the 8-bit lower data group 1 is connected to the data terminal.
1 is connected.

Further, in the figure, in order to temporarily hold the data read from the device 3 (3), the data buffer 14 is connected to the lower data group 11 and AD7 of the common bus.
~ AD0. In addition, the DMA transfer control unit 5 is assigned to A15 to A0 indicated by the lower address group 9.
In order to hold the address designated by the latch circuit 13, the latch circuit 13 and the lower address group 9 and the common bus AD15 ...
Prepared during AD0.

Device 3 in device 4 (4)
Similar to (3), the lower address group 9 and the lower data group 11 are connected, but AD7 to AD of the common bus.
The point where 0 is directly connected to device 4 (4) is device 3
Different from (3).

The data buffer 14 is enabled by the input of the write signal WT output from the DMA transfer control unit 5, and when enabled, the data read on the upper data group 10 or the lower data group 11 is stored. It is output on the common bus.

The latch circuit 13 receives the address strobe signal ASTB output from the DMA transfer control unit 5 and outputs the address output on the AD15 to AD0 of the common bus 12 to the AD15 to A of the lower address group 9.
This is a circuit for holding D0.

FIG. 10 shows a time chart of the third embodiment. First, the DMA transfer control unit 5 outputs the addresses of the transfer source device 1 (1) and the transfer source device 3 (3) onto the common bus 12, and then outputs the ASTB signal. That is,
The address of the device 1 (1) is output to A31 to A16 of the higher-order address group 8 and AD15 of the common bus 12 is output.
The address of device 3 (3) is output to AD0.

The rising edge of the ASTB signal causes the latch operation of the latch circuit 13, and the address of the device 3 (3) output to AD15 to AD0 is held in A15 to A0 of the lower address group 9.

Next, the DMA transfer control unit 5 outputs an RD signal giving a data read instruction to the device 1 (1) and the device 3 (3). As a result, the 8-bit data stored at the specified address is read from the device 1 (1), and D15 to D8 of the upper data group 10 are read.
The 8-bit data that has been output to the device 3 (3) and has been stored at the designated address is output to D7 to D0 of the lower data group 11. At this time, the data buffer 14 is in the disabled state,
The data output to D15 to D8 and D7 to D0 is not output to the common bus 12.

Next, the DMA transfer control unit 5 outputs the addresses of the transfer destination device 2 (2) and device 4 (4),
Then, the ASTB signal is output. That is, the device 2 (2) is assigned to A31 to A16 of the upper address group 8.
Output the address of AD15 to AD0 of the common bus 12.
Simultaneously outputs the address of the device 4 (4).

The latch operation of the latch circuit 13 is performed by the rising of the ASTB signal, and the address of the device 4 (4) output to AD15 to AD0 is held in A15 to A0 of the lower address group 9.

After that, when the DMA transfer control unit 5 outputs the WT signal, the data buffer 14 is enabled, and the 8-bit data output to D15 to D8 of the upper data group 10 connected to the device 1 is transferred to the common bus AD15. .. to AD8 and the 8-bit data output to D7 to D0 of the lower data group 11 connected to the device 3 (3) are output to the common buses AD7 to AD0.

The device 2 (2) and the device 4 (4) write the data output on the common bus 12 at the falling timing of the WT signal. That is, device 2
In (2), the 8-bit data output to the upper data groups AD15 to AD8 is written to the addresses designated by A31 to A16. Similarly, device 4 (4)
The 8-bit data output to the lower data groups D7 to D0 are written to the addresses designated by A15 to A0. The device 2 (2) and the device 4 (4) write data at the same timing.

The DMA transfer control unit 5 continuously repeats the above-described data read and write operations for a predetermined number of data set in the DMA transfer control unit 5, and thus the device 1 (1) From device to device 2 (2) and device 3 (3) to device 4 (4)
Two DMA transfers are performed, one for data transfer to the other.

In this way, AD15-A of the common bus 12
When D0 is used as an address of the lower address group 9 or as a common line through which 16-bit data flows, 8-bit data read from the two transfer source devices is held in the data buffer 14 and stored in the two transfer destinations. It is a feature of the third embodiment of the present invention that two sets of DMA transfer are simultaneously performed by outputting the 8-bit data held when the write operation is performed to the device onto the common bus 12.

In the third embodiment, the data buffer 14 is provided to prevent the collision of the address and the data on the common bus 12 so that the data is transferred and written to the device. May be fetched into a buffer inside the DMA transfer control unit 5, and when writing data to the transfer destination, the fetched data may be output to the common bus 12 and written to the transfer destination.

Next, as a fourth embodiment, an operation example of simultaneously performing two sets of DMA transfers for the same data in a DMA transfer system having a common bus sharing an address bus and a data bus will be described. FIG. 11 shows a block diagram of the basic configuration of the fourth embodiment of the present invention. As in FIG. 9, device 1 (1), device 2 (2), device 3
(3) and the DMA transfer control unit 5 are connected via the common bus 12.

In FIG. 11, AD15 to AD0 are connected to the address terminal of the device 1 (1) through A31 to A16 of the common bus 12 and the latch circuit 13, and AD15 of the common bus 12 is connected to the data terminal through the data buffer 14. ~ AD0 is connected. In this example, the data transferred is 16 bits. The data buffer 14 performs control for outputting the data read from the device 1 (1) onto the buses D15 to D0 to AD15 to AD0 of the common bus 12.

In the device 2 (2), the 16-bit high-order address group 8 of A31 to A16 is connected to the address terminals, and the AD15 of the common bus 12 is connected to the data terminals.
~ AD0 is connected. In device 3 (3),
AD15 to AD0 of the common bus 12 are connected to the address terminals through the latch circuit 13, and the common bus 1 is connected to the data terminals.
2 AD15 to AD0 are connected.

As described above, the latch circuit 13 is a circuit for holding the address output on AD15 to AD0 of the common bus 12 on AD15 to AD0 of the lower address group 9.

FIG. 12 shows a time chart of the fourth embodiment. First, the DMA transfer control unit 5 outputs the address of the transfer source device 1 (1) onto the common bus 12, and then outputs the ASTB signal. That is, the address of the device 1 (1) is output to A31 to A16 and AD15 to AD0.

The rising of the ASTB signal causes the latch operation of the latch circuit 13, and the lower address of the device 1 (1) output to AD15 to AD0 is held in A15 to A0 of the lower address group 9.

Next, the DMA transfer control unit 5 outputs an RD signal giving a data read instruction to the device 1 (1). As a result, the 16-bit data stored at the designated address is read from the device 1 (1) and output to D15 to D0. At this time, the data buffer 14 is in the disabled state, and the data output to D15 to D0 is not output to the common bus 12.

Next, the DMA transfer control unit 5 outputs the addresses of the transfer destination devices 2 (2) and 3 (3),
After that, the ASTB signal is output. That is, the address of the device 2 (2) is output to A31 to A16 of the upper address group 8 and the address of the device 3 (3) is output to AD15 to AD0 of the common bus 12 at the same time. AS
The rising edge of the TB signal causes the latch operation of the latch circuit 13, and the device 3 output to AD15 to AD0.
The address of (3) is from A15 of lower address group 9
It is held at A0.

After that, when the DMA transfer control unit 5 outputs the WT signal, the data buffer 14 is enabled and the 16-bit data output to D15 to D0 connected to the device 1 is output to the common buses AD15 to AD0. To be done.

Device 2 (2) and device 3 (3)
Is A of the common bus 12 at the falling timing of the WT signal.
The data output on D15 to AD0 is written.
That is, the device 2 (2) writes 16-bit data on AD15 to AD0 to the addresses designated by A31 to A16. Similarly, the device 3 (3) is A15-.
16 on AD15 to AD0 at the address specified by A0
Write bit data.

The DMA transfer control unit 5 continuously repeats the above-described data read and write operations for the predetermined number of data set in the DMA transfer control unit 5, and thus the device 1 (1) From the device to the device 2 (2) and the device 3 (3) are simultaneously executed.

In this way, AD15-A of the common bus 12
When D0 is used as an address of the lower address group 9 or a common line through which 16-bit data flows, 16-bit data read from the transfer source device is held in the data buffer 14 and stored in two transfer destination devices. The fourth embodiment of the present invention is that the 16-bit data held when the write operation is performed is output to the common bus 12 to simultaneously transfer the same 16-bit data to two transfer destination devices. Is a feature of.

FIG. 13 shows a block diagram of the fifth embodiment of the present invention. This example shows a 32-bit address bus A3
1 shows an ISDN communication terminal device having a bus configuration having 1-A0 and 16-bit data buses D15-D0 separately.

The ISDN communication terminal device mainly includes an ISDN line control unit 81, an image memory unit 82, an audio memory unit 83,
Two serial-parallel data conversion units (S / P conversion unit 1 (84), SP conversion unit 2 (85)), image codec unit 86, audio codec unit 87, DMA transfer control unit 8
8 and a CPU 89.

The data received through the ISDN line is separated by the ISDN line control unit 81, and is separated by, for example, B1.
Image data is output to the channel and audio data is output to the B2 channel.

Thereafter, in the S / P converters 1 and 2, the image data and the audio data are converted into 8-bit parallel data, and the DMA transfer control unit 88 transfers the image data by the DMA transfer to the image memory unit 82 or the image codec. And transfers the audio data to the audio memory unit 83 or the audio codec unit 87.

At this time, as in the case of the first embodiment, as shown in FIG. 13, by dividing the address bus and the data bus into upper and lower parts and connecting them to the respective devices, the image data and the audio data are Simultaneous DMA transfer is possible.

For example, in FIG. 13, the DMA transfer control unit 88 supplies the address of the S / P conversion unit 1 (84) to the address buses A31 to A16 and the address buses A15 to A0.
Simultaneously outputs the address of the S / P converter 2 (85) to
By issuing the RD signal 92, the image data is transferred from D15 to
Audio data is read on D8 on D7 to D0 at the same timing.

Next, the DMA transfer control section 88 assigns the address of the image codec section 86 to the address buses A31 to A16 and the audio codec section 87 to the address buses A15 to A0.
Of the image data output to D15 to D8 on the data bus to the address specified by the image codec unit D7.
The voice data output to D0 is the voice codec section 87.
Is written to the specified address of.

[0087]

According to the present invention, since the address bus and the data bus or the common bus are divided into two groups and are connected to the transfer source device and the transfer destination device, two different sets of DMA transfer are simultaneously performed in parallel. Can be done by
Furthermore, the time required for data transfer can be shortened and the speed of data processing can be increased.

[Brief description of drawings]

FIG. 1 is a configuration block diagram according to claim 1 of the present invention.

FIG. 2 is a configuration block diagram according to claim 2 of the present invention.

FIG. 3 is a configuration block diagram according to claim 3 of the present invention.

FIG. 4 is a configuration block diagram according to claim 4 of the present invention.

FIG. 5 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 6 is a time chart of the first embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 8 is a time chart of the second embodiment of the present invention.

FIG. 9 is a block diagram showing the configuration of a third embodiment of the present invention.

FIG. 10 is a time chart of the third embodiment of the present invention.

FIG. 11 is a block diagram showing the configuration of a fourth embodiment of the present invention.

FIG. 12 is a time chart of the fourth embodiment of the present invention.

FIG. 13 is a block diagram showing the configuration of a fifth embodiment of the present invention.

FIG. 14 is a configuration block diagram of a conventional example.

[Explanation of symbols]

1 device 1 2 device 2 3 device 3 4 device i 5 DMA transfer control unit 6 address bus 7 data bus 8 upper address groups 9 Lower address group 10 upper data groups 11 Lower data group 12 common buses 13 Latch circuit 14 data buffer

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Claims (2)

(57) [Claims] 1. A DMA transfer controller及 beauty plurality of devices
But it is independently connected luer address bus and de Taba scan to exist through <br/> to, in DMA transfer system DMA transfer control unit performs control of data transfer between any two devices, DMA transfer control unit and one particular device is connected to the 2n-bit address bus and m-bit data bus,
Upper address group also <br/> address terminal of any other device indicates a higher n-bit address of the address bus is <br/> connected to the lower address group showing a lower n-bit address, and any DMA transfer system device data terminal connected to the data bus of m bits, and performs the transfer of one m-bit data from a particular device to any other two devices. 2. A via the common bus of 2n bits transferred by the address and data are time division, DMA transfer control
Part you and a plurality of devices are connected, DMA transfer control
In DMA transfer system part performs control of data transfer between any two devices, address terminals of one particular device is connected to a common bus of 2n bits used as an address bus, and data terminals of the device There is connected to the k bits of the common bus that satisfies k ≦ 2n used as a data bus, an address terminal of any other device, a common bus n bits upper address group used as the upper address bits of the scan or It is connected to the lower address group of n bits used as the lower address bits, and the data terminal of any other device is connected to a common bus k bits satisfying k ≦ 2n used as a data bus of the common bus From one particular device to any other 2
A DMA transfer system characterized by transferring k-bit data to one device.