JP3480558B2 - Medium access control device and LAN connection device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a medium access control device (hereinafter referred to as "media access controller") and a LAN connection device equipped with the medium access control device.

[0002]

2. Description of the Related Art An ordinary telephone is connected to an exchange, whereas an internet telephone is connected to a computer network. For this reason, Internet telephones may include LAs for computer network connections.
An N (Local Area Network) connector is usually provided.

By the way, nowadays, with the spread of computers, especially in a business environment, a personal computer for each person is common knowledge. But,
In the current device, different LAN cables have to be wired for the Internet telephone and for the computer, so there is a problem that the network equipment increases.

Therefore, it is strongly required to connect the telephone and the personal computer with one LAN cable.

[0005]

FIG. 2 shows a connection example of a conventional device which enables such a connection. Further, FIG. 3 shows an example of the internal configuration of the telephone 2 that enables such connection. As shown in FIG. 3, the telephone 2 is characterized by a concentrator (HU
The point is that the concentrator circuit 2I corresponding to B) is incorporated. The concentrator circuit 2I is used for concentrating the data packet in which the voice data and the telephone control data are packetized and the data packet in which the transmission data of the personal computer 1 is packetized, and sending them to the switching HUB 3.

Thus, the telephone 2 and the switching HUB
On the cable connecting 3 and 3, the voice data packet and the telephone control data packet, which are packets transmitted and received between the telephone 2 and the switching HUB 3, and the packet transmitted and received, between the personal computer 1 and the switching HUB 3. Computer data packets are transmitted. Therefore, packets containing computer data and audio data are mixed on the cable.

By the way, in the case of the telephone having the configuration shown in FIG. 3, the concentrator circuit 2I sends the packets from the codec 2C side and the packets from the personal computer 1 to the upper switching HUB 3 in the order in which they are received. When a large amount of packet data is sent from the computer 1 side, during that time, packets from the codec side including the voice signal are in a waiting state, resulting in a problem that a call is interrupted.

Therefore, the configuration shown in FIG. 4 can be considered. The telephone 2 having the configuration shown in FIG.
A signal from the side is temporarily stored in the internal memory 2G. Therefore, in the case of the telephone 2 in FIG. 4, the voice packet from the codec 2C side and the personal computer 1
CPU2F can manage the priority of packets from the side,
Voice packets can be preferentially transmitted.

However, since the packets from the personal computer 1 side are temporarily stored in the memory 2G, a large-scale memory and high-speed packet processing are required. There is a problem of being scarce.

[0010]

(A) In order to solve such a problem, in the present invention, a medium access having an interface for network connection, an interface for voice packet transmission / reception, and an interface for computer data communication is provided. The control device is provided with the following means.

That is, a priority control circuit is provided which gives priority to a transmission packet input from the voice packet transmission / reception interface over a transmission packet input from the computer communication interface and outputs the transmission packet to the network connection interface. To do. Where priority
The control circuit appears at the interface for network connection.
Voice packet transmission / reception when confirming the existence of transmission packets
To the transmission FIFO memory connected to the interface for
Check if there is a transmission request, and if there is no transmission request,
Interface for computer communication only
Transmission request for transmission FIFO memory connected to
The presence or absence of is confirmed. (B) Further, in the present invention, the medium access control device is mounted on the LAN connection device.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION (A) Example of Mounted Device FIG. 5 shows a functional block configuration example of a LAN connection device (including a LAN board) mounted with a media access controller (MAC) according to the present invention. Here, in FIG.
In order to enable the connection form shown in (2), the case where the device is installed in an Internet telephone with two LAN ports will be described.

Needless to say, the LAN connecting device equipped with the media access controller is not limited to the Internet telephone, but may be applied to, for example, a terminal adapter.

The LAN port is also 10 BA
The optical fiber distributed data interface (FDDI: is not limited to SE-T, 100BASE-T, etc.).
FiberDistributed Data Interface) system, 100VG-
A port configuration suitable for AnyLAN, ATM-LAN and other networks can be applied.

The internal structure of the Internet telephone shown in FIG. 5 will be described. Cordic 2C is microphone 2B
It is used for encoding the audio signal input from the device and decoding the audio data input via the bus 2D. Memory 2
G is used for temporary storage of encoded voice data and for temporary storage of received voice data.

Media Access Controller (MAC)
2E 'is in charge of processing in the media layer of each communication process, sends and receives packets (hereinafter referred to as "CPU data") including voice data to and from the bus 2D, and connects to a physical layer device 2H2 for connecting to a personal computer. Computer data packets (hereinafter referred to as "PC data") are transmitted and received between the two.

That is, the media access controller (MAC) 2E 'does not send and receive computer data packets via the bus as shown in FIG.
It directly sends and receives to and from the physical layer device 2H2.

In the case of the Internet telephone, the bus 2
Since the packet transmitted / received to / from D includes the voice data, the packet media access controller (MAC) 2E ′ shown in FIG.
The U data is configured to be transmitted with priority over the PC data input from the physical layer device 2H2.

In addition, a packet media access controller (MAC) 2E 'and physical layer devices 2H1 and 2H.
The interface used for the connection with 2 is an MII interface (Media Independent Interfac) that is an interface common to various configurations that does not depend on the configuration of the physical layer.
e) is used, and a bus interface is used as an interface used for connection with the codec 2C. However, it is also possible to use the MII interface for all the interfaces. (B) Embodiment of Media Access Controller 2E (Part 1) FIG. 1 shows a media access controller (MAC) 2E.
2 shows a functional block configuration according to the first embodiment of FIG. Figure 1
Media access controller (MA
C) 2E 'is a priority control circuit 2E'1, a bus interface 2E'2, a first first-in first-out memory (FIFO memory) 2E'3, a first transceiver circuit 2E'4, a second transceiver circuit 2E'5. , Second first-in first-out memory (FIFO memory) 2E′6.

Of these, the priority control circuit 2E'1 functions as a means for realizing the above-mentioned CPU data priority transmission function. In the priority control circuit 2E′1, the transmission request given from the FIFO memory 2E′3 on the bus interface side and the FIFO memory 2 on the personal computer side are transmitted.
A function of monitoring the transmission request given from E′6 is provided.

As a general rule, when the transmission request is confirmed, the priority control circuit 2E'1 executes the operation of reading the corresponding transmission data from the FIFO memory that transmitted the confirmed transmission request and sending it to the switching HUB3. However, the priority control circuit 2E'1, when the transmission request from the transmission request and the personal computer side from the bus interface side conflict, priority to transmit request from the bus interface side, to corresponding FIFO memory 2E'3 The stored transmission data is preferentially transmitted.

The priority control circuit 2E'1 realizes a necessary priority control function by the determination processing shown in FIG.

Next, the contents of the priority processing procedure executed by the media access controller 2E 'having the above configuration will be described.

The output of transmission data from the bus interface side and the output of transmission data from the personal computer side occur as independent events.

Therefore, when CPU data is input from the bus interface side to the media access controller 2E '(that is, when transmission data is input), the CPU data indicates packet start, end, and other states. It is written to the corresponding FIFO memory 2E′3 together with the status bit that represents it.

Similarly, when PC data is input from the personal computer side to the media access controller 2E '(that is, transmission data is input), the PC data is in the packet start, end, and other states. Corresponding F with a status bit representing
It is written in the IFO memory 2E'6.

In each of the FIFO memories 2E'3 and 2E'6, when a packet to be transmitted is stored inside, a transmission request for the transmission is output to the priority control circuit 2E'1.

The priority control circuit 2E'1 first monitors whether the first transmission / reception circuit 2E'4 is in a transmission state or a standby state (step S1). Here, when it is confirmed that the transmission is in progress (when a negative result is obtained in step S1), the priority control circuit 2E′1 causes the FIFO memory 2E′3 or 2 to operate.
The transmission state in the first transmission / reception circuit 2E′4 is continuously monitored without confirming whether the transmission request is input from E′6 (since the transmission request cannot be transmitted at this time even if there is a transmission request).

On the other hand, when the standby state is confirmed (when a positive result is obtained in step S1), the priority control circuit 2E'1 determines that the FIFO on the bus interface side.
It is determined whether or not a transmission request is input from the memory 2E'3 (step S2). First, the FIFO memory 2
The determination of E′3 is given priority because the output of the CPU data input from the bus interface side has priority over the PC data input from the personal computer side.

If a positive result is obtained in step S2 (which means that there is CPU data to be sent), the priority control circuit 2E'1 determines that the FIFO
The first transmission / reception circuit 2 which issues a transmission start command to the memory 2E′3 and waits for the CPU data to be read
It is sent to E'4 (step S4).

On the other hand, when a negative result is obtained in step S2 (which means that there is no CPU data to be sent), the priority control circuit 2E '.
1 is a FIFO memory 2 on the personal computer side
It is determined whether or not a transmission request is input from E'6 (step S3).

If a positive result is obtained in step S3 (this means that there is PC data to be transmitted), the priority control circuit 2E'1 determines that the FIF
The first transmission / reception circuit 2 that issues a transmission start command to the O memory 2E′6 and waits for the PC data to be read
It is sent to E'4 (step S5).

If a negative result is obtained also in step S3, or if the transmission of the transmission data in step S4 or S5 is completed, the priority control circuit 2E '.
1 returns to the determination process of step S1 and again monitors whether the first transmission / reception circuit 2E′4 is in the transmission state or the standby state.

The above operation is repeatedly executed after the power supply to the priority control circuit 2E'1 (Internet telephone) is started or reset.

As described above, in the case of the media access controller (MAC) 2E 'according to the first embodiment,
Transmission data from the bus interface side (that is, C
Even when there is a conflict between the transmission requests of the PU data) and the transmission data from the personal computer side (that is, PC data), the transmission data from the bus interface side with a higher priority can be sent out preferentially.

In this way, the transmission of voice data with high real-time property becomes a waiting state for the transmission of PC data, and it is possible to eliminate the possibility that the call is interrupted.

Further, in the case of the media access controller (MAC) 2E 'according to the first embodiment, it is not necessary to store the PC data in the internal memory unlike the conventional device (FIG. 4), so that it is large. The device can be downsized without requiring a large-scale memory.

Similarly, since it is not necessary to store PC data in the internal memory, the load on the CPU 2F constituting the media access controller (MAC) 2E 'can be reduced as compared with the conventional device (FIG. 4). (C) Embodiment of Media Access Controller 2E (Part 2) FIG. 7 shows a media access controller (MAC) 2E.
3 shows a functional block configuration according to a second embodiment of the present invention. Figure 7
In the figure, the parts corresponding to those in FIG.

Media Access Controller (MAC)
2E ″ is a priority control circuit 2E′1 and a bus interface 2
E'2, first first-in first-out memory (FIFO memory) 2
E'3, first transmitting / receiving circuit 2 E'4, second transmitting / receiving circuit 2
E'5, second first-in first-out memory (FIFO memory) 2
E'6, a transmission flow control unit 2E "7, and a reception flow control unit 2E" 8.

The difference between the second embodiment and the first embodiment is that a transmission flow control unit 2E "7 and a reception flow control unit 2E" 8 are newly added.

This is for the following reason. Generally, when collisions frequently occur at the port on the uplink side or collisions frequently occur at the port on the personal computer 1 side, the second FI
This causes an overflow in the FO memory 2E'6.

Therefore, in the second embodiment, by providing the transmission flow control unit 2E "7 and the reception flow control unit 2E" 8, the states of the transmission FIFO 2E'61 and the reception FIFO 2E'62 are monitored, and the monitoring results are obtained. Based on, the avoidance of overflow is realized.

Next, the content of the flow control procedure executed by the media access controller 2E "having the above configuration will be described. The operation relating to the priority transmission function of CPU data (voice data) is the first embodiment. The description is omitted because it is the same as the form.

First, the flow control when transmitting a packet received from the personal computer 1 side to the uplink side will be described.

If packets are received one after another from the personal computer 1 side in spite of a collision occurring on the uplink side and waiting for transmission, the FIFO memory 2E'6 ( Specifically, the transmission FIFO 2E'61) may cause an overflow.

Therefore, the transmission flow control unit 2
The E "7 constantly monitors the free space information of the transmission FIFO 2E'61 and the transmission waiting state information (while the backoff timer is counting) of the transmission / reception circuit 2E'4 on the uplink side to check whether or not overflow may occur. Perform the action to predict.

When an overflow may occur, the transmission flow control section 2E "7 stops the packet transmission of the personal computer 1 by giving a flow control signal to the transmission / reception circuit 2E'5 on the personal computer side. , Transmit FIFO2E'61
Avoid overflow of.

Since the flow control here is the flow control in half-duplex communication, it is performed by transmitting dummy data and forcibly causing a collision at a port on the personal computer side.

By the way, there is a means of sending a pause packet during full-duplex communication, but since there is no collision during full-duplex communication, the FIF
The O memory 2E'61 does not occur either.

Next, the flow control when transmitting the packet received from the uplink side to the personal computer side will be described.

Also in this case, when the personal computer side has a collision and is in the transmission waiting state, but the packets from the uplink side are successively received, the FIFO memory 2E ' 6 (more specifically, the reception FIFO2E ′ 62) may cause an overflow.

Therefore, the reception flow control unit 2
The E "8 constantly monitors the free space information of the reception FIFO 2E'62 and the transmission waiting state information (while the backoff timer is counting) of the transmission / reception circuit 2E'5 on the personal computer side to check whether or not overflow may occur. Perform the action to predict.

If there is a risk of overflow, the reception flow control unit 2E "8 gives a flow control signal to the transmission / reception circuit 2E'4 on the uplink side, thereby switching the transmission on the uplink side. The transmission of the HUB 3 and the host machine is stopped to avoid the overflow of the reception FIFO 2E′62.

The above operation is always executed in parallel with the priority control of the CPU data described in the first embodiment.

As described above, in the case of the media access controller (MAC) 2E ″ according to the second embodiment,
In addition to the effects of the first embodiment, F in half-duplex communication
The overflow of the IFO memory 2E'6 can be surely avoided.

By adding such a function,
The capacity (depth) of the FIFO memory 2E'6 can be reduced, and the FIFO memory can be built in the gate array.

[0057]

As described above, according to the medium access control apparatus of the present invention, the priority control circuit inputs the transmission packet input from the voice packet transmission / reception interface to the computer communication interface. Since it is output to the interface for network connection with priority over the transmission packet, it is possible to avoid the situation where the transmission of the voice packet is waiting for the transmission of the packet for computer communication, and it is possible to effectively avoid the interruption of the call. .

Further, according to the medium access control apparatus of the present invention, the transmission packet for computer data communication is directly input to the medium access control apparatus, so that it is compared to the case where the packet is processed through the internal memory. Thus, it is possible to reduce the size of the internal memory and reduce the load on the internal processing circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a MAC with a priority control function.

FIG. 2 is a diagram showing a connection example of an Internet telephone.

FIG. 3 is a block diagram showing a conventional example (No. 1) of an Internet telephone.

FIG. 4 is a block diagram showing a conventional example (No. 2) of an Internet telephone.

FIG. 5 is a diagram illustrating an application example of a MAC with a priority control function.

FIG. 6 is a flowchart showing a determination processing procedure of a priority control circuit.

FIG. 7 is a block diagram showing an internal configuration of a MAC with a flow control function.

[Explanation of symbols]

1 ... Personal computer, 2 ... Telephone, 2C ... Cordic, 2D ... Bus, 2E, 2E1, 2E2, 2
E ', 2E "... Media access controller, 2E'1
... Priority control circuit, 2E'2 ... Bus interface, 2E '
3, 2E'6 ... FIFO memory, 2E'4, 2E'5 ... Transceiver circuit, 2E "7, 2E" 8 ... Flow control, 2
F ... CPU, 2G ... Memory, 2I ... Concentrator circuit, 3 ... Switching HUB.

Front page continuation (51) Int.Cl. ⁷ Identification code FI H04L 29/10 H04L 13/00 309C H04M 11/06 H04Q 11/04 R H04Q 11/04 (72) Inventor Makoto Tanaka Toranomon, Tokyo 1 7-112 Oki Electric Industry Co., Ltd. (56) Reference JP-A-8-251313 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 29/06 H04L 12 / 28 H04L 12/46 H04L 12/56 H04L 13/08 H04L 29/10 H04M 11/06 H04Q 11/04

Claims (3)

(57) [Claims] 1. In a medium access control device having an interface for network connection, an interface for voice packet transmission / reception, and an interface for computer data communication, a transmission packet input from the interface for voice packet transmission / reception is transmitted to a computer. Includes a priority control circuit that prioritizes transmission packets input from the communication interface and outputs them to the network connection interface.
And, the priority control circuit, Intafe for a network connection
When checking the existence of transmission packets to be output to the
A transmission FIFO connected to an interface for transmitting and receiving
Check if there is a transmission request for the memory, and
Interface for computer communication only if
The transmit FIFO memory connected to the
A medium access control device characterized by confirming the presence or absence of a transmission request . 2. The medium access control device according to claim 1 , wherein the priority control circuit is a FIFO for transmission and a FIFO for reception which are connected to an interface for computer communication.
The free capacity of the memory is monitored, and each FI
It further comprises a flow control unit for monitoring a collision state of an interface serving as a transmission destination of the packet accumulated in the FO memory and for giving a flow control signal to an interface of the transmission source corresponding to the FIFO memory in which overflow can occur. Access control device. 3. A LAN connection device comprising the medium access control device according to claim 1 .