JP3479607B2 - Reference signal distribution system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference signal distribution system applicable to a transmission terminal station device and a switching device which handle reference signals such as a reference frequency (clock) and a reference phase in a digital communication network.

[0002]

2. Description of the Related Art For example, SDH (Synchronous Digital Hierarchy), which is an international standard high-speed relay speed system created by ITU-T (International Telecommunication Union Telecommunication Standardization Sector)
In the device conforming to the standard, STM-1 (155.52 Mbit / sec), STM-4 (622.08 Mbit / sec), STM
It is necessary to handle signals of various speeds such as -16 (2.488 Gbit / sec).

Further, a reference clock signal is used for synchronizing the signals to be transmitted, but it is necessary to synchronize this clock signal between the transmitting side and the receiving side. Therefore, the information of the clock signal is distributed to each device included in the communication network. Conventionally, in a reference frequency (clock signal) distribution network used in a digital communication network, only the frequency component is transmitted and the phase is not managed. However, for example, when the clock supplied from the clock supply device in the station is switched, a phase jump of about 125 μs at maximum occurs, so that the phase synchronization is deviated.

Therefore, when the information on the reference phase is required, conventionally, a signal from another system using a standard radio wave or the like is received by a specific device to determine the reference phase, and the device determines the other phase. The reference phase information is redistributed to the devices.

In the conventional reference signal distribution system,
One device (for example, the clock circuit of a switching device) is shown in FIG.
It is configured like 0. This will be described below with reference to FIG. Signals input to the information receiving circuit from other devices include
Contains the reference clock signal. The reference clock signal is extracted in each of the plurality of information receiving circuits.
The extracted plurality of reference clock signals are selected by the clock selection circuit (1), and the reference clock signals selected here are input to the reference clock generation device via the clock transmission circuit.

The reference clock generator generates a plurality of new reference clock signals based on the reference clock signal input from the clock transmission circuit. The plurality of reference clock signals output from the reference clock generator are input to the clock selection circuit (2) via the clock reception circuit.
The clock selection circuit (2) selects any one of the plurality of input reference clock signals. The selected reference clock signal is input to the clock synchronization circuit. The clock synchronization circuit removes noise such as jitter in the reference clock signal and reproduces the reference clock signal. The reproduced reference clock signal is sent to another device via the information transmission circuit.

[0007]

In the conventional digital communication network, the reference frequency and the reference phase of the signal to be transmitted are managed by different systems. However, in general, the frequency accuracy does not match between the reference frequency and the reference phase, so that there is a drawback that a frequency difference occurs between the system that uses the reference frequency and the system that uses the frequency obtained from the reference phase. In addition, since maintenance of the frequency is also generally required for maintenance of the reference phase, double equipment is required.

It is an object of the present invention to provide a reference signal distribution system capable of reducing the cost of equipment as compared with the conventional system when it is necessary to manage both the frequency and the phase of a digital communication network.

[0009]

In order to solve the above-mentioned problems, in the present invention, the maintenance part of the reference frequency is shared by the reference frequency and the reference phase. Therefore, the reference phase is managed only by adding a minimum number of circuits to the conventionally used reference frequency maintenance management section, and the system configuration is simplified and the cost is reduced as the reference signal distribution system.

That is, the reference signal distribution system according to the first aspect includes a first reference clock signal serving as a frequency reference, a first reference phase signal serving as a phase reference, and information regarding the first reference phase signal. An information transmission circuit for transmitting a signal from a specific device to another device; a second reference clock signal input from the other device to the specific device;
And a second reference clock signal extracted from the signal received by the information receiving circuit, and the information receiving circuit for receiving the signal including the reference phase signal and the information about the second reference phase signal to the reference clock generator. And a clock receiving circuit that receives a third reference clock signal output from the reference clock generation device in response to a second reference clock signal output from the clock transmission circuit.
A clock selecting circuit for selecting a part of the second reference clock signal extracted from the signal received by the information receiving circuit and the third reference clock signal received by the clock receiving circuit; and the clock selecting circuit. A clock synchronization circuit for reproducing a fourth reference clock signal in synchronization with a signal selected by the circuit, and a phase for generating a third reference phase signal based on the fourth reference clock signal reproduced by the clock synchronization circuit. A signal generator, and a phase difference measuring unit that measures the phase difference between the third reference phase signal output from the phase signal generator and the second reference phase signal extracted from the signal received by the information receiving circuit. And a true reference based on the information on the phase difference output by the phase difference measuring unit and the phase information on the second reference phase signal extracted from the signal received by the information receiving circuit. A phase difference between the phase and the reference phase signal output from the phase signal generator is obtained, and the phase signal generator outputs the information including the obtained phase error to the information transmission circuit. A phase information interface for transmitting the reference phase signal to another device is provided, and the fourth reference clock signal and the third reference phase signal are supplied to the information transmission circuit.

In the present invention, a reference clock signal serving as a frequency reference, a reference phase signal serving as a phase reference, and a signal including information about the reference phase signal are specified via the information transmitting circuit and the information receiving circuit. It is transmitted and received between a device and another device. The clock transmission circuit transmits the second reference clock signal extracted from the signal received by the information reception circuit to the reference clock generation device. The reference clock generation device outputs a third reference clock signal according to the second reference clock signal output from the clock transmission circuit. This third reference clock signal is received by the clock receiving circuit.

The clock selection circuit selects a part of the signals from the second reference clock signal extracted from the signal received by the information receiving circuit and the third reference clock signal received by the clock receiving circuit. . The clock synchronization circuit reproduces the fourth reference clock signal in synchronization with the signal selected by the clock selection circuit. The phase signal generator generates a third reference phase signal based on the fourth reference clock signal reproduced by the clock synchronization circuit. The phase difference measuring unit is a control unit that measures the phase difference between the third reference phase signal output from the phase signal generating unit and the second reference phase signal extracted from the signal received by the information receiving circuit. A true reference phase and the phase signal generator based on phase difference information output by the phase difference measuring unit and phase information regarding a second reference phase signal extracted from a signal received by the information receiving circuit. The information of the phase error with respect to the reference phase signal output from is obtained, and the information including the obtained phase error is output to the information transmission circuit.

The phase information interface sends the reference phase signal output from the phase signal generator to another device.
Further, the fourth reference clock signal and the third reference phase signal are applied to the information transmission circuit.

With such a configuration, the reference frequency and the reference phase of the transmitted signal can be collectively managed by one system. Therefore, as compared with the case where the system for managing the frequency and the system for managing the phase are provided independently, the configuration of the equipment is simplified and the equipment cost is reduced. According to a second aspect of the present invention, in the reference signal distribution system according to the first aspect, the control unit transfers information including at least the detected phase error via a network shared by the control unit and another device. And

In the present invention, other devices can input not only the reference phase signal input from the phase information interface, but also information indicating the phase error of the reference phase signal via the network. Therefore, even if the reference phase signal output from a specific device to another device includes a relatively large phase error, the other device may not be able to detect the phase error information input via the network. The phase error of the reference phase signal can be corrected based on

According to a third aspect of the present invention, in the reference signal distribution system according to the first aspect, the clock synchronizing circuit is provided with means for correcting the phase of the fourth reference clock signal, and the phase difference measured by the phase difference measuring section is provided. Is fed back to the phase control input of the clock synchronization circuit to control the phase of the third reference phase signal, and the residual phase error information contained in the third reference phase signal is transmitted to the control unit. It is characterized in that the data is transferred via a network shared with other devices.

In the present invention, since the clock synchronization circuit is controlled according to the phase difference measured by the phase difference measuring section, the phase of the signal output from the clock synchronization circuit can be controlled. That is, it is possible to correct the phase error included in the third reference phase signal.
However, due to the limit of control in the clock synchronization circuit, the corrected third reference phase signal also contains a residual phase error. Therefore, this residual phase error information is transferred to another device via the network shared by the control unit and the other device. Other devices can reproduce a more accurate reference phase signal based on the input residual phase error information.

According to a fourth aspect of the present invention, in the reference signal distribution system according to the first aspect, the phase signal generating section is provided with means for correcting the phase of the third reference phase signal, and the position measured by the phase difference measuring section is measured. A signal corresponding to the phase difference is fed back to the phase control input of the phase signal generator to control the phase of the third reference phase signal, and the information of the residual phase error included in the third reference phase signal is controlled. It is characterized in that the data is transferred via a network shared by the unit and another device.

In the present invention, since the phase signal generator is controlled according to the phase difference measured by the phase difference measurer, the phase error of the third reference phase signal output from the phase signal generator is controlled. Can be corrected to reduce. However,
Due to the limit of control in the phase signal generator, the corrected third reference phase signal also includes a residual phase error. Therefore, this residual phase error information is transferred to another device via the network shared by the control unit and the other device. Other devices can reproduce a more accurate reference phase signal based on the input residual phase error information.

According to a fifth aspect of the present invention, in the reference signal distribution system according to the first aspect, each of the clock synchronization circuit and the phase signal generating section is provided with means for correcting the phase of the third reference phase signal, and the phase difference is provided. A signal corresponding to the phase difference measured by the measurement unit is fed back to the phase control input of the clock synchronization circuit and the phase control input of the phase signal generation unit to control the phase of the third reference phase signal, The residual phase error information included in the reference phase signal No. 3 is transferred via a network shared by the control unit and another device.

According to the present invention, the clock synchronizing circuit and the phase signal generator are controlled according to the phase difference measured by the phase difference measuring unit, so that the third reference phase output from the phase signal generator is controlled. It can be corrected to reduce the phase error of the signal. However, due to the limit of control in the clock synchronization circuit and the phase signal generator, the corrected third reference phase signal also contains a residual phase error. Therefore, this residual phase error information is transferred to another device via the network shared by the control unit and the other device. Other devices can reproduce a more accurate reference phase signal based on the input residual phase error information.

According to a sixth aspect of the present invention, there is provided the reference signal distribution system according to the first aspect, further comprising means for measuring a round trip transmission delay time of a signal in a communication path between the phase information interface and another device, and the round trip transmission. The phase information according to the delay time is transferred via a network shared by the control unit and another device. Due to the delay of the signal in the transmission path, the reference phase signal transmitted from a specific device and reaching another device causes a phase difference with respect to the reference phase signal transmitted from the specific device. In the case where a signal is transmitted from a specific device to another device and the signal received by the other device to which the signal is transmitted is immediately returned to the specific device, the signal is transmitted in the specific device. The round trip transmission delay time can be measured. The phase difference can be obtained from this round-trip transmission delay time.

In the present invention, the phase information corresponding to the round-trip transmission delay time is transferred via the network shared by the control unit and the other device, so that the phase shift occurs in the other device. The reference phase signal can be corrected by itself. According to a seventh aspect of the present invention, in the reference signal distribution system according to the first aspect, the third divider is connected to a first frequency divider for inputting and dividing the third reference clock signal and an output of the first frequency divider. A phase comparator, an adder connected to the output of the phase comparator, a filter connected to the output of the adder, a frequency variable oscillator connected to the output of the filter, and the frequency variable oscillator outputs A phase-locked oscillator composed of a second frequency divider for inputting the frequency-divided result to the phase comparator is provided in the clock-synchronized circuit, and the phase-difference measuring unit is responsive to the phase difference measured by the phase-difference measuring section. A signal is applied to the input of the adder as a control signal.

In the seventh aspect, the signal output from the variable frequency oscillator can be output as the fourth reference clock signal. The phase difference between the third reference clock signal and the fourth reference clock signal can be adjusted by the control signal input to the adder. The phase difference of the fourth reference clock signal can be corrected by controlling the phase difference according to the phase difference measured by the phase difference measuring unit.

According to an eighth aspect of the present invention, in the reference signal distribution system according to the first aspect, at least one of a frequency divider having a function of controlling a start phase of frequency division and a phase delay generator having a function of controlling a delay time is provided. The phase signal generator is characterized in that the phase of the third reference phase signal output from the phase signal generator is controlled by a control signal input to the phase signal generator.

By using a frequency divider having a function of controlling the start phase of frequency division, the phase of the signal output by the frequency divider can be controlled. Also, when a phase delay generator having a function of controlling the delay time is used, the phase of the signal output by the phase delay generator can be controlled. According to a ninth aspect of the present invention, in the reference signal distribution system according to the first aspect, the third divider is connected to a first frequency divider for inputting and dividing the third reference clock signal and an output of the first frequency divider. A phase comparator, an adder connected to the output of the phase comparator, a filter connected to the output of the adder, a frequency variable oscillator connected to the output of the filter, and the frequency variable oscillator outputs A phase-locked oscillator composed of a second frequency divider for inputting the frequency-divided result to the phase comparator is provided in the clock-synchronized circuit, and the phase-difference measuring unit is responsive to the phase difference measured by the phase-difference measuring section. A signal is applied as a control signal to the input of the adder, and at least one of a frequency divider having a function of controlling a start phase of frequency division and a phase delay generator having a function of controlling a delay time is used to generate the phase signal. Set up Te, characterized in that inputs a signal corresponding to the phase difference the phase difference measurement unit was measured as a phase control signal to the phase signal generating portion.

In the ninth aspect, the clock synchronization circuit and the phase signal generator have a function of controlling the phase of each signal. Further, since the signal corresponding to the phase difference measured by the phase difference measuring unit is input to the clock synchronization circuit and the phase signal generating unit as the phase control signal, the phase of the third reference phase signal output from the phase signal generating unit The error can be reduced.

According to a tenth aspect of the present invention, in the reference signal distribution system according to the first aspect, a plurality of signal distribution units including at least the information transmitting circuit, the information receiving circuit, the clock transmitting circuit, the clock receiving circuit, the clock selecting circuit and the clock synchronizing circuit. A signal received by the information receiving circuit and a third reference clock signal received by the clock receiving circuit are transmitted from at least one of the signal distributing units to a clock selecting circuit of another signal distributing unit. The clock selection circuit of each of the signal distribution units selects a part of the signals obtained from the signal distribution unit and the signals arriving from another signal distribution unit. And

In the tenth aspect, since the signals received by each of them can be commonly used by the plurality of signal distribution units, the degree of freedom of signals selected by each signal distribution unit is increased.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) FIG. 1 shows an embodiment of a reference signal distribution system according to the present invention.
Will be described with reference to. This form corresponds to claim 1.

FIG. 1 is a block diagram showing the configuration of the reference signal distribution system of this embodiment. The reference signal distribution system shown in FIG. 1 distributes a signal serving as a frequency and phase reference to a transmission terminal station device and a switching device used in a digital communication network. In this aspect, the information transmitting circuit, the information receiving circuit, the clock transmitting circuit, the clock receiving circuit, the clock selecting circuit, the clock synchronizing circuit, the phase signal generating unit, the phase difference measuring unit, the control unit, and the phase information interface according to claim 1, The information transmitting circuit 22, the information receiving circuit 11, the clock transmitting circuit 13, the clock receiving circuit 15, the clock selecting circuit 16, the clock synchronizing circuit 17, the phase signal generating unit 18,
It corresponds to the phase difference measuring unit 20, the control unit 21, and the phase information interface 19.

The reference signal distribution system shown in FIG. 1 has an information receiving circuit 11, a clock selecting circuit 12, a clock transmitting circuit 13, a clock receiving circuit 15, and a clock selecting circuit 1.
6, clock synchronization circuit 17, phase signal generation unit 18, phase information interface 19, phase difference measurement unit 20, control unit 2
1 and the information transmission circuit 22. The information transmission circuit 22 sends a transmission signal 65 to another device.
Further, the reception signal 51 from another device is the information reception circuit 1
Received at 1. Each of the reception signal 51 and the transmission signal 65 includes reference phase information including a reference clock signal serving as a frequency reference used for signal transmission, a reference phase signal serving as a phase reference, and error information of the reference phase signal. Other general information is included.

In FIG. 1, it is assumed that the reception signal 51 and the transmission signal 65 of three independent systems are transmitted to three other devices. Of the received signal 51 received by the information receiving circuit 11, the reference clock signal is applied to the clock selection circuit 12 and the clock selection circuit 16 as the reference clock signal 52. The reference phase signal of the received signal 51 is applied to the phase difference measuring unit 20 as the reference phase signal 53. Further, the reference phase information of the received signal 51 is applied to the control unit 21 as the reference phase information 54.

The clock selection circuit 12 selects a part of the reference clock signals 52 of a plurality of systems. The selected reference clock signal 52 is input to the clock transmission circuit 13 as the reference clock signal 55. Clock transmission circuit 1
3 applies the inputted reference clock signal 55 as the reference clock signal 56 to the reference clock generator 14. The reference clock generator 14 generates a reference clock signal 57 according to the input reference clock signal 56. The reference clock signal 57 is received by the clock receiving circuit 15. The clock receiving circuit 15 applies the received reference clock signal 57 to the clock selection circuit 16 as the reference clock signal 58.

The clock selection circuit 16 is the information receiving circuit 1
Reference clock signals 52 of a plurality of systems inputted from 1 and the reference clock signal 5 inputted from the clock receiving circuit 15
Any one of 8 is selected. The selected signal is output from the clock selection circuit 16 as the reference clock signal 59. The clock synchronization circuit 17 synchronizes with the reference clock signal 59 input thereto and synchronizes with the reference clock signal 6
Play 0. The clock synchronization circuit 17 is provided to remove noise such as jitter contained in the reference clock signal 59. The reference clock signal 60 reproduced by the clock synchronization circuit 17 is applied to the information transmission circuit 22 and the phase signal generation unit 18, respectively.

The phase signal generator 18 has a built-in frequency divider. The phase signal generator 18 divides the input reference clock signal 60 to generate a reference phase signal 61. The reference phase signal 61 generated by the phase signal generation unit 18 is the phase information interface 19 and the phase difference measurement unit 2
0 and the respective inputs of the information transmission circuit 22 are applied.

The phase information interface 19 outputs the input reference phase signal 61 as a reference phase signal 62 to another device 23. The phase difference measuring unit 20 uses the phase of the reference phase signal 61 output from the phase signal generating unit 18 as a reference, and the reference phase signal 53 output from the information receiving circuit 11
Each phase of is measured. The phase difference obtained by this measurement, that is, the information on the phase error included in the reference phase signal 53 is output from the phase difference measuring unit 20 as the reference phase information 63.

Based on the reference phase information 63 output from the phase difference measuring section 20 and the reference phase information 54 output from the information receiving circuit 11, the control section 21 includes reference phase information including actual phase error information. 64 is applied to the information transmission circuit 22. As the reference phase information 64, the reference phase information 54,
Both 63 are output, or the sum or difference of both is output.

The information transmitting circuit 22 is the clock synchronizing circuit 1.
The reference clock signal 60 reproduced in step 7, the reference phase signal 61 generated by the phase signal generator 18, and the reference phase information 64 output from the controller 21 can be included in the transmission signal 65 and transmitted. . In the reference signal distribution system shown in FIG. 1, the frequency (reference clock signal) and the phase (reference phase signal and reference phase information) of the reference signal are managed using a common circuit. Therefore, the system can be configured with relatively few facilities.

(Second Embodiment) One embodiment of the reference signal distribution system of the present invention will be described with reference to FIG. This form corresponds to claim 2. FIG. 2 is a block diagram showing the configuration of the reference signal distribution system of this embodiment. This form is a modification of the first embodiment,
2, the same elements as those in FIG. 1 are designated by the same reference numerals. For the same parts, the following description will be omitted.

In this form, the network of claim 2 corresponds to the network 66. In the reference signal distribution system of FIG. 2, the control unit 21B controls the reference phase information 54,
The reference phase information 64 corresponding to 63 is output not only to the information transmission circuit 22 but also to the other device 23 via the network 66. In the example of FIG.
Since the correction control of the phase of the reference phase signal 62 input to the other device 23 is not performed, the reference phase signal 62 may include a relatively large phase error. However, in another device 23, even if the input reference phase signal 62 includes a phase error, the network 6
The phase error of the reference phase signal 62 can be corrected on the basis of the phase error information included in the reference phase information 64 input from 6.

(Third Embodiment) FIGS. 3 and 5 show one embodiment of the reference signal distribution system of the present invention.
~ It demonstrates with reference to FIG. This form corresponds to claims 3 to 5 and claims 7 to 9. FIG. 3 is a block diagram showing the configuration of the reference signal distribution system of this embodiment. FIG. 5 is a block diagram showing the configuration of the clock synchronization circuit. FIG. 6 is a block diagram showing a configuration example (1) of the phase signal generator. FIG. 7 shows a configuration example of the phase signal generator (2).
It is a block diagram showing.

This embodiment is a modification of the second embodiment. 3, the same elements as those of FIG. 2 are shown with the same reference numerals. For the same parts, the following description will be omitted. In this form, the first of claims 7 and 9
The frequency divider, the phase comparator, the adder, the filter, the frequency variable oscillator, and the second frequency divider of the frequency divider 31, the phase comparator 32, the adder 33, the filter 34, the voltage controlled oscillator 35, and the frequency divider, respectively. Corresponds to the divider 36. The frequency divider and the phase delay generator of claims 8 and 9 respectively correspond to the frequency divider 41 and the phase delay generator 43 having the start phase control function.

The clock synchronization circuit 17 shown in FIG.
It is configured like. Referring to FIG. 5, the clock synchronization circuit 17 is composed of a frequency divider 31, a phase comparator 32, an adder 33, a filter 34, a voltage controlled oscillator 35, and a frequency divider 36. The frequency divider 31 outputs a signal obtained by dividing the reference clock signal 59 input to the clock synchronization circuit 17 by a predetermined division ratio. The signal output from the frequency divider 31 is applied to one input in1 of the phase comparator 32. The frequency divider 3 is connected to the other input in2 of the phase comparator 32.
The signal output by 6 is applied. The phase comparator 32 is 2
It outputs a signal corresponding to the phase difference between the signals applied to the two inputs in1 and in2.

The adder 33 outputs the result of adding the signal output from the phase comparator 32 and the phase control signal 71 output from the phase difference measuring section 20B shown in FIG. As the adder 33, one configured by a digital circuit or an analog circuit is used according to the input signal.

The signal output from the adder 33 is the filter 3
Applied to the input of the voltage controlled oscillator 35 through 4. The voltage controlled oscillator 35 oscillates at a frequency according to the input signal. The signal output from the voltage controlled oscillator 35 is output as the reference clock signal 60. Further, the signal output from the voltage controlled oscillator 35 is input to the frequency divider 36. The frequency divider 36 outputs a signal obtained by dividing the reference clock signal 60 by a predetermined frequency division ratio. This signal is fed back to the input in2 of the phase comparator 32.

Therefore, the clock synchronization circuit 17 operates as a phase locked oscillator. That is, a phase difference (offset) corresponding to the phase control signal 71 is provided between the input reference clock signal 59 and the output reference clock signal 60.
Can be given. For example, if the phase comparator 32 is 2
The difference (in1-in2) between the two inputs is output, and the adder 33
When a result of simple addition of two inputs is output, assuming that the phase of the input in1 of the phase comparator 32 is 0 and the phase control input of “Δt” is applied to the phase control signal 71, The phase of the signal output from the phase comparator 32 is “−Δ.
In the case of "t", the output of the adder 33 becomes 0, and the clock synchronization circuit 17 enters the synchronization state. In that state, the phase of the reference clock signal 60 becomes “Δt”, so that a phase difference of “Δt” occurs between it and the reference clock signal 59.

The phase signal generator 18 shown in FIG.
Either of the configurations of FIGS. 6 and 7 can be adopted. In FIG. 6, a frequency divider 41 having a start phase control function is provided.
Is used to configure the phase signal generator 18. By inputting the phase control signal 72 output from the phase difference measuring section 20B shown in FIG. 3 to the frequency divider 41 having the start phase control function, the reference phase signal 61 output from the phase signal generating section 18 is input.
You can adjust the phase of. That is, an offset can be given to the phase between the reference clock signal 60 and the reference phase signal 61.

In FIG. 7, the frequency divider 42 and the phase delay generator 43 connected to the output thereof form the phase signal generator 18.
Is configured. The phase delay generator 43 can control the internal signal delay time according to the phase control signal 72. That is, a phase difference according to the phase control signal 72 can be given between the input and the output of the phase delay generator 43. The phase difference measuring unit 20B in FIG. 3 measures each phase of the reference phase signal 53 output from the information receiving circuit 11 with the phase of the reference phase signal 61 output from the phase signal generating unit 18 as a reference. The phase difference obtained by this measurement, that is, the information on the phase error included in the reference phase signal 53 is output from the phase difference measuring unit 20 as the reference phase information 63.

The phase control signals 71 and 72 output by the phase difference measuring section 20B are also signals corresponding to the phase error obtained by the measurement. The phase control signal 71 is rounded so that the accuracy of the information becomes equal to the phase control resolution of the clock synchronization circuit 17. Similarly, the phase control signal 72 is rounded so that the accuracy of the information becomes equal to the phase control resolution of the phase signal generator 18.

That is, according to the phase error detected by the phase difference measuring section 20B, the clock synchronization circuit 17 and the phase signal generating section 18 control the phase of the reference phase signal 61 so that the phase error becomes zero. The phase error included in the reference phase signal 61 is significantly reduced. In the example of FIG. 3, both the clock synchronization circuit 17 and the phase signal generator 18 are controlled so as to correct the phase error. However, one of the clock synchronization circuit 17 and the phase signal generator 18 is phase controlled. The phase error included in the reference phase signal 61 is significantly reduced even by performing the above.

However, even when such phase control is performed, the reference phase signal 61 contains a residual phase error due to the control limit. This residual phase error is measured by the phase difference measuring unit 20B and is used as the reference phase information 63 by the control unit 2
Applied to 1C. The control unit 21C transfers the input reference phase information 63 to another device 23 via the network 66.

In another device 23, the reference phase signal 62 containing the residual phase error is received, but the network 66
The residual phase error of the reference phase signal 62 can be corrected by itself based on the reference phase information 63 input via the. (Fourth Embodiment) One embodiment of the reference signal distribution system of the present invention will be described with reference to FIG.
This form corresponds to claim 6.

FIG. 4 is a block diagram showing the configuration of the reference signal distribution system of this embodiment. This form is a modification of the third embodiment. 4, the same elements as those of FIG. 3 are denoted by the same reference numerals. For the same parts, the following description will be omitted. In the reference signal distribution system of FIG. 4, the transmission delay time of the signal in the transmission path between the phase information interface 19 and the other device 23 is measured. That is, the reference phase signal 61 input to the phase information interface 19 is transmitted to the other device 23 through the outward path 62a. This signal is returned at the receiving end of the other device 23 and reaches the phase information interface 19 through the return path 62b.

The time from when the phase information interface 19 sends out the reference phase signal 61 to when it returns is
It is a round-trip transmission delay time of a signal in the outward path 62a and the inward path 62b. This round trip transmission delay time is calculated by the phase difference measuring unit 2
0C is detected by measuring the time difference (phase difference) between the reference phase signal 61 input to it and the return path reference phase signal 75.

Assuming that the transmission delay times of the outgoing route 62a and the returning route 62b are equal, half the detected round-trip transmission delay time is taken as the transmission delay time of the outgoing route 62a from the phase information interface 19 to another device 23. Can be regarded as The phase difference measuring unit 20C includes the information of the time difference (phase difference) measured as described above in the reference phase information 63 and sends it to the control unit 21D. This reference phase information 63 is
Under the control of the control unit 21D, the data is transferred to another device 23 via the network 66.

Therefore, the other device 23 inputs the phase error corresponding to the transmission delay error contained in the reference phase signal 61 input from the phase information interface 19 via the forward path 62a from the control section 21D via the network 66. It can be corrected by the reference phase information 63. (Fifth Embodiment) One embodiment of the reference signal distribution system of the present invention will be described with reference to FIGS. This form corresponds to claim 10.

FIG. 8 is a block diagram showing the configuration of the reference signal distribution system of this embodiment. FIG. 9 is a block diagram showing the configuration of the signal distribution unit shown in FIG. This form is the first
It is a modification of the embodiment. 8 and 9,
The same elements as those in FIG. 1 are denoted by the same reference numerals. For the same parts, the following description will be omitted. In this aspect, the signal distribution unit of claim 10 corresponds to the signal distribution units 100A, 100B, 100C.

As shown in FIG. 8, the reference signal distribution system of this embodiment has three signal distribution units 100A and 100A.
It is equipped with B and 100C. Each of these signal distribution units 100A, 100B, 100C is configured as shown in FIG. Referring to FIG. 9, the signal distribution unit 100A includes an information receiving circuit 11, a clock transmitting circuit 13, a clock receiving circuit 15, and a clock selecting circuit 1.
6, clock synchronization circuit 17, phase signal generation unit 18, phase information interface 19, phase difference measurement unit 20, control unit 2
1 and an information transmission circuit 22.

In this example, the received signal 51 input to the information receiving circuit 11 is only one system as shown in FIG.
The transmission signal 65 transmitted from the information transmission circuit 22 also has only one system.

All the signals included in the received signal 51 received by the information receiving circuit 11 are received signals 91 (B,
It is output from the signal distribution unit 100A as C).
The reference clock signals 92 (B, C) input from the outside of the signal distribution unit 100A are also input to the clock selection circuit 16. Further, the clock receiving circuit 1
The reference clock signal 57 received from the reference clock generator 14 by 5 is output to the outside of the signal distribution unit 100A as the reference clock signal 93 (B, C). Also,
The reference clock signal 94 (B, C) input from the outside of the signal distribution unit 100A is input to the clock selection circuit 16.

The signal distribution units 100B and 100C are similar to those shown in FIG. As shown in FIG. 8, the received signal 91 (B,
C) are signal distribution units 100B and 100C, respectively.
Is input as a reference clock signal 92. In addition, the reference clock signal 9 input to the signal distribution unit 100A
2 (B, C) are signal distribution units 100B,
The received signal 91 is output from 100C.

Further, the reference clock signal 93 (B, C) output from the signal distribution unit 100A is supplied to the signal distribution units 100B and 100C, respectively.
Is entered as. The reference clock signals 94 (B, C) input to the signal distribution unit 100A are the reference clock signals 93 output from the signal distribution units 100B and 100C, respectively.

Signal distribution units 100A, 100B, 1
Each of the clock selection circuits 16 of 00C selects any one of the reference clock signal 52, the reference clock signal 92, the reference clock signal 58, and the reference clock signal 94 which are input thereto. In the reference signal distribution system of FIG. 8, a plurality of signal distribution units 100A, 100
B and 100C can share each other's signals.

[0065]

As described above, according to the present invention, since the reference frequency and the reference phase are integrally managed, a relatively small amount of equipment is added to the conventional reference signal distribution system that manages only the reference frequency. By itself, it becomes possible to manage both the reference frequency and the reference phase. Therefore, the system configuration of the reference signal distribution system is simplified and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a reference signal distribution system according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a reference signal distribution system according to a second embodiment.

FIG. 3 is a block diagram showing a configuration of a reference signal distribution system according to a third embodiment.

FIG. 4 is a block diagram showing a configuration of a reference signal distribution system according to a fourth embodiment.

FIG. 5 is a block diagram showing a configuration of a clock synchronization circuit.

FIG. 6 is a block diagram showing a configuration example (1) of a phase signal generation unit.

FIG. 7 is a block diagram showing a configuration example (2) of a phase signal generation unit.

FIG. 8 is a block diagram showing a configuration of a reference signal distribution system according to a fifth embodiment.

9 is a block diagram showing a configuration of the signal distribution unit of FIG.

FIG. 10 is a block diagram showing a configuration of a conventional reference signal distribution system.

[Explanation of symbols]

11 information receiving circuit 12 clock selecting circuit 13 clock transmitting circuit 14 reference clock generator 15 clock receiving circuit 16 clock selecting circuit 17 clock synchronizing circuit 18 phase signal generating section 19 phase information interface 20 phase difference measuring section 21 control section 22 information transmitting circuit 23 Other Device 31 Frequency Divider 32 Phase Comparator 33 Adder 34 Filter 35 Voltage Controlled Oscillator 36 Frequency Divider 41 Frequency Divider 42 Frequency Divider 43 Phase Delay Generator 51 Received Signals 52, 55 , 56, 57, 58, 59, 60 Reference clock signal 53, 61, 62 Reference phase signal 54, 63, 64 Reference phase information 62a Forward 62b Return 65 Transmission signal 66 Network 71, 72 Phase control signal 75 Return reference phase signal 91 Received signals 92, 93, 94 Reference clock signal 100A, 100B, 100C signal distribution unit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-327072 (JP, A) JP-A-8-251149 (JP, A) JP-A-5-14300 (JP, A) JP-A-3- 286643 (JP, A) JP 60-253344 (JP, A) JP 5-22268 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/00 H04L 3 / 00 H04L 7/033

Claims (10)

(57) [Claims] 1. A first reference clock signal serving as a frequency reference, a first reference phase signal serving as a phase reference, and the first reference clock signal.
And a second reference clock signal input from the other device to the particular device, the information transmitting circuit sending a signal including information about the reference phase signal of the other device from the particular device to the other device. An information receiving circuit for receiving a signal including a phase signal and information about the second reference phase signal, and a clock for transmitting a second reference clock signal extracted from the signal received by the information receiving circuit to a reference clock generator. A transmitter circuit, a clock receiver circuit for receiving a third reference clock signal output by the reference clock generator according to a second reference clock signal output by the clock transmitter circuit, and a signal received by the information receiver circuit A clock for selecting a part of the second reference clock signal extracted from the second reference clock signal and the third reference clock signal received by the clock receiving circuit. A clock selection circuit, and a fourth circuit in synchronization with the signal selected by the clock selection circuit.
A clock synchronizing circuit for regenerating the reference clock signal, a phase signal generating section for generating a third reference phase signal based on the fourth reference clock signal reproduced by the clock synchronizing circuit, and an output from the phase signal generating section A third reference phase signal to be generated and a second extracted from the signal received by the information receiving circuit.
A phase difference measuring section for measuring a phase difference with the reference phase signal of, and a phase relating to the second reference phase signal extracted from the information received by the information receiving circuit and the information of the phase difference output by the phase difference measuring section. Based on the information, to obtain the information of the phase error between the true reference phase and the reference phase signal output from the phase signal generation unit, and a control unit that outputs information including the obtained phase error to the information transmission circuit. A phase information interface for transmitting the reference phase signal output from the phase signal generator to another device, and providing the fourth reference clock signal and the third reference phase signal to the information transmission circuit. A reference signal distribution system characterized by. 2. The reference signal distribution system according to claim 1, wherein the control unit transfers information including at least the detected phase error via a network shared by the control unit and another device. And a reference signal distribution system. 3. The reference signal distribution system according to claim 1, wherein the clock synchronization circuit is provided with a means for correcting the phase of the fourth reference clock signal, and the means is provided for responding to the phase difference measured by the phase difference measuring section. The signal is fed back to the phase control input of the clock synchronization circuit to control the phase of the third reference phase signal, and the information of the residual phase error contained in the third reference phase signal is supplied to the control unit and another device. A reference signal distribution system characterized by being transferred via a network shared by and. 4. The reference signal distribution system according to claim 1, wherein the phase signal generating section is provided with a means for correcting the phase of the third reference phase signal, and the phase signal generating section is responsive to the phase difference measured by the phase difference measuring section. The obtained signal is fed back to the phase control input of the phase signal generator to control the phase of the third reference phase signal, and the information of the residual phase error included in the third reference phase signal is used by the control unit and others. A reference signal distribution system characterized in that the data is transferred via a network shared with other devices. 5. The reference signal distribution system according to claim 1, wherein each of the clock synchronization circuit and the phase signal generation unit is provided with means for correcting the phase of the third reference phase signal, and the phase difference measurement unit includes: A signal corresponding to the measured phase difference is fed back to the phase control input of the clock synchronization circuit and the phase control input of the phase signal generator to control the phase of the third reference phase signal, and the third reference A reference signal distribution system, wherein information on a residual phase error included in a phase signal is transferred via a network shared by the control unit and another device. 6. The reference signal distribution system according to claim 1, further comprising means for measuring a round trip transmission delay time of a signal on a communication path between the phase information interface and another device, A reference signal distribution system, wherein the corresponding phase information is transferred via a network shared by the control unit and another device. 7. The reference signal distribution system according to claim 1, which is connected to a first frequency divider for inputting and dividing the frequency of the third reference clock signal, and an output of the first frequency divider. A phase comparator, an adder connected to the output of the phase comparator, a filter connected to the output of the adder, a frequency variable oscillator connected to the output of the filter, and the frequency variable oscillator outputs A phase-locked oscillator composed of a second frequency divider for inputting the frequency-divided result to the phase comparator is provided in the clock-synchronized circuit, and the phase-difference measuring unit is responsive to the phase difference measured by the phase-difference measuring section. A reference signal distribution system, wherein a signal is applied as a control signal to an input of the adder. 8. The reference signal distribution system according to claim 1, wherein at least one of a frequency divider having a function of controlling a start phase of frequency division and a phase delay generator having a function of controlling a delay time is used to generate the phase signal. A reference signal distribution system, characterized in that the phase of a third reference phase signal output from the phase signal generation unit is controlled by a control signal input to the phase signal generation unit. 9. The reference signal distribution system according to claim 1, further comprising: a first frequency divider for inputting and dividing the third reference clock signal, and an output of the first frequency divider. A phase comparator, an adder connected to the output of the phase comparator, a filter connected to the output of the adder, a frequency variable oscillator connected to the output of the filter, and the frequency variable oscillator outputs A phase-locked oscillator composed of a second frequency divider for inputting the frequency-divided result to the phase comparator is provided in the clock-synchronized circuit, and the phase-difference measuring unit is responsive to the phase difference measured A signal is applied as a control signal to the input of the adder, and at least one of a frequency divider having a function of controlling a start phase of frequency division and a phase delay generator having a function of controlling a delay time is used to generate the phase signal. Set up In addition, the reference signal distribution system is characterized in that a signal corresponding to the phase difference measured by the phase difference measuring unit is input to the phase signal generating unit as a phase control signal. 10. The reference signal distribution system according to claim 1, wherein a plurality of signal distribution units including at least the information transmission circuit, the information reception circuit, the clock transmission circuit, the clock reception circuit, the clock selection circuit, and the clock synchronization circuit are provided. At least one of the signal distribution units is configured to send a signal received by the information receiving circuit and a third reference clock signal received by the clock receiving circuit to a clock selection circuit of another signal distribution unit. The clock selection circuit of each of the signal distribution units selects a part of the signals from the signals obtained inside the signal distribution unit and the signals arriving from another signal distribution unit. Signal distribution system.