JP3477803B2 - Delay device and delay phase output device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay device, and more particularly to a delay device optimal for generating a plurality of delay phases used for accurately recording data in a magneto-optical disk device and its peripheral circuits. The present invention relates to a delay phase output device including.

BACKGROUND OF THE INVENTION As a method for recording data in a magneto-optical disk device at high density, a method using laser pulse emission magnetic field modulation is known. This is because when an external magnetic field is applied to the disk in the recording direction and a laser beam is applied to this to apply heat, the coercive force decreases and the Curie point temperature T
In c, the property of becoming zero is used. That is, the temperature of the recording portion of the magneto-optical disk is raised above the Tc point by an optical head such as a semiconductor laser, and the temperature is lowered while the external magnetic field is applied, and the magnetization is directed in the direction of the external magnetic field.

When data is recorded using a data clock which is an external clock such as a sample servo system, an accurate delay phase is given to the data clock to record the data at an accurate position on the disk format. It is necessary to accurately set the extinction position and also to separately set the phase of the magnetic field modulation data in accordance with the laser emission timing.

When setting each phase, for correction of recording pits due to the thermal response of the disk, correction of circuit characteristics such as delay of the laser drive circuit, and correction of changes in environmental factors such as disk temperature during use. There is a demand for a delay device that can be set arbitrarily. In consideration of the case where the necessary correction amount is large, the delay phase to be applied to such a data clock is the maximum of the data clock 1
It is also necessary to cover the range up to the period.

Also, "laser fall" for setting the data recording position, "laser rise" for setting the laser pulse width, and "magnetic field timing" for requiring a saturation magnetic field at the "laser fall" time point. At least 3
The phase is required, thus determining the exact position of the recording pits on the disc.

[0006]

[Prior art]

(Conventional circuit example (1)) Conventionally, a plurality of delay elements DL1, DL2, DL3, ..., DL15 as shown in FIG. 1 are connected in series, and a data clock Dck is used as a first stage delay element DL.
1 and output from each delay element are sequentially delayed data clocks d0, d1, d2, ..., d14, d
15 is selected by the selection circuit (16 alternatives) 2
There is known a delay line 4 which obtains a desired delay phase data clock Ddck by arbitrarily selecting it according to el.

In the conventional circuit example (1) shown in FIG. 1, accumulation of changes in delay amount of each delay element due to environmental factors such as temperature, which will be described later, becomes a problem.

(Conventional Circuit Example (2)) Next, although the present application has not been published yet, the inventor of the present application accumulated the delay amount change of each delay element due to the temperature or the like of the conventional circuit example (1). I invented a delay line that solved the above problem and applied for it as Japanese Patent Application No. 5-337,679 (December 28, 1993).

As shown in FIG. 2, this conventional circuit example (2) is a delay line 6 having a PLL inside and a plurality of delay elements DL1 to D16 whose delay amounts are controlled according to an input voltage. And a phase matching means 8 using a PLL and a data clock Dck for the first stage delay element DL1.
Sequentially input data clocks d0, d1, d2, ..., d14, d15
Selection circuit 1 for arbitrarily selecting the signal according to the selection signal Sel
With 0 and. Here, the phase matching means 8 has a phase comparator (PC) 12, a loop filter (LPF) 14, and a voltage controller (VC) 16.

According to the structure of the delay line 6, since the phase adjusting means 8 is provided, the first stage input clock d
The phase of 0 and the output clock d16 of the final stage are controlled so as to always coincide with each other, and the problem of the accumulation of the delay amount change due to the temperature of the delay element DL and the like is solved.

(Conventional Circuit Example (3)) Considering the entire magneto-optical disk device in which the delay line 6 is used (see FIG. 5), the conventional circuit example (2) described above is shown in detail in FIG. 4A. As shown, there is a PLL circuit 18 in the preceding stage of the delay line 6, and the PLL circuit 18 and the delay line 6 (having the phase matching means 8 inside) (FIG. 2).
There are circuit blocks that are substantially the same as and become redundant.

[0012] Therefore, although this application has not yet been published at this point in time, the inventor of the present application has performed voltage control in which the redundancy of the circuit between the PLL circuit 18 and the delay line 6 in the preceding stage which the conventional circuit example (2) has is eliminated. Invented oscillator 20, and applied for patent 5
-Filed as 337, 345 (December 28, 1993).

As shown in FIG. 3, this conventional circuit example (3) is a voltage controlled oscillator 20 having a ring oscillator 22 inside, and the delay amount is controlled according to the input voltage. Output d1 of the inverter Inv15
5, a ring oscillator 22 in which an odd number of inverters Inv1 to Inv15 having 5 as an input d0 of the first-stage inverter Inv1 is connected in a ring shape, and data clocks d1 to d15 (= d0) output from each inverter Inv.
Selection circuit 2 for arbitrarily selecting the signal according to the selection signal Sel
4 and.

The selection circuit 24 is a conventional circuit example (1).
Unlike (2) and (2), there is a feature in the clock selection method.
That is, the data clocks d2, d4, ..., d14 appearing at the output terminals of the even-numbered inverters in the order of the data clocks d1 appearing at the output terminals of the odd-numbered inverters corresponding to the monotonous increase of the selection signal Sel. , D3
..., d13 are taken out in this order.

According to the conventional circuit example (3), the peripheral circuit of the voltage controlled oscillator 20 is as shown in FIG. 4B, and the peripheral circuit when the conventional circuit example (2) of FIG. 4A is used. By comparison, the voltage controlled oscillator 20 in the PLL circuit 34 of FIG. 4B is the voltage controlled oscillator (Osc) of FIG. 4A.
PLL with 30 and delay line (DL) 6
The circuit 18 and the delay line 6 are integrated,
Avoids circuit redundancy.

[0016]

Conventional circuit example (1)
In FIG. 1, since it is difficult to compensate for the performance change of the delay element due to the environmental factor (for example, temperature), the phase of the delay phase data clock Ddck deviates from the set value. For example, when the delay amount characteristic of each delay element DL changes by ± d [nsec] with respect to the temperature change range during use, the data clock dn-1 passing through the delay element DL by (n-1) stages is ± (n-1) d [ns at the maximum for the set value
There is a problem that a deviation of [ec] occurs.

The conventional circuit example (2) solves the problem of the accumulation of the change in the delay amount. However, this conventional circuit example (2) (FIG. 2) has a problem of redundancy of the PLL circuit as described above.

Further, in the conventional circuit example (2), the data clock Ddck of the delay phase is single, but as described above, the magneto-optical disk device "laser rising" or "laser rising" at the time of data recording. Since at least three delay phases (phase variables) of "laser fall" and "magnetic field timing" are required, it is assumed that the data clock Dck (reference clock) input to the delay element array is adjusted to any one. However, at least the remaining two delay phase data clocks Ddck are required.

To this end, the delay lines 6 shown in FIG. 2 have heretofore been provided separately for the required number of delay phases, for example "laser rising", "laser falling" and "magnetic field timing". There was a problem that three pieces had to be prepared.

Next, the conventional circuit example (3) (FIG. 3) solves the problem of the redundancy of the PLL circuit as described above. However, even in this conventional circuit example (3), for example, when at least three delay phases (phase variables) of "laser rising", "laser falling", and "magnetic field timing" are required, There is a problem that three voltage controlled oscillators 20 shown in FIG. 3 must be prepared separately.

Therefore, the present invention is a further improvement of the conventional circuit examples (2) and (3), and the delay line 6 is separately provided by the number of delay phases according to these conventional circuit examples.
Another object is to solve the problem of having to prepare the voltage controlled oscillator 20.

[0022]

A delay device according to the present invention is, for example, as shown in FIG. 7, a plurality of stages of variable delay elements (DL1 to DL1) connected in series.
6), the delay amount is controlled to control the first stage input clock (Dck = d0) and the last stage output clock (d1) of the delay element.
A plurality of phase matching means (8) for matching the phase with 6) and a plurality of output clocks (d) of the delay elements of arbitrary stages are selectively taken out corresponding to each input selection signal (Sel to Sel ″). It is possible to output a plurality of delay phases (Ddck to Ddck ") by including the clock selecting means (10 to 10").

Further, the delay device (54) is
Each delay element (DL) has an even number of inverters (Inv1, Inv2) having equal characteristics.

The delay phase output device according to the present invention is provided with a selection signal setting circuit (52), a delay device (54) and a laser drive pulse forming circuit (56) as shown in FIG. The setting circuit (52) temporarily sets each selection signal (Sel to Sel ″) and outputs the plurality of registers (72) to the delay device (54).
The delay device (54) has a plurality of stages of variable delay amount variable delay elements connected in series, and controls the delay amount to output a first stage input clock and a final stage output of the delay element. The phase matching means for matching the phase with the clock and the output clock of the delay element at any stage are used as the selection signals (Sel).
~ Sel ") and a plurality of clock selection means for selectively extracting the plurality of delay phases (Ddck ~).
Ddck ″) can be output, and the laser drive pulse forming circuit (56) has a delay phase clock (Ddck) and “laser falling” that determine “laser rising”.
The laser drive signal LDP is formed by receiving the clock (Ddck ′) of the delay phase that determines

Another delay device according to the present invention has an odd number of delay elements (Inv1 to Inv15) having an inversion function in which the delay amount is controlled according to the input voltage, as shown in FIGS. A ring oscillator (22) connected in a ring shape, and delay elements (Inv1 to Inv1).
Clocks (d1 to d1) appearing at the output terminal of Inv15
A plurality of clock selection circuits (2) that selectively take out 5) according to each input selection signal (Sel to Sel ″).
4 to 24 ″) and each clock selection circuit (24
˜24 ″) corresponds to the monotonic increase of the selection signals (Sel to Sel ″), first in the order of the clocks (d2, d4 ... The clock (d1, which appears at the output terminal of the delay element
It is possible to output a plurality of delay phases (Ddck to Ddck ") by the plurality of clock selection circuits (24 to 24") in this order.

Further, in this delay device, the delay element is composed of an inverter (Inv).

Another delay phase output device (6
As shown in FIG. 12, for example, 8) includes a selection signal setting circuit (52), a delay device (70) and a laser drive pulse forming circuit (54), and the selection signal setting circuit (5).
2) has a plurality of registers (72 to 72 ″) for temporarily setting respective selection signals (Sel to Sel ″) and outputting them to the delay device (70), and the delay device (70) is The delay amount is controlled according to the input voltage, and a ring oscillator in which an odd number of delay elements having an inversion function are connected in a ring shape and a clock that appears at the output terminal of each delay element are input to each selection signal (Sel ~ Sel ″)
A plurality of clock selection circuits that are selectively taken out in accordance with each of the clock selection circuits, and each of the clock selection circuits corresponds to a monotonically increasing selection signal supplied to the clock selection circuit. The sequence of clocks appearing on the output terminals,
Next, the clocks are extracted in the order of the clocks appearing at the output terminals of the odd-numbered delay elements, and thus a plurality of delay phases (Ddck to Ddck ″) can be output by the plurality of clock selection circuits, and the laser drive pulse forming circuit (54) Is
A laser drive signal is formed by receiving a delay phase clock (Ddck) that determines the "laser rise" and a delay phase clock (Ddck ') that determines the "laser fall".

[0028]

In the delay device according to the present invention, the phase of the first stage input clock and the last stage output clock of the delay element array are matched by the phase matching means to prevent the delay amount from changing and the output clock of each stage of the delay element. Since there are provided a plurality of selection circuits for selecting in accordance with the selection signal, a plurality of delay phases can be obtained. A delay phase output device according to the present invention uses this delay device, includes a circuit for setting a selection signal in all stages thereof, and a laser drive pulse forming circuit in the rear stage thereof. required in the disk device "laser rising", "laser falling", a plurality of phase delay that Ru using the magnetic field application and the like are obtained.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a delay phase output apparatus including a delay device capable of outputting a plurality of delay phases (phase variables) and a peripheral circuit according to the present invention will be described below in detail with reference to the drawings.

(Circuit Configuration of Magneto-Optical Disk Device) Referring to FIG. 5, a magneto-optical disk device 36 in which the delay device (claim 1) and the delay phase output device (claim 3) according to the present invention are used. The relevant parts will be briefly described.

Reference numeral 38 is a magneto-optical disk, which is driven by a spindle motor 40 to have a constant angular velocity (CAV), for example.
It is driven to rotate. As a servo system for the magneto-optical disk 38, a well-known sample servo system is adopted.

The signal Pprf reproduced by the optical head (H) 42 from the clock pits preformatted in the servo bytes of the magneto-optical disk 38 is sent to the PLL circuit 18 via the RF amplifier 44 and the reproduction signal processing circuit 46. Supplied. The PLL circuit 18 outputs the data clock Dck synchronized with the reproduction signal of the clock pit to the delay phase output device 50 according to the present invention.

The delay phase output device 50 has a built-in delay device 54 capable of outputting a plurality of delay phases according to the present invention. This delay device 5
In No. 4, "Laser rising", "Laser falling", and "Magnetic field timing" required for data recording
3 delay phases are generated. Among these, the magnetic head drive pulse M formed from the "magnetic field timing" delay phase
The HDP is supplied to the pre-encoder 58, and the “laser rising” delay phase and the “laser falling” delay phase are L
The laser drive pulse LDP that is supplied to the DP formation circuit 56 and is formed here is supplied to the laser drive circuit 60.

On the other hand, a host computer (not shown)
The recording data (NRZ data) Din from is supplied to the pre-encoder 58.

Thus, the recording data Din is modulated into NRZI series data in synchronization with the predetermined delayed magnetic head drive pulse MHDP supplied from the delay device 54 of the delay phase output device 50 to the pre-encoder 58, It is supplied to the magnetic head drive circuit 62. And
A magnetic head (MH) 64 for generating an external magnetic field generates a magnetic field corresponding to the modulated data by a magnetic head drive pulse MHD.
It is generated in synchronization with P and applied as a saturation magnetic field on the pits to be recorded on the magneto-optical disk 38.

During this magnetic field application, the delay phase output device 5
A laser drive pulse LDP having a predetermined delay and a laser pulse width set is supplied from the laser drive pulse forming circuit 56 of 0 to the laser drive circuit 60. The optical head (H) is synchronized with this laser drive pulse LDP.
Reference numeral 42 intermittently irradiates the magneto-optical disk 38 with a laser beam at the timing when the saturation magnetic field is applied at the “laser fall” time.

In this way, the modulation data is accurately recorded on the pit to be recorded by the cooperation of the magnetic data applied by the magnetic head 64 and the laser beam irradiation by the optical head 42.

As a result, the recording pits are clearer than in the case of continuous laser beam irradiation. This is because magneto-optical recording (thermal recording) is not performed in the transient state (unstable or gray state) of magnetic field data.

The other parts of the magneto-optical disk device 36 are omitted because they are not necessary for understanding the delay device 54 and the delay phase output device 50 capable of outputting a plurality of delay phases according to the present invention. The present invention provides a delay phase output device 50 (claim 3) including a delay device 54 (claim 1) capable of outputting a plurality of optimum delay phases to the optical disk device 36 as described above and a peripheral circuit thereof. To do.

Instead of this, there is a delay device and a delay phase output device used in another embodiment of the magneto-optical disk device. This delay device of another aspect (claim 4) can be used in a magneto-optical disk device 66 as shown in FIG. Compared with the magneto-optical disk device 36 of FIG. 5, the magneto-optical disk device 66 (similar to the relationship between the conventional circuit examples (2) and (3)) has the PLL circuit 18 and the delay phase output device 50 of FIG. Voltage controlled oscillator (V
A delay phase output device 68 having a delay device 70 using CO) is provided.

In this delay phase output device 68, the delay device 70 using a voltage controlled oscillator (VCO) is
Delay device 54 of delay phase output device 50 of FIG.
"Laser rising", "Laser falling", and "Magnetic field timing" required for data recording
3 delay phases are generated. Similar to the magneto-optical disk device 36 of FIG. 5, the magnetic head drive pulse MHDP formed from the "magnetic field timing" delay phase is supplied to the pre-encoder 58, and the "laser rising" delay phase and the "laser falling" delay are supplied. The phase is supplied to the LDP forming circuit 56, forms a laser drive pulse LDP, and is supplied to the laser drive circuit 60.

The other parts are similar to those of the magneto-optical disk device 36 shown in FIG.

Therefore, according to the present invention, a VCO capable of outputting a plurality of delay phases most suitable for the above-mentioned optical disk device 66.
A delay phase output device 68 (claim 6) including a delay device 70 (claim 4) using the above and a peripheral circuit thereof is also provided.

[Delay Device According to the Present Invention] FIG. 7 is a diagram showing a circuit configuration of an embodiment of the delay device 54 according to the present invention, which is denoted by reference numeral 54 when viewed from the magneto-optical disk device 36 of FIG. It corresponds to the block. In addition, the technology is an improvement of the conventional circuit example (2) (FIG. 2),
The feature is that a plurality of selection circuits 10 are provided.

This delay device 54 comprises a plurality of (stages) delay elements DL1, DL2, DL indicated by a broken line frame.
3, ..., DL15, DL16, a phase comparator (PC) 12 as a phase matching means 8, a loop filter (LP)
F) 14 and voltage control unit (VC) 16 and, for example, three selection circuits (16 choices 1) 10, 10 ', 10 ". The number of selection circuits depends on the device used. The number of delay phases to be set is the same as that of the magneto-optical disk device 3
In the case of 6, there are three "laser rising", "laser falling", and "magnetic field timing".

(Delay Element) The delay device 54 is a device using the delay device,
For example, delay elements represented by n broken lines whose number (stage number) is determined based on the resolution t / n of the delay phase required by the magneto-optical disk device 36 (where t is the period of the input reference data clock). (DL) is a delay element array in which DL1, DL2, DL3, ..., DLn are connected in series from left to right in the figure.

For example, in FIG. 7, from the required performance of the magneto-optical disk device, for example, a phase resolution t / 16 of 1/16 of one cycle t of the data clock is required, and the delay element is D
Sixteen L1 to DL16 are provided.

The delay amount of each delay element DL is variable depending on the power supply voltage from the voltage control section 16, so that P
Reference data clock Dck from LL circuit 18 (FIG. 5)
1 in each stage of each delay element DL1 to DL16
Data clock d is sequentially delayed by 1/16 of cycle t.
It is output as 1 to d16 (= d0).

Specifically, as shown in FIG. 7, one delay element (eg, DL2) is an even number (eg, 2) of inverters having the same characteristics (eg, Inv21 and Iv21).
nv22). These inverters Inv
Is an electronic component whose delay time characteristic changes substantially linearly depending on the applied power supply voltage, and is preferably a MOS type IC, for example. First delay element DL of this delay element array
For 1, the reference data clock Dck is input.

One of the features of the present invention is that the output of the delay element DL in each stage has an inverter (for example, I
nv21 and Inv22 combination),
It can be mentioned that there is no difference in circuit configuration and the delay phase resolution t / n becomes uniform. In addition, the output of the delay element DL of each stage has the same duty ratio (H / t, that is,
Since it can be grasped as a pulse having a logic high level “1” and a period of 1 cycle), extra signal processing such as inserting an inverting element in every other output is unnecessary.

(Phase Matching Means) As shown in FIG. 7, the delay device 54 according to the present invention is different from the delay line 4 of the conventional circuit example (1) of FIG.
PLL when the column of L is a voltage controlled oscillator (VCO)
It has a phase matching means 8 utilizing the idea of (phase locked loop).

The data clock d0 (= Dck) at the first stage input and the data clock d16 at the last stage input are input to the phase comparator (PC) 12, and the phase comparator 12 compares the phases of these clocks. The phase error signal Error, which is proportional to the error, is supplied to the loop filter (LPF) 24. The loop filter 14 is mainly composed of a low-pass filter, converts the phase error Error into a DC voltage, and supplies the DC voltage to the voltage controller (VC) 16.

The voltage controller 16 mainly processes the delay element DL (combination of the inverters Inv) and controls the output voltage to the delay element DL so as to reduce the phase error Error to zero. This is supplied to each inverter Inv as a power supply voltage for delay time control. In this way, the delay time of each inverter Inv is controlled, and the first stage input clock d0 and the last stage output clock d1 are controlled.
6 always matches. As a result, it is possible to avoid the accumulation of changes in the delay amount due to performance changes due to environmental factors such as temperature when the phase matching means is not provided as in the conventional circuit example (1).

(Clock selecting means) Compared to the conventional circuit example (2) described in FIG. 2, the feature of the present invention lies in the clock means. That is, in order to obtain three kinds of predetermined delayed output data clocks Ddck, Ddck ', Ddck ", three selection circuits 10, 10', 10" are provided in parallel with the delay element array. ing. For example, there are a selection circuit 10 for "laser rise", a selection circuit 10 'for "laser fall", and a selection circuit 10 "for" magnetic field timing ".

Since the selection circuits 10 to 10 "are substantially the same and have the same multiplexer function, one of the selection circuits 10 will be mainly described. This" laser rising "selection circuit is described. 10, the data input clock d0 (= input data clock Dck) from the branch point n0 before the input end of the first-stage delay element DL1 changes to the branch point between the first-stage delay element DL1 and the second-stage delay element DL2. n
The data clock d1 is input from 1 and the data clock d2 is input from the branch point n2 between the second stage delay element DL2 and the third stage delay element DL3. By sequentially repeating the same circuit configuration, the data clock d15 is input from the branch point n15 between the 15th stage delay element DL15 and the final 16th stage delay element DL16. The selection circuit 10 '
Similarly, d0 to d15 are input for 10 "and 10".

The selection circuit 10 has a multiplexer function of selecting one specific clock from the plurality of delayed data clocks d0 to d15 in response to the 4-bit data clock selection signal Sel. The selection signal Sel is the result of the trial writing for the trial writing area near the inner circumference of the magneto-optical disk 38 (FIG. 5) and is stored in the CPU or
Is stored in the DSP and the "laser rising" selection signal Sel suitable for the disk 38 is set according to the result. By this selection signal Sel, a specific one is selected from the plurality of delayed data clocks d0 to d15, and is output as a predetermined delayed data clock Ddck that defines the "laser rise".

The selection circuit 10 'is the same as the selection circuit 10 except that the selection signal Sel' is input to determine the "laser fall" and the predetermined delayed data clock Ddck 'is output. .

The selection circuit 10 "is the same as the selection circuit 10 except that the selection signal Sel" is input to determine the "magnetic field timing" and the data clock Ddck "delayed by a predetermined value is output.

The above is the delay device 5 shown in FIG.
It is the contents of 4. Next, as an application example of the delay device 54, a delay phase output device 50 including a SEL setting circuit 52 and an LDP forming circuit 56 which are peripheral circuits will be described.

[Delayed Phase Output Device According to the Present Invention] The delayed phase output device 50 according to the present invention is an application example using the delay device 54 described above. As shown in FIG. 8, the delay phase output device 50 includes a delay device 54 and three registers 72, 7 in the preceding stage.
2 ', 72 "SEL setting circuit 52 and two FFs 74, 76 in the subsequent stage, for example, an LD having D-FF
And a P forming circuit 56. 2 FFs 74,7
The data input terminal D of 6 is clamped to the logic high level "1".

7, the reference data clock Dck and the selection signals Sel to Sel ″ are input to the delay device 54 from the PLL circuit 18 at the preceding stage. These selection signals Sel to Sel ″ are input. The SEL setting circuit from the host computer (not shown) or the dedicated DSP (digital signal processor (not shown)) described as storing the recording data Din in FIG. 5 through the CPU bus 78 or the like. Register 7 of 52
2 to 72 "and are respectively input to the delay device 54. Each time the selection signals Sel to Sel" are output to the delay device 40, the registers 72 to 7 are set.
A reset signal is supplied to the 2 ″ reset terminal R to reset the contents.

In the delay device 54, as described above, the delay element DL from the reference data clock Dck
Thus, 16 types of delayed data clocks d, which are sequentially delayed by 1/16 of one cycle, are generated. In contrast,
Selection signal Se for "laser rising" from register
A predetermined delayed data clock d is selected corresponding to l and is supplied to the clock input terminal Cp of the FF 76 as the delay phase Ddck of "laser rising".

Similarly, the delayed data clock Ddck 'is selected corresponding to the selection signal Sel' for "laser falling" from the register 72 ', and the "laser falling" delay is applied to the clock input terminal Cp of the FF74. Phase Dd
Supplied as ck '.

Similarly, a predetermined delayed data clock Ddck "is selected in response to the selection signal Sel" for "magnetic field timing" from the register 72 ", which is directly output to the pre-encoder 46 of FIG. Magnetic head drive pulse MHDP (= delay phase Ddc) of "magnetic field timing"
k ″).

"Laser rising" delay phase Ddck
The LDP forming circuit 56 which has received the delay phase Ddck ′ of “laser fall” and operates as follows. First, assuming that the output Q of the lower FF 76 is a logic low level "0",
This is supplied to the reset terminal / R of the upper FF 74, and the upper FF 74 is in the reset state. The upper / Q (inverted output of Q) is a logic high level "1", which is the lower F.
It is supplied to the reset terminal / R of the F76 and the lower FF76
Is not in reset. In this state, when the delay signal Ddck for "laser rising" is supplied to the clock terminal Cp of the lower FF 76, the output from the Q terminal becomes the logical high level "1" and the laser drive pulse LDP rises.

At this timing, a logic high level "1" is supplied to the reset terminal / R of the upper FF 74, and the upper F is reset.
The reset of F74 is released, and the state of waiting for the data clock Ddck 'for the "laser fall" signal is entered. When the "laser falling" signal data clock Ddck 'enters the clock terminal Cp of the upper FF 74, the output / Q becomes a logic low level "0" and is supplied to the reset terminal / R of the lower FF 76 to supply the lower FF. Is reset,
The laser drive signal LDP becomes the logic low level “0”.

At this timing, the upper FF 74 is reset again to prohibit the "laser falling" input Ddck '. As described above, the laser drive pulse LDP having the predetermined delay and the specific laser width set is formed and supplied to the laser drive circuit 60 (FIG. 5).

(Operation) FIG. 9 shows the output D of the PLL circuit 18.
ck (FIGS. 5 and 7), the data clocks d1 to d16 (=) output from the delay elements DL of the delay device 54.
Dck) (FIG. 7) and laser drive pulse LDP (FIG. 8). PLL circuit 18 of FIG.
From the reference data clock Dck (delayed phase output device 5
It is supplied to the first stage of the delay element array of the delay device 54 (in 0).

Next, as described with reference to FIG. 7, the data clocks d1 to d are sequentially delayed from each stage of the delay element array by t / n (t / 16 in the figure) with respect to Dck (= d0).
16 (= d0) is output. Here, the delay t / n is
Two stages of the inverter Inv, that is, "rising edge →
The amount of delay is "falling edge → rising edge".

In the example of FIG. 9, the laser drive pulse LDP
Determines (d0 to (t / 1
D2 which is delayed by 2 stages of 6) is used. In addition, for the determination of "laser fall" (from this d2 ((t / 1
D8 which is delayed by 6 stages in 6) is used.

To determine the "magnetic field timing" that cooperates with this, d2 or d3 is selected so that a saturation magnetic field is generated at the "laser fall" d8.

[Another Delay Device According to the Present Invention] FIG. 10 is a diagram showing a circuit configuration of an embodiment of another delay device 70 according to the present invention. From the entire magneto-optical disk device 66 of FIG. It corresponds to the delay device 70 in the block of reference numeral 68. The other delay device 70 is a technique improved from the conventional circuit example (3) and is characterized in that a plurality of selection circuits 24 to 24 ″ are provided.

The delay device 70 (improved from the conventional circuit example (3)) and the delay device 54 (improved from the conventional circuit example (2)) in FIG. 7 are different from each other in FIG. 4A.
Can be easily understood from the comparison between FIG. Note that FIG. 4A
And FIG. 4B show a conventional circuit example (2) and a conventional circuit example (3).
It is prepared for the purpose of comparison with FIG. 4A, and in the following description, in FIG. 4A (delay line 6 is the delay phase output device 50), (selection signal SEL is selection signal SE
L to SEL ″), (output Ddck to output Ddck to D
4B (reading the voltage-controlled oscillator Osc20 as the delay phase output device 70) and (selecting signal S
EL is a selection signal SEL to SEL ″), (output Ddck
Please read each as output Ddck to Ddck ").

As shown in FIG. 4A, the reference clock Ref clk reproduced from the clock pit is P in the broken line frame.
It is supplied to the series circuit of the LL circuit 18 and the delay phase output device 54. In this PLL circuit 18, a phase comparator (PC)
24, loop filter (LPF) 26, voltage control unit (V
C) 28 and oscillator (Osc) 30 are connected in series,
The output of the oscillator 30 is fed back to the phase comparator 24 via the frequency divider (1 / m) 32, and has a period of 1 / m of the period of the input reference clock Ref clk by a PLL (phase lock loop) action. The data clock Dck is generated.

The delay phase output device 54 to which the data clock Dck is supplied also has the PLL (phase adjusting means 8) therein as described with reference to FIG.

Therefore, the phase comparator (PC) 12 and the loop filter (LPF) 14 of the phase matching means 8 shown in FIG.
And the voltage controller (VC) 16 is the PLL circuit 1 of FIG. 4A.
8 phase comparator (PC) 24, loop filter (LP
F) 26 and voltage controller (VC) 28 are redundant.

Therefore, as shown in FIG. 4B, another delay phase output device 68 according to the present invention has a function having both the oscillator 30 and the delay phase output device 54 of FIG. 4A, thus avoiding the overlap of the PLL circuit. ing.

As shown in FIG. 4B, the reference clock Ref clk reproduced from the clock pit is P in the broken line frame.
It is supplied to the LL circuit 34. In this PLL circuit 34,
Phase comparator (PC) 24, loop filter (LPF) 2
6. The voltage control unit (VC) 28 and another delay phase output device 68 are connected in series, and the output of the delay phase output device 68 is fed back to the phase comparator 24 via the frequency divider (1 / m) 32. The PLL (Phase Lock Loop) function generates the data clock Dck having a cycle of 1 / m of the cycle of the input reference clock Ref clk.

That is, the delay phase output device 68 as a whole is supplied with a voltage (for controlling the delay amount of each delay element) from the voltage controller 28, and delayed by an arbitrary predetermined amount in accordance with the selection signals Sel to Sel ″. Data clocks Ddck to Dd
ck ″ are output respectively. This delay phase output device 68
It has a selection signal setting circuit 52, a delay device 70, and a laser drive pulse forming circuit 56. Next, the delay device 70 will be described.

As shown in FIG. 10, the specific circuit configuration of the delay device 70 comprises a ring oscillator 22 and three selection circuits (15 choices) 24, 24 ', 24 ".

(Ring Oscillator) Ring Oscillator 2
Reference numeral 2 forms a PLL by connecting a plurality of stages of delay elements in a ring shape, the number (stage number) of which is determined based on the resolution t / n required by a device using this, for example, a magneto-optical disk device 66. .

As the delay element, for example, an inverter In
and a plurality of inverters Inv1, which have the same performance.
Inv2, Inv3, Inv4, ..., Invn (n = 15 in the figure) are connected in a ring shape. The delay amount control voltage is supplied from the voltage control unit (VC) 28 (FIG. 4B) of the previous stage to each inverter Inv to control the delay amount of the inverter, and the output d15 of the final stage inverter Inv15 becomes the input d0 of the first stage inverter Inv1. To do so.

The ring oscillator 22 acts as a voltage controlled oscillator (VCO), and n must be an odd number to oscillate here. From each stage, clock cycle t
Of the phase delay clocks d1 to d15 (= d0) obtained by dividing the number of stages into n (the number of stages is 15 in FIG. 6). Since the total number n of the inverters Inv is an odd number, if the final stage output d15 is the first stage input d0, the input becomes an inverting input.

It should be noted here that the delay amount of the output d15 of the final stage inverter with respect to the input d0 of the first stage inverter is equivalent to 1/2 of the cycle t of the data clock Dck oscillated by the voltage controlled oscillator 22. (D0 and d15 in FIG. 13). However, it is possible to select a phase amount that is sequentially delayed from the outputs d1 to d15 (= d0) of each local delay element and is delayed by a maximum of one cycle t.
This is because, as will be described later, the selection method by the selection circuits 24, 24 ', 24 "is characteristic.

Further, one of the characteristics of the delay device 70 according to the present invention is that the delay device 54 (FIG. 7).
Similarly, the output of the delay element in each stage is the output from the inverter Inv having the same characteristics, and there is no difference in the circuit, and the delay phase resolution is uniform.

The final output D of this ring oscillator 22
ck (= d15) is a frequency divider (1 / m) 32 (FIG. 4B)
Also sent to.

Sequentially delayed data clocks d1, d2, d3, ..., D1 output from the inverter Inv of each stage.
3, d14, d15 (= d0) are respectively supplied to the selection circuits 24, 24 ', 24 "described below.

(Selecting Circuit) Compared to the conventional circuit example (3) described with reference to FIG. 2, the feature of the present invention lies in the clock selecting circuit. That is, the data clock Dd having three types of delay phases
ck to Ddck ″, three selection circuits 24,
24 'and 24 "are provided in parallel with the ring oscillator 22. For example, a selection circuit 24 for" laser rising ", a selection circuit 24'for" laser falling ", and" magnetic field timing ". For selection circuit 2
4 ″.

Since the selection circuits 24 to 24 "are substantially the same and have the same multiplexer function, one of the selection circuits 24 will be mainly described.

Selection circuit (15 choices) 24 shown in FIG.
As a result, one data clock selected corresponding to the “laser rising” selection signal Sel from the sequentially delayed data clocks d1 to d15 (= d0) from the inverter Inv of each stage is the phase delay clock Ddck. Is output as.

As the clock selection signal Sel, as described above, the delayed selection signal Sel optimal for "laser rising" is generated according to the result of the trial writing on the magneto-optical disk 66 (FIG. 6).

FIG. 11 shows the details of the selection circuit 24, and the selection method in the selection circuit 24 will be described using this.

The selection circuit 24 includes a decoder 78, a plurality of (15 in FIG. 10) AND gates 80, and one O gate.
It has an R gate 82. AND gate 1 for one inverter Inv (FIG. 10) of the ring oscillator 22.
Therefore, the number of AND gates is the same as the number n of inverters (15 in FIG. 10).

The data clock (eg, dn) output from the inverter Inv is supplied to one input terminal of the corresponding AND gate 80 (eg, nth AND gate).

The outputs from the decoder 78 are supplied to the other input ends of all the AND gates 80, respectively.

The selection signal Sel is supplied to the decoder 78, the output signal i of the decoder 78 is supplied with a logic high level "1" according to Table 1, and the other is supplied with a logic low level "0".

[0097]

TABLE 1 Selection 択信No. Sel output signal i 0000 i = 2 0001 i = 4 0010 i = 6 0011 i = 8 0100 i = 10 0101 i = 12 0110 i = 14 0111 i = 1 1000 i = 3 1001 i = 5 1010 i = 7 1011 i = 9 1100 i = 11 1101 i = 13 1111 i = 15 (that is, i = 0)

That is, in response to the monotonic increase of the selection signal Sel, the output i of the even-numbered columns 2, 4, ..., N−1, and the first 1, 3, 5 ,. The n-th output i is selected, and a logical high level “1” is applied only to the selected output.
Is output

The outputs of all the AND gates 80 are supplied to the OR gate 82, and thus the OR gate 82 outputs the predetermined delayed data clock Ddck corresponding to the selection signal Sel.

This output order is d2i (modulo
n). That is, the remainder obtained by dividing 2i by n is the output order. For example, in the third of fifteen,
(2 × 3) / 15 = 0 (quotient) ... 6 (remainder) and d6 is output, and (9 × 15) is (2 × 9) / 1.
5 = 1 (quotient) ... 3 (remainder) and d3 is output.

In the above embodiment, the order of the delay amounts is set to the clocks d2, d4, ..., D12, d14, d1, d3.
, D13, d15 (= d0) are described,
Since d15 and d0 match, the order of the delay amounts is set to clocks d0, d2 ,.
2, d14, d1, d3, ..., D13 are the same.

The selection circuit 24 'is "laser falling".
Is the same as the selection circuit 24, except that the selection signal Sel ′ is input to determine the output, and the predetermined delayed data clock Ddck ′ is selected and output.

[0103]

The selection circuit 24 "is the same as the selection circuit 24 except that the selection signal Sel" is input to determine the "magnetic field timing" and the predetermined delayed data clock Ddck "is selected and output. .

The above is the contents of the delay device 70 shown in FIG.

Next, as an application example of the delay device 70, a delay phase output device 68 including the SEL setting circuit 52 and the LDP forming circuit 54 which are the peripheral circuits thereof will be described.

[Delayed Phase Output Device According to the Present Invention] Another delayed phase output device 68 according to the present invention is the VCO described above.
It is an application example of the delay device 70 using. In addition, SE which is a peripheral circuit of the delay device 70
The L setting circuit 52 and the LDP forming circuit 54 are the same as the SEL setting circuit 52 and the LDP forming circuit 56 used in the delay phase output device 50 described in FIG. Therefore, only the essential points will be briefly described.

As shown in FIG. 12, the delay phase output device 6
4 is a delay device 70 using the VCO described above.
And the SEL setting circuit 52 of the three registers 72 to 72 ″ in the preceding stage and the LDP forming circuit 54 of the two FFs 74 and 76 in the subsequent stage. The data input terminals D of the two FFs 74 and 76. Is clamped to logic "1".

To the delay device 70 using the VCO, the delay amount control voltage of the delay element from the voltage control unit 28 at the preceding stage and the selection signals Sel to Sel ″ are input. These selection signals Sel to Sel. ″ Is a register 72 via a CPU bus 78 or the like from a host computer (not shown) or a dedicated DSP (not shown).
.About.72 ″ and input to the delay device 70, respectively.

In the delay device 70 using the VCO, the data clock d which is sequentially delayed by 1/16 of one cycle from the reference data clock Dck is generated and corresponds to the "laser rising" selection signal Sel from the register 72. The data clock Ddck is selected and supplied to the clock input terminal Cp of the FF76.

Similarly, the data clock Ddck 'corresponding to the "laser falling" selection signal Sel' from the register 72 'is selected and supplied to the clock input terminal Cp of the FF74. Similarly, the data clock Ddck ″ corresponding to the “magnetic field timing” selection signal Sel ″ from the register 72 ″ is selected, and the pre-encoder 58 of FIG. 6 is selected.
Is supplied to.

"Laser rising" delay phase Ddck
The LDP forming circuit 54 which has received the delay phase Ddck ′ of “laser fall” and operates as follows. First, it is assumed that the output Q (laser drive pulse LDP) of the lower FF 76 is at logic “0”. The upper FF 74 is in the reset state, the / Q is logic "1", and the lower FF 76 is not in the reset state. In this state, when the data clock Ddck of the delay phase is input to the clock terminal Cp of the lower FF 76, the output of the Q terminal is logic "1" and the laser drive pulse LDP rises.

At the same time, the reset of the FF 74 on the upper stage is released, and the FF 74 is in a state of waiting for the data clock Ddck '. Dd
When ck 'enters the clock terminal Cp of the upper FF 74, the output / Q becomes logic "0", the lower FF 76 is reset, and the output Q (laser drive signal LDP) falls to logic "0".

(Operation) FIG. 13 shows the reference clock Ref.
clk (FIG. 4B), output clocks d1 to d15 (= d of each delay element of the delay device 70 using the VCO).
0) (FIG. 10) and laser drive pulse LDP (FIG. 12). PLL circuit 3 of FIG. 4B
4 is supplied with the reference signal Ref clk, and the voltage control unit 2
8 and the data clock output Dck (= d0) of the delay device 70 (having the ring oscillator 22) are locked at 1 / m with respect to the reference signal Ref clk.

Next, t / n (in the figure,
The clocks d1 to d15 delayed by t / 15) are output. Here, the delay t / n is determined by the inverter Inv
This is the delay amount for one stage. The output order is as described in Table 1. Therefore, the output waveform is the selection signal Sel
The order is as follows, corresponding to the monotonic increase of.

1. No delay d0 (= d15) to t / 1
Clock delayed by 5 d2 2. Further, a clock d4 delayed by t / 15 3. Further, the clock d6 delayed by t / 15 4. Further, the clock d8 delayed by t / 15. Further, the clock d10 6.t delayed by t / 15. Further, the clock d12 delayed by t / 15 7. Further, the clock d14 8.t delayed by t / 15. Further, a clock d1 9.t delayed by t / 15. Further, the clock d3 10.t delayed by t / 15. Further, the clock d5 delayed by t / 15 11. Further, the clock d7 12.t delayed by t / 15. Further, the clock d9 13.t delayed by t / 15. Further, the clock d11 delayed by t / 15 14. Furthermore, the clock d13 15.t delayed by t / 15. Further, a clock d15 delayed by t / 15

The output of the clock d15 becomes the input d0 of the first-stage inverter Inv1, and since the total number of inverters is an odd number n, the phase of d15 is inverted.
The total delay amount of v1 to Inv15 is a half cycle (t / 2) of the data clock Dck.

However, by sequentially inverting the signals of the outputs d1 to d15 and setting the output order to the order of the even columns and then the odd columns, the sequential delay for one cycle (t) is performed. Data clock can be used.

In the example of FIG. 13, the laser drive pulse LDP is used.
Is from d0 to 2 × (t /
15) d4 delayed by only is used. Further, d8 delayed by 6 × (t / 15) from this d4 is used for the determination of “laser fall”.

To determine the "magnetic field timing" that cooperates with this, d2 or d4 is selected so that a saturation magnetic field is generated at the "laser fall" d8.

(Effects of Embodiment) According to the delay device of the present invention, an arbitrary phase clock can be obtained with a resolution of t / n (where t is a clock period and n is the number of delay element stages).

Further, according to the delay device of the present invention, the PLL is applied to the input clock to compensate the change in the delay amount due to the environmental factors such as the change in the temperature of the delay element. Does not occur.

Further, according to the delay device of the present invention, the sequentially delayed clocks can be taken out under the same condition, so that the delay phase resolution can be made uniform.

Further, according to the delay device according to the present invention, the delay phase amount at the final stage corresponds to one cycle, so that it can be used for an application of an apparatus which requires an arbitrary delay phase amount.

Further, according to the delay device using the VCO, substantially similar blocks are eliminated, and simplification and reduction of the circuit scale can be achieved.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention. The technical scope of the present invention is specified only by the description of the claims.

[0127]

According to the delay device of the present invention, a plurality of delay phases can be obtained. Further, according to the delay phase output device of the present invention, it is possible to obtain the laser drive pulse LDP and the magnetic head drive pulse MHDP suitable for the magneto-optical disk device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a conventional circuit example (1).

FIG. 2 is a diagram illustrating a conventional circuit example (2).

FIG. 3 is a diagram illustrating a conventional circuit example (3).

FIG. 4A is a diagram illustrating a conventional circuit example (2) and its peripheral circuits. FIG. 4B shows a conventional circuit example (3).
3A and 3B are diagrams illustrating a peripheral circuit and a peripheral circuit thereof.

FIG. 5 is a circuit configuration diagram of a related portion of a magneto-optical disk device in which the delay device and the delay phase output device according to the embodiment of the present invention are used.

FIG. 6 is a circuit configuration diagram of a related portion of a magneto-optical disk device in which a delay device according to another embodiment of the present invention is used.

FIG. 7 is a circuit configuration diagram of a delay device that is an embodiment of the present invention.

8 is a circuit configuration diagram of a delay phase output device which is an application example of the delay device in FIG.

9 is a diagram showing the timing of the embodiment shown in FIGS. 7 and 8. FIG.

FIG. 10 is a circuit configuration diagram of a delay device which is another embodiment of the present invention.

11 is a diagram showing details of the selection circuit shown in FIG. 10;

12 is a circuit configuration diagram of a delay phase output device which is an application example of the delay device in FIG.

FIG. 13 is a diagram showing the timing of the embodiment shown in FIGS.

[Explanation of symbols]

2, 10-10 ", 24-24" selection circuit 4, 6 delay line 8 Phase matching means 12, 24 Phase comparator (PC) 14,26 Loop filter (LPF) 16, 28 Voltage controller (VC) 18,34 PLL circuit 20, 30 Voltage controlled oscillator (Osc) 32 frequency divider (1 / m) 36,66 Magneto-optical disk device 38 magneto-optical disk 40 Spindle motor (M) 42 Optical head (H) 44 RF circuit 46 Playback signal processing circuit 50,68 Delayed phase output device 52 Selection signal setting circuit 54,70 delay device 56 Laser drive pulse forming circuit 58 pre-encoder 60 laser drive circuit 62 Magnetic head drive circuit 64 magnetic head 72-72 "register 74,76 flip-flops 78 CPU bus 80 AND circuit 82 OR circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 5/13 H01S 3/03 H03K 5/15 G11B 11/105 G11B 20/10 G11B 20/14 G11B 7 / 00

Claims (6)

(57) [Claims] 1. A plurality of stages of delay elements having a variable delay amount connected in series, and a phase adjusting means for controlling the delay amount so as to match the phases of a first stage input clock and a last stage output clock of the delay element. A delay device capable of outputting a plurality of delay phases, comprising a plurality of clock selection means for selectively extracting an output clock of the delay element in an arbitrary stage according to each input selection signal. 2. The delay device according to claim 1, wherein each of the delay elements has an even number of inverters having equal characteristics. 3. A delay phase output device comprising a selection signal setting circuit, a delay device and a laser drive pulse forming circuit, wherein the selection signal setting circuit temporarily sets each selection signal. The delay device includes a plurality of stages of delay elements connected in series, each of which has a variable delay amount, and controls the delay amount to input a first stage input clock and a final stage of the delay element. A plurality of delays are provided having a phase matching means for matching the phase with the output clock, and a plurality of clock selecting means for selectively extracting the output clock of the delay element of an arbitrary stage in response to each of the selection signals. It is possible to output a phase, and the laser drive pulse forming circuit outputs a delay phase clock that determines the laser rise and a delay phase clock that determines the laser fall. A delayed phase output device receiving and forming a laser drive signal. 4. A ring oscillator in which a delay amount is controlled according to an input voltage and an odd number of delay elements having an inverting function are connected in a ring shape, and a clock appearing at an output terminal of each delay element is input. And a plurality of clock selection circuits that selectively take out according to each selection signal.Each of the clock selection circuits corresponds to a monotonic increase of the selection signal, and first outputs to the output terminals of the even-numbered delay elements. A delay device capable of outputting a plurality of delay phases by the plurality of clock selection circuits in the order of appearing clocks and then in order of appearing clocks at output terminals of odd-numbered delay elements. 5. The delay device according to claim 4, wherein the delay element comprises an inverter. 6. A delay phase output device comprising a selection signal setting circuit, a delay device and a laser drive pulse forming circuit, wherein the selection signal setting circuit temporarily sets each selection signal. The delay device includes a ring oscillator in which a delay amount is controlled according to an input voltage and an odd number of delay elements having an inversion function are connected in a ring shape, A plurality of clock selection circuits for selectively extracting a clock appearing at the output terminal of the delay element according to each input selection signal, and each of the clock selection circuits is supplied to the clock selection circuit. Corresponding to the monotonic increase of the selection signal,
First, the clocks appearing at the output terminals of the even-numbered delay elements are output in the order of the clocks appearing at the output terminals of the odd-numbered delay elements, and thus the plurality of delay phases can be output by the plurality of clock selection circuits. A delay phase output device in which the laser drive pulse forming circuit forms a laser drive signal by receiving a delay phase clock that determines a "laser rise" and a delay phase clock that determines a "laser fall".