JP3473587B2 - In-vehicle communication device and road communication device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention transmits a communication signal for transmitting communication data using a synchronization signal, and processes subsequent communication data based on the synchronization signal included in the received communication signal. The in-vehicle communication device and the road communication device described above.

[0002]

In this type of communication method, for example, in order to send and receive signals in a synchronized state between the transmitting and receiving devices, a transmission signal is preceded by a synchronizing signal. I am trying. In this case,
In wireless communication, it is necessary to set the data length of the synchronization signal as long as possible in order to prevent adverse effects of external noise and ensure reliable communication. However, setting the data length of the synchronization signal to be long when performing communication requires extra communication time, which means that in an environment where communication time is limited as described below. There is a disadvantageous condition for the communication of.

In such a case, there is a case where communication is carried out between a communication device mounted on a vehicle such as an automobile and a communication device provided on a road in a communication area through which this vehicle passes when passing. . For example, at a tollgate such as an expressway, the vehicle side is equipped with an in-vehicle device that can process payment of tolls charged according to the traffic section and payment processing of the fee by wireless communication processing, and an antenna is provided on the road side. It is considered that wireless communication is automatically performed when an automobile travels. By constructing such a communication system, there is no need to stop the car at the tollgate, and it is expected that effects such as elimination of labor costs and man-hours for toll collection processing or congestion at the tollgate can be expected.

Therefore, under the above-mentioned environment, it is necessary that the communication for the fee collection processing is surely completed within a short time when the vehicle-mounted device of the automobile passes through the communication area of the antenna. Therefore, in order to solve the above-mentioned problems and surely achieve the communication processing, it is considered to perform the communication processing using a plurality of synchronization signals having different data lengths.

Therefore, the present inventor has assumed the following configuration as the identification form of the synchronization signal in such a case. FIG. 16 shows the configuration thereof. As two types of synchronization signals having different data lengths, UW1 (Unique) as a 32-bit (4 octet) first synchronization signal.
Word 1) and second 16-bit (2 octets)
UW2 (Unique Word)
2) is set as follows.

UW1 0111 1100 1101
The shift register 1 holds 32 bits of data, and is provided so as to sequentially shift when a digital signal is input as received data. The data of each bit of this shift register 1 is a 32-bit comparator 2.
Connected to each input terminal of. The comparator 2 is provided so as to output a detection signal when the input data is the same as the bit pattern of the synchronization signal UW1 described above. 16
The input terminal of the bit comparator 3 is the shift register 1
Is connected so as to receive the upper 16-bit data, and is provided so as to output the detection signal when the input data is the same as the bit pattern of the synchronization signal UW2 described above.

At the start of communication, a synchronization signal UW1 having a long data length is added to the beginning of the communication start signal and transmitted from a transmitter (not shown) in order to reliably obtain a synchronized state. In the receiving unit, when the transmission signal is received, the reception data demodulated into a digital signal is input to the shift register, and the first comparator 2 detects that the reception data includes the synchronization signal UW1. When,
New communication is started based on the synchronization signal UW1.

Further, when the synchronization is obtained in this way and the communication is started, the time for synchronizing the next transmission signal to be continuously transmitted in the transmitting unit when transmitting the subsequent data. The synchronization signal U is added at the beginning of the communication signal to shorten the
W2 is added and transmitted. When the receiving unit receives this transmission signal and detects that the received data includes the synchronization signal UW2, the above-described communication is continued based on the synchronization signal UW2.

In this way, the synchronization signal UW1 having a long data length (32 bits) is used to obtain the overall timing at the start of communication, and the short data length (16 bits) is used to obtain the timing of the subsequent transmission signal. By using the synchronization signal UW2 of, it becomes possible to perform communication while surely synchronizing in the limited communication time.
Communication efficiency can be improved.

By the way, when the circuit for obtaining the synchronization is formed as described above, each of the synchronization signals UW1 and UW2 has a configuration for identifying the synchronization signals having different data lengths.
Since it is necessary to provide comparators 2 and 3 for detecting the synchronization signal respectively, the number of bits required to configure the comparator increases, and the circuit is simplified in configuring the semiconductor integrated circuit. There are still technical issues to be solved such as space saving and space saving.

The present invention has been made in view of the above circumstances. An object of the present invention is to simplify the structure of a sync signal detection circuit when it is necessary to use a plurality of sync signals having different data lengths. An object of the present invention is to provide an on-vehicle communication device and a roadside communication device that can be realized.

[0012]

According to the invention of claim 1, when two or more kinds of synchronization signals used for communication signals are provided and the data lengths thereof are set differently, a synchronization signal having a long data length is used. Since the bit pattern is set to include the bit pattern of the sync signal with a shorter data length, the configuration for detecting the sync signal with a longer data length is in addition to the configuration for detecting a sync signal with a shorter data length. hand,
Since it is obtained by providing the configuration for detecting the remaining bit patterns, the configuration for detecting the synchronization signal of the vehicle-mounted communication device can be simplified, and space can be saved.

According to the second aspect of the present invention, by adding the identification bit pattern of a predetermined number of bits in association with the sync signal of the short data length differently from the bit pattern of the long data length, the subsequent reception Since it is possible to determine whether the data is the bit pattern of the sync signal having a long data length or the message bit pattern following the sync signal having a short data length at the time when the identification bit pattern is detected, the short data length When the synchronization signal is detected, it becomes possible to quickly perform communication processing thereafter, and this also contributes to prevention of erroneous determination due to noise or the like.

According to the third aspect of the invention, when a synchronization signal having a long data length is detected from the received communication signal, communication processing is started based on the synchronization signal, and a synchronization signal having a short data length is transmitted from the subsequent communication signal. When the signal is detected, the communication process is continued based on the synchronization signal. As a result, in the state where the communication is not started, the communication is started only when the synchronization signal having the long data length is detected, so that even if the synchronization signal having the short data length is detected, this is an erroneous detection due to noise. Alternatively, it can be determined that it is not a synchronization signal for itself. Further, in the state where the communication is started, the continuous communication data is accepted only when the short sync signal is detected, so that the operation of detecting the sync signal having the long data length can be suspended.

According to the fourth aspect of the invention, in the receiving section of the vehicle-mounted communication device, the first detection circuit detects the synchronization signal having the shortest data length, and the second detection circuit includes the synchronization signal. When the remaining bit pattern of the synchronization signal having a longer data length is detected, the corresponding synchronization signal having a longer data length than the synchronization signal having the shortest data length can be detected.

According to the invention of claim 5, in the roadside communication device for performing communication processing with the vehicle-mounted communication device, the synchronization signal used for the communication signal is 2 as in the case of the invention of claim 1.
When setting more than one type and setting their data lengths differently, since the bit pattern of the synchronization signal with the longer data length is set to include the bit pattern of the synchronization signal with the shorter data length, The configuration for detecting a synchronization signal with a long data length can be obtained by providing the configuration for detecting a remaining data bit pattern in addition to the configuration for detecting a synchronization signal with a short data length. The configuration for detection can be simplified, and space can be saved.

According to the invention of claim 6, similarly to the invention of claim 2, the identification bit pattern of a predetermined number of bits is set to be different from the bit pattern of long data length in association with the sync signal of short data length. By adding these, it becomes possible to quickly perform communication processing after detecting a sync signal with a short data length, and this also contributes to prevention of erroneous determination due to noise or the like. Become.

According to the seventh aspect of the present invention, the roadside communication device transmits a communication signal indicating that communication is newly started by using a synchronization signal having a long data length, and a communication signal that continues the communication is transmitted. Since the transmission is performed using the synchronization signal having the short data length, the synchronization can be surely established at the start of the communication, and the continuous communication can be quickly synchronized.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment in which the present invention is applied to a toll collection system for expressways will now be described with reference to FIG.
The description will be made with reference to FIGS. First, in FIG. 3 showing the overall appearance configuration, an expressway 11 (only one lane is shown) has three lanes 12, 13, and 14 on one side, and this road 11 is located at a predetermined toll collection point. Across the road (RSE; Road Side
A gantry 15 as an equipment is provided. This gantry 15 has the above lanes 12 to 14
Corresponding to, the antenna unit 16 which is a road communication device
To 18 are arranged downward, and communication areas 19 to 21 are set by each.

The communication areas 19 to 21 are respectively set in the directions in which a vehicle (for example, an automobile 22 in the drawing) approaches from each antenna unit 16 to 18. In this case, the antenna units 16 to 18 are provided with the antenna elements 23 to 25, respectively. Also,
The antenna units 16 to 18 are provided with a control circuit section on a base attached to the lower surface of the gantry 15 and antenna elements 23 to 25, and are entirely covered with a resin cover through which radio waves can be transmitted. It is considered as a structure.
The control circuit section is provided with an electrical configuration to be described later, whereby the antenna elements 23 to 25 are drive-controlled and a transmitting / receiving operation is performed.

The antenna elements 23 to 25 are constructed so that their radiation surfaces can be adjusted, whereby the communication area 1
The setting range of 9 to 21 can be adjusted. Although not shown, each antenna element 23 to
Reference numeral 25 is a microstrip type array antenna element formed by forming eight square patches on one surface side of the printed board, coupling these with a transmission line and connecting them to a feeding terminal.

Now, the automobiles 22 and 22 which are vehicles passing through the highway 11 are equipped with an on-vehicle device (OBE; On Boa) which is an on-vehicle communication device near the dashboard.
rdEquipment) 26, 26 is mounted. Each of the vehicle-mounted devices 26, 26 is provided with an antenna 27 for receiving and transmitting a communication signal with the antenna units 16-18 of the roadside device 15. This antenna 27
Is a microstrip type antenna in which two square patches are formed on a printed circuit board similar to those used for the antenna elements 23 to 25.

Next, the electrical structure will be described with reference to FIGS. 1 and 2.
Will be described with reference to. First, regarding the configuration of the antenna units 16 to 18 having the same configuration, the antenna unit 1
6 will be described as a representative. Figure 2 shows the overall structure.
The control circuit 28 of the antenna element 23 uses the other antenna element 2
It is connected to a control unit 31 that controls the control circuits 29 and 30 of 4, 25 together.
The control circuit 32, the power supply circuit 33, and the interface circuit 3 for exchanging data with the outside.
4 is included.

In the control circuit 28 provided corresponding to the antenna element 23, the modulation circuit 35 has a predetermined frequency f1.
The oscillation output given from the transmitting oscillator 36 is used as a carrier wave, which is modulated with a transmission signal given from the control circuit 32 and output to the antenna element 23 via the circulator 37.

Further, the receiving circuit 38 for performing signal processing such as demodulation is connected to the mixer 39, and the mixer 39 has a predetermined frequency f2 (for transmitting, set from the receiving oscillator 40 for receiving). The oscillation output of the frequency f1 is set to a value different from that of the frequency f1, and the circulator 3
A communication signal corresponding to the received signal is given from the antenna element 23 via 7. After the carrier wave and the radio signal corresponding to the received signal are combined by the mixer 39,
It is given to the receiving circuit 38. The receiving circuit 38 demodulates the given combined signal to obtain received data and outputs it to the control circuit 32.

Next, in the vehicle-mounted device 26, the control circuit 41
Is configured to include a CPU, a ROM, a RAM, an A / D converter, a D / A converter, a digital demodulation circuit, and the like. According to a communication program stored in advance, predetermined communication is performed as described later. The processing procedure is executed to communicate with the antenna units 16 to 18 of the road equipment.

The modulation circuit 42 controls the frequencies f1 and f2.
The oscillation output (frequency f2) for transmission given from the oscillator 43 which can be set between the two is used as a carrier wave to be modulated by the transmission signal given from the control circuit 41 and output to the antenna 27 via the circulator 44. It has become.

Further, the receiving circuit 4 which performs demodulation signal processing
Reference numeral 5 is connected to a mixer 46. The mixer 46 is supplied with an oscillation output f1 for reception given from an oscillator 43, and a reception signal is given from an antenna 27 via a circulator 44. . The carrier wave and the radio signal corresponding to the received signal are combined by the mixer 46 and then given to the receiving circuit 45. The receiving circuit 45 is adapted to perform analog demodulation of the given combined signal to obtain a received data signal and output this to the control circuit 41.

In the control circuit 41, the analog demodulated signal supplied from the receiving circuit 45 is digitally demodulated to obtain received data. In this case, for example, since the analog demodulated signal is digitally modulated by the Manchester encoding method or the like, the original received data is obtained by this digital demodulation. In addition,
The power source of the vehicle-mounted device 26 is supplied to each part by the battery 47, and the control circuit 41 stores or reads out data in the data memory 48 as needed and uses it.

Now, FIG. 1 shows an electrical configuration for detecting a synchronization signal from the received data obtained by digital demodulation in the digital demodulation section in the control circuit 41 described above, and the 32-bit shift register 49 is , Receive data is input, and bit data is sequentially shifted.

The first comparator 50 is a shift register 49.
The upper 16-bit data of the first sync signal UW1 (Unique Wor) having a data length of 32 bits (4 octets) is input as will be described later.
A detection signal is output when the bit pattern of the upper 16 bits of d 1) matches. The second comparator 51 is adapted to receive the lower 16-bit data of the shift register 49, and as described later,
The detection signal is output when the data length matches the bit pattern of the second synchronization signal UW2 of 16 bits (2 octets).

The first AND circuit 52 has a synchronizing signal UW1.
Of the first comparator 50 and the second comparator 51, the two input terminals of which are connected to the output terminals of the first comparator 50 and the second comparator 51. When the received data that matches the bit pattern of UW1 is input, the detection signal of the synchronization signal UW1 is output.

The second AND circuit 53 has a synchronizing signal UW2.
Of the second comparator 51 and one input terminal thereof is connected to the output terminal of the first comparator 50 through the inverter circuit 54 and the other input terminal thereof is connected to the second comparator 51.
Is connected to the output terminal of. And the second comparator 5
1 provides a high-level detection signal, that is, a signal in which a bit pattern of the synchronization signal UW2 is detected, and the first comparator 50 corresponds to a low-level detection signal, that is, the upper 16-bit bit pattern of the synchronization signal UW1. When the reception data is not obtained, the detection signal of the synchronization signal UW2 is output.

The reception start determination circuit 55 includes the first and second
AND circuits 52 and 53 for receiving the detection signals, and a control signal from the CPU 56 as well, which will be described later on the basis of the detection signals and the control signals of the synchronizing signal UW1 or UW2. In this way, a reception start determination signal is output to the data register 57.

The data register 57 is the shift register 4
Received data of 8 bits is input in parallel from a predetermined bit position of 9, and when a determination signal is given from the reception start determination circuit 55, data received after that is connected to the CPU 56. It is designed to output received data to the bus. And the CPU 56
Performs communication processing based on the received data captured at the timing obtained by the synchronization signal UW1 or UW2, and generates and outputs a transmission signal.

In the above structure, the first detection circuit in the present invention is the first and second comparators 50.
And 51, a second AND circuit 53, and an inverter circuit 54. The second detection circuit includes first and second comparators 50 and 51, and a first AND circuit 52.
It consists of and.

Next, the operation of this embodiment will be described with reference to FIGS. Prior to the description of this operation, the protocol of the data communication method used in this embodiment will be briefly described below.

That is, the data communication method applied in the present embodiment is a DSRC (Dedicated Short-Ran) provided for wireless bidirectional communication between a road unit and a vehicle unit within a limited communication area.
ge Communication) protocol is used. And, according to the regulation of this DSRC protocol, mainly automatic toll collection (ETC; Electric)
Toll Collection is described, but not limited to this, and commercial vehicle management (CV) will be provided in the future.
O; Commercial Vehicle Operator
cation) or various ITS (advanced transportation system; Intelligent)
It is applicable to the Transport System application.

Now, this DSRC protocol is based on ISO /
Although it complies with OSI (Open System Interconnection), it requires a simplified configuration to complete communication within a limited time, so the physical layer (L1), data link layer ( L2) and application layer (L2)
7) 3 layer structure, of which data link layer (L
2) is further processed by LLC (Logical Link Co).
control; logical link control) sublayer and MAC (Me)
A medium access control (medium access control) sublayer is divided into layers, and the application layer (L7) appropriately includes L3 to L6 defined by OSI.

The conditions and systems required for this data link layer are as follows. (1) Communication in a variety of communication areas is possible. Specifically, about 3 m (minimum communication area at toll gate)
To about 35 m (general communication area on the main line) with a single protocol. FIG. 5 shows three embodiments corresponding to such a condition.

FIG. 5A corresponds to a case where four lanes are covered by one antenna, for example, when a notice or wide area information is communicated. In this case, a passing vehicle can pass at a high speed. In consideration of this, the communication area is set up to a range of about 35 m. In FIG. 2B, a communication area of about 10 m is provided when three lanes are covered by one antenna. In the same figure (c), when four lanes are divided into separate lanes, one antenna is provided to set a communication area of about 4 m for each lane. It corresponds to the configuration of.

(2) Simultaneous communication with plural vehicles In order to enable simultaneous communication with plural vehicles, a time division multiple access method based on the slotted aloha method is adopted. In this case, a vehicle equipped with an in-vehicle device travels in a narrow communication area at a high speed (for example, a maximum speed of about 180 km / h when supporting multiple lanes and a maximum speed of about 80 km / h when dividing into one lane). Since it is premised that communication can be performed reliably, it is necessary to control the probability of communication collision between a plurality of vehicles to be extremely low.

(3) Large amount of information and high reliability of communication The amount of information of the ETC exit tollgate beacon communication is 4.1 kbit at maximum, and the CVO / bidirectional navigation general main line beacon communication The maximum amount of information is 31k bits. Also, in ETC, when the bit error rate (BER) on the wireless line is 1 × 10 −5,
Communication error rate of the entire communication system is 1 × 10 −6
Reliability shall be ensured as follows.

(4) Appropriateness for active communication system The downlink from the road device enables not only half-duplex communication but also full-duplex communication. The uplink from the vehicle-mounted device basically assumes half-duplex communication, and full-duplex communication is also possible.

In the present communication protocol provided to satisfy the above-mentioned conditions, the communication process is executed by the communication procedure described below. Here, the communication control procedure of the synchronous adaptive slotted aloha method suitable for bidirectional communication between a plurality of mobile on-board devices and roadside devices within a short time is used as a reference. And, basically, it is premised on half-duplex communication, but as adopted in the present embodiment, a communication control method capable of full-duplex communication using different frequencies for uplink and downlink is defined. There is.

FIG. 6 conceptually shows an example of a communication state that satisfies the above-mentioned conditions. For example, each of four vehicles is mounted in the communication area A of one road unit RSE. In-vehicle devices OBE-A, OBE-B, O
The case where BE-C and OBE-D perform bidirectional communication is shown. FIG. 7 describes the communication operation between the communication frame of the synchronous slotted aloha system in the full-duplex mode and the four vehicle-mounted devices OBE-A to D.

In this protocol, as shown in FIG. 8, one communication frame is used for FCMS, MDS, ACTS.
It is composed of three slots. In this case, FC
MS (Frame Control Message)
Slot) is because the on-road unit RSE controls communication.
It is a slot for performing frame synchronization, communication slot allocation, and the like for the vehicle-mounted device OBE, and is always located at the beginning of the frame. MDS (Message Data)
Slot) is a slot that is provided so as to be located following FCMS and that contains actual communication data. An acknowledgment for data transmission is also included in this slot, and MDC (MessageData Ch) that contains communication data.
ACK and ACKC (ACKnow)
led channel). And, ACTS (ACTivation Slot) is
This slot is used by the in-vehicle device OBE to make a communication registration request, and it always has a WCN (Wireless Call Num)
ber) -specifies ACTS followed by multiple ACs
TCs (ACTivation Channels) are continuously allocated, and this ACTS is the last slot of a frame.

The slots provided in the downlink are composed of FCMS and MDS, and the slots provided in the uplink are composed of MDS and ACTS. By repeating this frame a certain number of times, one transaction is completed.

Next, the communication procedure in the above case will be described. FIG. 7 shows that the MDS in the full-duplex communication mode is 4,
The figure shows the frame structure when the ACTS is 2, and the MDS is multiplexed by using transmission channels of different frequencies in the downlink and the uplink.

(0) First, the OBE detects the signal level of the FCMS constantly transmitted from the RSE, judges that it has entered the communication area A, and activates the OBE.

(1) The RSE informs the communication profile such as the frame structure by the FCMS.

(2) OBE determines the contents of FCMS,
The ACTC in the ACTS is randomly selected, a link address is added, and a link request signal is transmitted to the RSE to request an association.

(3) Next, the OBE sends data to the OBE on the downlink and receives the data from the OBE on the uplink according to the slot allocation of the FCMS. At this time, OBE and RSE return ACK in the same slot at the end of data transmission.

As described above, the four OBE-A to D
By assigning a slot to each of the RSE and the RSE, the communication is surely performed without collision.

Next, the structure of the above-mentioned full-duplex communication frame will be described in detail.

(1) FCMS (frame control message slot) As shown in FIG. 9, this is a non-field information SIG (Signal) such as the channel configuration of the physical medium layer of 1 octet.
ing), an identification number field FID (Fixed Equipment ID) of RSE of 1 octet, 1
Octet frame configuration information field FSI (Fr
ame Structure Information
n), a service application information field SC (Service Code) of RSE, and eight slot control fields SCI (S) for allocating communication slots.
lot control identifier). SCI is 1 as MDS allocation information.
Octet control information subfield CI (Contr
ol Information) and a 2-octet link address subfield IDN (ID Number).
r) and.

These signals include a 2-octet preamble signal PR (PRiamble), a 4-octet synchronization signal UW1 (Unique Word), and a 2-octet error check signal CRC (Cyclic Red).
(Undancy ErrorCheck) is added to the beginning, and guard times t0 and t2 are set before and after that,
The slot length is set to 100 octets as a whole.

Here, the unique word UW1 is set as a flag in a general communication system,
This is added in order to detect the beginning of the frame on the side of the vehicle-mounted device OBE that receives this and establish synchronization. For example, a bit pattern of 4 octets, that is, 32 bits is set as follows.

UW1 = 0111 1100 110
1 0010 0001 0101 1101 1000 That is, the upper 16 bits and the lower 16 bits of the UW1 bit pattern are set in the first comparator 50 and the second comparator 51.

(2) MDS (Message Data Slot) This is an MDC for data transmission, as shown in FIG.
(Message Data Channel) and A that notifies the sender whether the received signal was received correctly.
CKC (ACKnowledge Channel). Further, guard times t3 and t4 are set before and after the ACKC, and are set to a slot length of 100 octets as a whole.

Of these, the MDC is a 65-octet LPDU (Link Servi) as shown in FIG.
ce Data Unit) and 2-octet MAC
It is composed of a control field (MAC). LPDU
Indicates the LLC control field and the LSDU (Link Se
This is a LP that consists of
Data scrambling is applied to the DU and MAC control fields and CRC. And these signals include
2 octet preamble signal PR, 2 octet synchronization signal UW2, and 2 octet error check signal CR
C is added and transmitted at the physical medium layer.

Here, the unique word UW2 is added in order to detect the beginning of the slot on the side of the vehicle-mounted device OBE which receives it and establish synchronization. For example, the unique word UW2 has a bit pattern of 2 octets, that is, 16 bits. Set like.

UW2 = 0001 0101 1101 1000 As shown in FIG. 4, this UW2 is set to the same bit pattern as the above-mentioned lower 16-bit bit pattern of UW1. The bit pattern of UW2 is set in the second comparator 51.

ACKC (reception notification channel) is
One-octet reception notification information field AI (Acti
(Vation Information) only, a 2-octet preamble signal PR is added to this signal.
The 2-octet synchronization signal UW2 and the 2-octet error check signal CRC are added and transmitted on the physical medium layer. The synchronization signal UW2 used here
Is the same sync signal UW2 as used in the above MDC.

(3) WCN-ACTS, ACTS (Link Request Slot) The link request slot has a link request slot (ACTS) consisting only of the link request signal ACTC and a link request slot having a multiplex area of the identification code channel (WCNC). (WCN-ACTS). Further, one slot of the link request slot is composed of a plurality of ACTCs. Then, in the same manner as described above, the 2-octet preamble signal PR, the 2-octet synchronization signal UW2, and the 2-octet error check signal CRC are also added to these link request slots.

In the present embodiment, the antenna units 16 to 18 as the RSE are shown as an example corresponding to the configuration of FIG. 5C, and the communication protocol is as described above. The configuration shown in FIG. 5 (a) is also applicable.

In the antenna units 16-18,
Communication signals are transmitted to the communication areas 19 to 21, respectively. In this case, FCMS is transmitted at the beginning of the frame that constitutes each communication signal. As described above, the 32-bit sync signal UW1 which is a sync signal having a long data length is added to this FCMS. In addition, the communication signal transmitted when communication is performed in each slot assigned by this FCMS is a synchronization signal having a short data length.
A bit synchronization signal UW2 is added.

Now, when the vehicle equipped with the on-vehicle device 26 is passing through the lane 12 of the highway 11, the gantry 15
When approaching the communication area 19 of the antenna unit 16 when passing under, the communication signal transmitted from the antenna unit 16 is received. The in-vehicle device 26
The communication signal received by the antenna 27 is the circulator 4
When it is input to the mixer 46 via 4, it is combined with the oscillation output of the oscillator 43 and input to the receiving circuit 45.

The receiving circuit 45 analog-demodulates the received communication signal and outputs it to the control circuit 41. In the control circuit 41, a digital demodulation unit (not shown) demodulates the received data and sequentially outputs the received data to the shift register 49.

Since the synchronizing signal UW1 is added to the beginning of the received data as described above, when the synchronizing signal UW1 is input to the shift register 49, the first comparator 50 and the second comparator 50
Comparator 51 outputs the detection signal when the bit patterns match. This gives A
The output of the ND circuit 53 remains low level, and the AND circuit 52 outputs a high level detection signal.

As a result, the reception start judging circuit 55 judges that the synchronizing signal UW1 has been detected, and outputs a judgment signal to the data register 57 so that the CPU 56 side receives the subsequent received data. This information is also output to the CPU 56, and the CPU 56 processes the received data input via the data register 57 based on this information. Then, the communication signal modulated through the modulation circuit 42 to transmit the response signal corresponding to the timing of the slot designated by the FCMS obtained at this time is transmitted from the antenna 27.

If there is subsequent reception data in this frame, the reception data obtained at that timing is input to the CPU 56 by detecting the synchronization signal UW2 added to the beginning of the reception data in the same manner as described above. Like In this case, when the UW2 bit pattern is input to the shift register 49, the second comparator 51 outputs a high-level detection signal when the reception data of UW2 is input to the lower 16 bits. become. Further, at this time point, since the preamble data is input to the upper 16-bit portion of the shift register 49, the first comparator 50 is in a low level output state.

As a result, the AND circuit 52 is in the low level state, and the AND circuit 53 outputs the high level detection signal. That is, when the data of the synchronizing signal UW2 is input to the shift register 49, this can be detected immediately. Reception start determination circuit 5
Reference numeral 5 outputs a determination signal so that the data received by the data register 57 is received by the CPU 57 at the detection timing of the synchronizing signal UW2. Further, the CPU 57 receives the determination signal and then processes the subsequent received data.

When the series of communication processes is completed in this way, for example, billing process data such as a toll is stored in the data memory 48 of the vehicle-mounted device 26. Further, when traffic information or the like is obtained as data, it is displayed on a display device (not shown) or the like to notify the driver of the information.

According to the present embodiment as described above, in the communication process between the vehicle-mounted device 26 and the antenna units 16 to 18 which are the road devices under the conditions of the DSRC communication protocol,
The 16-bit bit pattern in the sync signal UW1 is the bit pattern of the sync signal UW2 with respect to the 32-bit sync signal UW1 set in the FCMS at the start of communication and the 16-bit sync signal UW2 set in the MDS that follows. Since it is set to be the same as the above, the configuration for identifying and detecting the synchronization signals UW1 and UW2 can be simplified, and space can be saved when configuring an integrated circuit. .

Further, since the bit pattern of the sync signal UW2 is made to match the bit pattern of the lower 16 bits of the sync signal UW1, when the sync signal UW2 is detected, the received data of 16 bits of the sync signal UW2 is received. Since it can be determined immediately when is input to the shift register 49, the communication processing can be rapidly advanced, and the vehicle-mounted device 26 and the antenna unit 1 can be processed.
It becomes possible to reliably carry out the necessary communication processing within a limited time between 6 and 18.

FIGS. 12 and 13 show the second embodiment of the present invention. The difference from the first embodiment is that the bit pattern of the synchronizing signal UW2 is set in the bit pattern of the synchronizing signal UW1. This is a bit pattern of a portion obtained by shifting the lower 16 bits by 2 bits to the upper side.

FIG. 13 shows a bit pattern of the synchronizing signal UW2 with respect to the synchronizing signal UW1.
Adopts the bit pattern up to the subsequent 30th bit, with the 15th bit from the beginning of the bit pattern of the synchronization signal UW1 as the first bit. Further, a code added subsequently to the synchronizing signal UW2 is provided as a 2-bit identification code. This identification code is "01",
Three patterns of "10" and "11" are provided so that they can be distinguished from the lower two bits "00" of the synchronization signal UW1.

Then, for example, while it is FCMS to add the synchronization signal UW1, the synchronization signal UW2 is M
Since it is added to the head of a plurality of slots such as DC, ACK, and ACT, in order to identify them, the synchronization signal U
When adding “01” to W2, MDC,
It is decided that it is an ACK slot when adding “10” and an ACT slot when adding “11”.

FIG. 12 shows a circuit configuration for determining these three identification codes together with the synchronization signals UW1 and UW2. The first comparator 58 compares 14-bit data, and the upper 14-bit data of the shift register 49 is input. Second comparator 5
Reference numeral 9 is for comparing 16-bit data, and the data in the upper 15th bit to the 30th bit of the shift register 49 is input.

The decoder 60 inputs the lower 2-bit data of the shift register 49 and outputs a high-level detection signal to the corresponding one of the four output terminals. The second comparator 59 is set to detect the bit pattern of the synchronizing signal UW2, and the first comparator 58 is set to detect the bit pattern of the upper 14 bits of the synchronizing signal UW1. ing.

The output terminal of the first comparator 58 is connected to the input terminal of the AND circuit 61, and the output terminal of the second comparator 59 is commonly connected to the input terminals of the AND circuits 61-64. Further, the output terminal of "00" of the decoder 60 is connected to the input terminal of the AND circuit 61, and "01", "1"
The output terminals of "0" and "11" are connected to the input terminals of the AND circuits 62, 63 and 64, respectively.

According to the above configuration, when the synchronizing signal UW1 is added to the received data, the first comparator 58,
The high level detection signal is output from the second comparator 59, and the high level detection signal is output from the decoder 60 to the output terminal of "00". As a result, the AND circuit 6
Only 1 will output a high level detection signal,
Therefore, the synchronization signal UW1 is detected.

When the synchronizing signal UW2 is added to the received data, the output of the decoder 60 differs depending on whether the subsequent 2-bit identification code is "01", "10" or "11". At this time, the first comparator 58
Becomes a low level output and the second comparator becomes a high level output, so that a high level detection signal is output from any of the AND circuits 62 to 64 according to the value of the identification code. As a result, the reception start determination circuit 55 makes a determination in a state where the identification code added to the synchronization signal UW2 is determined.

According to the second embodiment as described above, since the identification code is added to the synchronization signal UW2 to distinguish the slots, the identification code is determined even in the slots to which the same synchronization signal UW2 is added. Since the slot can be determined in advance, the processing of received data can be performed quickly, and erroneous determination due to noise or the like can be prevented as much as possible.

FIG. 14 shows the third embodiment of the present invention. The difference from the second embodiment is that the bit pattern of the synchronizing signal UW2 is the same as the bit pattern of the upper 16 bits of the synchronizing signal UW1. I have just set it. In this case, the first comparator 58 causes the lower 14 bits of the shift register 49 to be accompanied by setting the synchronization signal UW2 in this way.
The second comparator 59 is provided to compare the bit data, the second comparator 59 is provided to compare the upper 16 bits of the shift register 49, and the decoder 60 is provided to the upper 17th bit and the 18th bit of the shift register 49. It is provided to input the data of.

The second comparator 59 is set so as to detect the bit pattern of the synchronizing signal UW2 as described above, and the first comparator 58 sets the lower 14 bits of the synchronizing signal UW1.
It is set to detect a bit pattern of bits. Further, the same effects as those of the second embodiment can be obtained by the third embodiment as well.

FIG. 15 shows a fourth embodiment of the present invention. The difference from the first embodiment is that there are three synchronization signals U.
It has just been applied when W1, UW2 and UW3 are used. In this case, the synchronization signal UW1 is set with a data length of N1 bits, and the synchronization signal UW2 is set to N2 (<N
1) The bit length is set to the same bit pattern as that located near the center of the bit pattern of the synchronizing signal UW1. Further, the synchronization signal UW3 is N3 (<
N2) bit data length and upper N of the synchronization signal UW2
It is set to the same bit pattern as the 3-bit bit pattern.

The shift register 65 to which the received data is sequentially input is provided with one having N1 bits or more, and N1 bits of data at a predetermined position among them are provided from the upper side to the first comparator 66, the first comparator 66. The two comparators 67, the third comparator 68, and the fourth comparator 69 are distributed and input.

Of these, the second comparator 67 is provided so as to receive N3 bit data and detect the bit pattern of the synchronizing signal UW3. The third comparator 68 inputs (N2-N3) bits of data and receives the synchronization signal U
It is provided so as to detect the bit pattern of the lower (N2-N3) bits of W2. In addition, the first comparator 6
The sixth and fourth comparators 69 have a bit pattern of a predetermined number of bits on the upper side and the lower side of the synchronization signal UW1 (total (N1
-N2) bits) are respectively detected.

AND circuits 70, 71 and 72 are provided so as to output the detection signals of synchronizing signals UW1, UW2 and UW3, respectively, and the input terminal of AND circuit 70 is the output of four comparators 66-69. The input terminal of the AND circuit 71 is connected to the output terminals of the comparators 67 and 68 and the output terminals of the comparators 66 and 69 via the inverter circuits 73 and 74, respectively. The input terminal of the AND circuit 72 is the comparator 67.
Connected to the output terminal of the inverter circuit 75-
It is connected to the output terminals of the comparators 66, 68 and 69 via 77 respectively.

According to the above configuration, when the reception data includes the synchronization signals UW1 to UW3, the detection signals can be obtained from the AND circuits 70 to 72 corresponding to the respective synchronization signals UW1 to UW3. Even when the number of types of sync signals having different data lengths is increased in this way, the number of bits set in the comparator can be provided by the number of bits of the sync signal UW1 having the maximum data length.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. In addition to highways, it can be applied to general roads, parking lots, etc., and can also be applied to other ITS such as commercial vehicle management CVO or two-way navigation as another communication system using synchronization signals of different data lengths. . Furthermore, the present invention can be applied to other wireless communication systems and can be applied not only to wireless communication but also to wired communication.
In addition to the full-duplex communication method, the half-duplex communication method can be applied.

The number of synchronization signals may be four or more. Further, the data length can be set to any number of bits. The number of bits of the shift register is applicable as long as it is equal to or larger than the number of bits of the longest synchronization signal. The reception start determination circuit can be appropriately provided as needed. The data fetching bit position from the shift register of the data register can be appropriately set as required.

[Brief description of drawings]

FIG. 1 is an electrical configuration diagram of essential parts showing a first embodiment of the present invention.

FIG. 2 is an overall electrical configuration diagram

FIG. 3 is an external perspective view showing a positional relationship between a roadside device and a vehicle-mounted device.

FIG. 4 is an operation explanatory view illustrating a correspondence relationship between bit patterns of two synchronization signals.

FIG. 5 is a diagram showing a specific aspect of a required communication area.

FIG. 6 is a conceptual diagram showing a communication status of RSE communicating with a plurality of OBEs.

FIG. 7 is a diagram illustrating a slot configuration of a communication frame and a communication status with each OBE.

FIG. 8 is a diagram showing a basic configuration of a communication frame.

FIG. 9 is a diagram showing a data structure of FCMS.

FIG. 10 is a diagram showing a data structure of MDS.

FIG. 11 is a diagram showing a data structure of MDC.

FIG. 12 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 13 is a view corresponding to FIG.

FIG. 14 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

FIG. 15 is a view corresponding to FIG. 1 showing a fourth embodiment of the present invention.

16 is a view corresponding to FIG. 1 showing a conventional example.

[Explanation of symbols]

11 is a highway, 15 is a gantry (road machine), 16 to 18 are antenna units (road communication devices), 19-21 are communication areas, 22 is an automobile (vehicle), 23 to 25 are antenna elements, 26 is an in-vehicle device (in-vehicle communication device), 27 is an antenna, 28 to 30 are control circuits, 31 is a control unit, 32 is a control circuit, 41 is a control circuit, 49 is a shift register, 50 is the first comparator, 51 is the second comparator, 52 is the first AND circuit, 53 is the second AND circuit, 55 is a reception start determination circuit, 56 is a CPU, 57 is a data register, 58 is the first comparator, 59 is the second comparator, 60 is a decoder, 61 to 64 are AND circuits, 65 is a shift register, 66-69 comparator, Reference numerals 70 to 72 are AND circuits.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 7/08 H04B 7/26 H04J 3/06 H04L 7/00

Claims (7)

(57) [Claims] 1. An in-vehicle communication device, which is mounted on a vehicle and processes subsequent communication data based on a synchronization signal included in a communication signal received when passing through a predetermined communication area, wherein the synchronization signal Is configured so that at least two types having different data lengths are set, and the bit pattern of the synchronization signal having a longer data length is set to include the bit pattern of the synchronization signal having a shorter data length. In-vehicle communication device. 2. The synchronization signal, when an identification bit pattern of a predetermined number of bits is added to the synchronization signal of the short data length, the identification bit pattern of the position corresponding to the long data length. The vehicle-mounted communication device according to claim 1, wherein the bit pattern is set to be different from the bit pattern. 3. When the synchronization signal with the long data length is detected from the received communication signal, communication processing is started based on the synchronization signal, and when the synchronization signal with the short data length is detected from the communication signal that follows, the communication processing is started. The in-vehicle communication device according to claim 1, wherein the communication process is continued based on the synchronization signal. 4. The in-vehicle communication device includes a receiving unit that detects the synchronization signal, and the receiving unit detects the synchronization signal having the shortest data length among the synchronization signals so that the bit pattern of the comparison unit is detected. Of the bit pattern of the sync signal having a data length longer than the sync signal having the shortest data length when the sync signal having the shortest data length is detected by the first detection circuit. 4. A vehicle-mounted vehicle according to any one of claims 1 to 3, further comprising: a second detection circuit that compares a portion other than the bit pattern detected by the first detection circuit and detects a synchronization signal thereof. Communication device. 5. A roadside communication for transmitting communication data by using a synchronization signal as a communication signal and performing communication processing with an in-vehicle communication device mounted on a vehicle passing through a predetermined communication area. In the device, at least two types of sync signals having different data lengths are set, and the bit pattern of the sync signal having a longer data length is set so as to include the bit pattern of the sync signal having a shorter data length. An on-road communication device characterized in that 6. The synchronization signal, when an identification bit pattern of a predetermined number of bits is added to the synchronization signal of the short data length, the identification bit pattern is of a position corresponding to the long data length. The road communication device according to claim 5, wherein the bit pattern is set to be different from the bit pattern. 7. The roadside communication device transmits a communication signal indicating that communication is newly started using the synchronization signal having the long data length, and a communication signal continuing to the communication transmits the communication signal having the short data length. 7. The road communication device according to claim 5, wherein transmission is performed using a synchronization signal.