JP3472313B2 - Non-volatile storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile storage device for storing information by accumulating charges generated near a boundary between a channel region and a drain region. 2. Description of the Related Art Generally, a non-volatile memory device (hereinafter referred to as a non-volatile memory) which does not lose stored information even when power is turned off is provided with a non-volatile memory element for semi-permanently storing electric charge. (Hereinafter referred to as a non-volatile memory element)
A field effect transistor (hereinafter referred to as FET: field) having a SAMOS (stacked gate avalance injection MOS) structure
effect transistor). This S
FIG. 30 shows the basic configuration of an FET having an AMOS structure. An FET having a SAMOS structure is shown in FIG.
The source region 3 and the drain region 4 are formed on the silicon substrate 1 with the channel region 2 interposed therebetween, and the floating gate 5 is floating above the channel region 2.
And a control gate 6 are formed. In addition,
The floating gate 5 is surrounded by an insulating film (not shown). In the FET, predetermined voltages are applied to the source region 3 and the control gate 6, respectively.
Information is written by injecting hot electrons generated at the boundary between the drain region 4 and the channel region 2 into the floating gate 5. In recent years, with the development of the semiconductor industry, integration of a nonvolatile memory has been required. To meet this demand,
It is conceivable to improve the degree of integration of the memory cell circuit. Therefore, a nonvolatile memory as shown in FIGS. 31 and 32 has been proposed. FIG. 31 is an equivalent circuit diagram of the nonvolatile memory, and FIG. 32 is a perspective sectional view thereof. [0005] As shown in FIG.
FETs 10A, 10B, 10C, 10D, 1 having a transistor / 1 cell structure and having a SAMOS structure
Memory cells 11A, 11B, 11C, 11D, 11E, 11 having 0E, 10F, 10G, 10H, 10I
F, 11G, 11H, and 11I are arranged in a matrix with a predetermined capacity (9 bits in the figure). Then, the FETs 10A, 10B, 10C,
10D, 10E, 10F and 10G, 10H, 10I
Word lines WL1, WL2,
WL3 are connected to each other and the word line WL
FETs 10A, 10 adjacent to each other for WL1, WL2, WL3
B, 10C, 10D, 10E, 10F and 10G, 1
Sources and drains of 0H and 10I are connected. Further, bit lines BL1, BL2, BL3, and BL4 are respectively connected to the source and drain of the source-drain connection intermediate point and the FETs 10A, 10C, 10D, 10F and 10G, 10I at both ends. Further, in this nonvolatile memory, as shown in FIG. 32, one contact is shared by two memory cells,
Drain / source wiring is performed using the buried diffusion layer 12 that shares the source and drain regions of adjacent memory cells, that is, a virtual ground array is used to achieve high-density mounting. In the nonvolatile memory shown in FIGS. 31 and 32, since the FET having the SAMOS structure is used as the nonvolatile memory element, the floating gate is formed of an insulating film. , A region X (see FIG. 32) for separating the floating gate is required, and the size of the region X is usually determined by lithography technology. The movement of hot electrons between the boundary between the drain region and the channel region and between the floating gate and the floating gate depends on the ratio between the capacitance between the control gate and the floating gate and the capacitance between the floating gate and the source-drain. It is determined. Therefore, in order to improve the movement of hot electrons between the boundary between the drain region and the channel region and the floating gate and to drive the device at a low voltage, the capacitance between the control gate and the floating gate must be increased. I had to make the floating gate bigger to save money. Therefore, no matter how the lithography technology is used, there is a limit in reducing the size of the region X for separating the floating gate.
The reality was that further integration could not be achieved. An FET having a SAMOS structure is:
It has two gates, a floating gate and a control gate, which not only complicates the structure, but also requires two processes to form each gate, and also complicates the manufacturing process. In view of the above, an object of the present invention is to provide a non-volatile memory device that can achieve higher integration and that has a simple structure and can simplify a manufacturing process. [0011] The invention as set forth in claim 1 is as follows.
A channel region, a diffusion layer serving as a source region and a drain region with the channel region interposed therebetween are formed in the semiconductor substrate, a charge storage film for storing charges is formed on the channel region, and a gate electrode is formed on the charge storage film. A plurality of non-volatile storage elements are formed and are arranged in an array in which a plurality of nonvolatile storage elements for storing information by injecting and accumulating charges generated near a boundary between a channel region and a drain region into a charge accumulation film are arranged in an array. A word line is connected to the diffusion layer serving as the source region and the drain region, and a bit line is connected to the diffusion layer at right angles to the word line.
Is long along the above bit line,
Just above the diffusion layer, between the word line and the bit line, a selective oxide film that insulates between the word line and the bit line is formed by a LOCOS method. Are continuously formed over the channel regions of all the nonvolatile storage elements arranged in the array. According to the first aspect of the present invention, since charges can be stored in the charge storage film, it is only necessary to insulate between the word line and the bit line by the selective oxide film, which is conventionally required. The overlapping area between the floating gate and the control gate, which has occurred, can be eliminated, and the element can be miniaturized. Further, not only the structure becomes simple, but also one process is required to form the gate, so that the manufacturing process is simplified, and the manufacturing cost is reduced . A first embodiment of the present invention will now be described with reference to FIGS.
8 will be described in detail. In this embodiment, a nonvolatile memory element that stores electric charges semi-permanently (hereinafter, referred to as nonvolatile memory element) is an MNOS type field effect transistor (hereinafter, referred to as FET: field effect transistor). A non-volatile memory device (hereinafter, referred to as a non-volatile memory) using the memory will be described. The structure of the nonvolatile memory will be described with reference to FIGS. FIG. 1 is a plan view showing a part of a nonvolatile memory according to a first embodiment of the present invention, and FIG.
3 is a sectional view taken along line BB of FIG. 1, FIG. 4 is a sectional view taken along line CC of FIG. 1, and FIG. 5 is a sectional view taken along line DD of FIG.
As shown in FIG. 1, the non-volatile memory of this embodiment is an MNOSF
ET20A, 20B, 20C, 20D, 20E, 20
Memory cells 21A, 21B, 21C, 21D, 21 using F, 20G, 20H, 20I as nonvolatile memory elements
E, 21F, 21G, 21H, 21I are arranged in a matrix with a predetermined capacity (9 bits in the figure),
Each memory cell 21A, 21B, 21C, 21D, 21
As described later, word lines WL1, WL2, WL3 and bit lines BL1, BL2, BL3, BL4 are connected to E, 21F, 21G, 21H, and 21I in a manner orthogonal to each other. In the following description, MNOSFETs 20A, 20B, 20C, 20M
D, 20E, 20F, 20G, 20H and 20I are collectively referred to as "MNOSFET 20". MNOSFE as nonvolatile memory element
T20 is, as shown in FIG. 2 to FIG.
A P-well 31 is formed on an N-type silicon substrate 30 having a plane orientation (100) of about / cm.
Arsenic ions or the like are implanted, an N ⁺ -type diffusion layer 33 serving as a source region and a drain region is formed with the channel region 32 interposed therebetween, and a tunnel oxide film 34 made of silicon oxide is formed on the channel region 32. A charge storage film (hereinafter, referred to as a trap film) 35 made of silicon nitride for storing charges is formed thereon, and the trap film 3 is formed.
5, a gate electrode 36 made of polysilicon is formed. As shown in FIG. 2, the diffusion layer 33 serving as a source region and a drain region is formed on the bit line BL shown in FIG.
1, BL2, BL3, and BL4, the word lines WL1, WL2, WL3 and the bit lines BL1, BL3 are provided immediately above the diffusion layer 33, as shown in FIGS.
In order to insulate between BL2, BL3 and BL4, LOCOS (local
A selective oxide film (hereinafter, referred to as a LOCOS oxide film) 37 formed to be thicker than the tunnel oxide film 34 by an oxidation of silocon method is arranged so as to be connected to the tunnel oxide film 34. Then, the LOCOS oxide film 37
Is a bit line B, like the diffusion layer 33, as shown in FIG.
It is provided long along L1, BL2, BL3, and BL4. The trap film 35 is laminated not only on the tunnel oxide film 34 but also on the LOCOS oxide film 37 as shown in FIGS. 4 and 5, and as shown in FIG.
It is provided long along the bit lines BL1, BL2, BL3, BL4. The gate electrode 36 is, as shown in FIG.
Memory cells 21A, 21B, 21C, 21D, 2 along each word line WL1, WL2, WL3 shown in FIG.
Shared by 1E, 21F and 21G, 21H, 21I. As shown in FIGS. 3 and 5, elements between the MNOSFETs 20 are isolated by an isolation P ⁺ layer 38 formed by implanting boron ions or the like into the active region Y shown in FIG. The electrical configuration of the nonvolatile memory will be described with reference to FIG. FIG. 6 is an equivalent circuit diagram of the nonvolatile memory. As shown in FIG. 6, MNOSFETs 20A and 20A
B, 20C, 20D, 20E, 20F and 20G, 2
The word lines WL1, WL2,
WL3 are connected to each other and the word line WL
MNOSFET 20 adjacent to every 1, WL2, WL3
A, 20B, 20C, 20D, 20E, 20F and 2
The sources and drains of 0G, 20H, and 20I are connected. Also, the MNOSFETs 20A, 20C, 20D, 2
Bit lines BL1, BL2, BL3, and BL4 are connected to the sources and drains of OF and 20G, 20I, respectively. That is, as shown in FIGS. 4 to 6, the nonvolatile memory is a virtual ground array by sharing the source region and the drain region between adjacent MNOSFETs. Further, the writing, erasing, and reading operations of information in the nonvolatile memory will be described with reference to FIG. <Write> Consider a case where information is written to the memory cell 21E. The first voltage + V _pp (1) (for example, 9 V) is applied to the word line WL2 to which the memory cell 21E is connected.
V) to select the memory cell 21E,
A second voltage V _pp (2) (for example, 10 V) is applied to the bit line BL2 connected to the drain of the MNOSFET 20E in the memory cell 21E, and the MNOSFE
Bit line BL3 connected to the source of T20E
Is grounded to GND, hot electrons are injected and accumulated in the trap film according to the operation principle of the MNOSFET 20, which will be described later, and information is written to the memory cell 21E. [0022] In this case, grounding the word line W L 1, W L 3 of the memory cell 21E is not connected to GND,
When the bit lines BL1 and BL4 are opened,
No current flows to other memory cells, and no information is written. When writing information to the memory cell 21D, + V _pp (1) is applied to the word line WL2 and V _pp (2) is applied to the bit line BL1, respectively.
When the bit line BL2 is grounded to GND, the word lines WL1 and WL3 are grounded to GND, and the bit lines BL3 and BL4 are opened, the memory cell 2
Information is written to 1D. At the time of writing, the bit line which is in the open state becomes V _pp (2) or the GND level. _pp (2) may be applied or grounded to GND. That is, + V _pp (1) is applied to the gate of the MNOSFET in the selected cell, and V _pp (2) is applied to the drain, and the source and the well are G
Ground to ND, and connect all bit lines on the source side in the same memory matrix circuit to GND.
And the earth, the V _pp (2) to all of the bit line on the drain side
If so indicia pressurized, the writing speed increases. <Erasing> Erasing is performed by applying V
_pp (2) is applied to the word line by −V _pp (1) (for example, −6 V
When a third voltage is applied, holes are injected and accumulated in the trap film, as described later.
Information is erased. <Reading> A case where information stored in the memory cell 21E is read will be considered. The first voltage V _pp (1) (sense voltage) is applied to the word line WL2 to which the memory cell 21E is connected.
Is applied to the MNOSFET 20E in the memory cell 21E.
Bit line BL2 connected to the drain of
D, a second voltage V _pp (2) (for example, about 2 V) is applied to a bit line BL3 connected to the source of the MNOSFET 20E via a load (not shown), and another bit line BL3 is connected to the bit line BL3. Word lines WL1 and WL3 are connected to GND
And the bit lines BL1 and BL4 are opened. At this time, if information is written in the memory cell 21E, the MNOSFET 20E is turned off, and if no information is written in the memory cell 21E, the MNOSFET 20E is turned on. This MN
When the OSFET 20E is conductive or non-conductive, the bit line BL3
Of the bit line BL3, the information stored in the memory cell 21E is read. At this time, when V _pp (2) is applied to the bit line side used as the source at the time of writing and the bit line side used as the source at the time of writing is grounded to GND, MN
A large change in the threshold voltage _Vth of the OSFET 20 can be obtained, and reading can be stabilized. For the production how the non-volatile memory, 9 to 1
8 will be described in the order of steps. FIG. 9 is a plan view showing a state after the diffusion layer is formed, and FIG. 10 is a sectional view taken along line EE of FIG. FIG. 11 is a plan view showing a state after the LOCOS oxide film is formed, and FIG. 12 is a sectional view taken along line GG of FIG. FIG. 13 is a sectional view showing a state after the formation of the tunnel oxide film, the trap film and the gate electrode. 14 is a plan view showing a state after patterning of the gate electrode, FIG. 15 is a sectional view taken along line HH of FIG. 14, FIG. 16 is a sectional view taken along line II of FIG. 14, and FIG. is there. FIG. 18 is a sectional view showing a state after element isolation. In the steps of FIGS. 9 and 10, boron ions and the like are applied to the N-type silicon substrate 30 at 50 keV by 2 ×.
^Implant about 10 ¹³ cm ^-2 to form P on the silicon substrate 30.
A well 31 is formed. Then, a silicon oxide film 40 is grown on the P well 31 by, for example, about 50 nm by a thermal oxidation method, and furthermore, LPCVD (low pressure chemical vapor deposition).
A silicon nitride film 41 is deposited on the silicon oxide film 40 by, for example, about 150 nm by a por deposition method.
Thereafter, the silicon nitride film 41 is patterned into a stripe shape, and arsenic ions or the like are applied to the P well 31 at 100 keV and 5 × 1 using the silicon nitride film 41 as a mask.
By ^implanting about 0 ¹⁵ cm ^-2 , N wells serving as a source region and a drain region are sandwiched in the P well 31 with the channel region 32 interposed therebetween.
^{+ A} diffusion layer 33 is formed. In the steps of FIGS. 11 and 12, the silicon oxide film 40 immediately above the diffusion layer 33 is grown to a thickness of, for example, 600 nm by steam oxidation in a wet atmosphere, and the LOC is formed.
An OS oxide film 37 is formed. Then, the silicon nitride film 41 and the silicon oxide film 40 are removed by wet etching. In the wet etching, hot phosphoric acid is preferably used for the silicon nitride film 41 and hydrofluoric acid is preferably used for the silicon oxide film 40. In the step of FIG. 13, the surface of the P well 31 exposed in the steps of FIGS.
A tunnel oxide film 34 having a thickness of, for example, 10 nm is formed on the channel region 32 so as to be connected to the LOCOS oxide film 37. Next, a trap film 35 and a gate electrode 36 are formed by sequentially depositing, for example, 30 nm of silicon nitride and 400 nm of polysilicon, for example. It is preferable that the polysilicon be doped with phosphorus in order to reduce the resistance. In the steps of FIGS. 14 to 17, the gate electrode 36 is formed by the LOC formed in the steps of FIGS.
It is patterned in a stripe shape perpendicular to the OS oxide film 37. In the process of FIG. 18, FIGS.
Gate electrode 36 patterned in the step of
Using the OS oxide film 37 as a mask, the active region Y shown in FIG.
¹³ cm ^{-2 is} implanted to form an isolation P ⁺ layer 38, and element isolation is performed. Thereafter, although not shown, after depositing an interlayer insulating film, a contact hole is opened at a predetermined position from the periphery of the memory matrix, and a metal wiring such as Al-Si is formed. Next, the operating principle of the MNOSFET 20 will be described with reference to FIGS. FIG. 7 shows MNOSF
FIG. 8 is a diagram illustrating the operation principle of ET, and FIG. 8 is a diagram illustrating a change in the threshold voltage of the MNOSFET due to writing and erasing.
In FIG. 7, 33a is a source region, 33b denotes a drain region, taking the gate voltage V _G drain current I _D, the horizontal axis on the vertical axis in FIG. 8. At the time of writing, when a high voltage is applied to the gate electrode 36, as shown in FIG. 7, hot electrons are generated in the vicinity of the drain region 33b. Is injected and accumulated. Then, the MNOSFET 20 changes the threshold voltage V _th to the level shown in FIG.
Is shifted in the + direction as shown by T1 shown in FIG. On the other hand, when an electric field opposite to that at the time of writing is applied to the gate electrode 36 at the time of erasing, holes are generated in the vicinity of the drain region 33b.
Is injected and accumulated. Then, MNOSFET2
0 indicates that the threshold voltage V _th is −− like T2 shown in FIG.
Shift in the direction. [0033] At this time, since the fluctuation of the threshold voltage V _th is only the vicinity of the drain region 33b, the channel region
32 source region 33a near and in central part of, if the gate voltage V _G is an enhancement (enhancement) form no current flows at the time of 0V, is MNOSFET20,
Source even when the gate voltage V _G is 0V - a current path is formed between the drain, such as drain current flows,
A so-called depletion transistor
istor). As described above, in the nonvolatile memory element, the tunnel oxide film 34 is formed on the channel region 32, the trap film 35 is formed on the tunnel oxide film 34, and the gate electrode 36 is formed on the trap film 35. Has been
Even without a floating gate as in the related art, charges can be stored in the trap film 35. As described above, even if the floating gate is eliminated, the charge can be accumulated. Therefore, it is only necessary to insulate between the word line and the bit line by the LOCOS oxide film 37. The element can be miniaturized by eliminating the overlap region. Further, not only the structure becomes simple, but also one process is required to form the gate, so that the manufacturing process is simplified, and the manufacturing cost is reduced. Further, the LOCOS oxide film 37 is disposed immediately above the diffusion layer 33 serving as a source region and a drain region, so that the region of the diffusion layer 33 occupying one device can be reduced. To contribute. Further, by increasing the impurity concentration of the diffusion layer 33, charges are easily generated between the source and the drain, and even if the capacitance of the gate electrode 36 occupying the element is reduced, sufficient charges necessary for storing information are generated. Can be generated. Accordingly, the channel region 32 can be made smaller, which contributes to higher integration of the device. Next, a second embodiment of the present invention will be described in detail with reference to FIGS. The structure of the nonvolatile memory according to the present embodiment will be described with reference to FIG. FIG.
FIG. 4 is an enlarged sectional view of a main part of a nonvolatile memory according to a second embodiment of the present invention. As shown in FIG.
A first gate electrode 50 is formed on the trap film 35,
On the trap film 35, a second gate electrode 51 shared by each memory cell along the word line is formed.
Between the gate electrode 50 and the second gate electrode 51
Interlayer insulating film 5 2 made of silicon oxide is interposed. Other configurations are almost the same as those of the first embodiment. Regarding the method for manufacturing the nonvolatile memory,
The steps will be described in order with reference to FIGS. FIG. 20 is a plan view showing a state after the LOCOS oxide film is formed, and FIG. 21 is a sectional view taken along the line KK of FIG. FIG. 22 is a plan view showing a state after the formation of the trap film and the first gate electrode.
23 is a sectional view taken along line LL of FIG. 21, and FIG.
FIG. 25 is a sectional view taken along line M-N of FIG. 21. FIG.
6 and 27 are cross-sectional views showing the state after forming the diffusion layer.
26 is a sectional view taken along line LL of FIG. 21, and FIG.
It is M sectional drawing. FIG. 28 is a plan view showing the state after the formation of the interlayer insulating film and the second electrode, and FIG. 29 is a cross-sectional view taken along the line OO of FIG. In the steps of FIGS. 20 and 21, after a P-well 31 is formed on an N-type silicon
The S oxide film 37 is formed in an island shape. 22 to 25, a tunnel oxide film 34 and a trap film 35 are sequentially stacked on the entire surface, and then a first gate electrode 50 is formed between adjacent LOCOS oxides 37 for each column. In the steps of FIGS. 26 and 27, arsenic ions or the like are implanted into a predetermined active region of the P well 31 to form an N ⁺ -type diffusion layer 33 serving as a source region and a drain region with a channel region therebetween. In the step of FIG. 28 and 29, the entire surface is laminated interlayer insulating film 5 2, provided the contact hole on each of the first gate electrode 50. Then, the first gate electrode 50 is formed through the contact hole.
The second gate electrode 51 is formed in a stripe shape along the word line so as to be connected to the second gate electrode 51. The same operation and effect as in the first embodiment can be obtained in the above-mentioned nonvolatile memory. It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention. In the above embodiment, NO (ni
Although an example having a tride-oxide (tride-oxide) structure has been described, the ONO (oxide
-nitride-oxide). As is apparent from the above description, according to the present invention, charges can be stored in the charge storage film, so that only the word lines and the bit lines are insulated by the selective oxide film. In addition, the overlapping area between the floating gate and the control gate, which has been conventionally required, can be eliminated, and the element can be miniaturized. Further, not only the structure becomes simple, but also one process is required for forming the gate, so that the manufacturing process is simplified, and the manufacturing cost is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a part of a nonvolatile memory device according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along line AA of FIG. FIG. 3 is a sectional view taken along line BB of FIG. 1; FIG. 4 is a sectional view taken along the line CC of FIG. 1; FIG. 5 is a sectional view taken along line DD of FIG. 1; FIG. 6 is an equivalent circuit diagram of a nonvolatile memory device. FIG. 7 is an explanatory diagram of the operation principle of the nonvolatile memory element. FIG. 8 is a diagram showing a change in threshold voltage of a nonvolatile memory element due to writing and erasing. FIG. 9 is a plan view showing a state after a diffusion layer is formed. FIG. 10 is a sectional view taken along line EE of FIG. 9; FIG. 11 is a plan view showing a state after a selective oxide film is formed. FIG. 12 is a sectional view taken along line GG of FIG. 11; FIG. 13 is a cross-sectional view showing a state after forming a tunnel oxide film, a trap film, and a gate electrode. FIG. 14 is a plan view showing a state after gate electrode patterning. FIG. 15 is a sectional view taken along the line HH in FIG. 14; FIG. 16 is a sectional view taken along line II of FIG. 14; FIG. 17 is a sectional view taken along the line JJ of FIG. 14; FIG. 18 is a cross-sectional view showing a state after element isolation. FIG. 19 is an enlarged sectional view of a main part of a nonvolatile memory according to a second embodiment of the present invention. FIG. 20 is a plan view showing a state after a selective oxide film is formed. 21 is a sectional view taken along the line KK of FIG. FIG. 22 is a plan view showing a state after formation of a trap film and a first gate electrode. FIG. 23 is a sectional view taken along line LL of FIG. 22; FIG. 24 is a sectional view taken along line MM of FIG. 22; FIG. 25 is a sectional view taken along line NN of FIG. 22; FIG. 26 is a cross-sectional view taken along line LL of FIG. 22 showing a state after formation of a diffusion layer. FIG. 27 is a cross-sectional view taken along the line MM of FIG. 22 showing a state after formation of a diffusion layer. FIG. 28 is a plan view showing a state after formation of an interlayer insulating film and a second electrode. FIG. 29 is a cross-sectional view taken along the line OO of FIG. 28 showing a state after element isolation. FIG. 30 is a diagram showing a basic configuration of a conventional nonvolatile memory element. 31 is an equivalent circuit diagram of a nonvolatile memory device using the nonvolatile memory element of FIG. 30. FIG. 32 is a perspective sectional view of the same. [Description of Signs] 20, 20A, 20B, 20C, 20D, 20E, 20
F, 20G, 20H, 20I MNOSFET 30 Silicon substrate 32 Channel region 33 Diffusion layer 33a Source region 33b Drain region 34 Tunnel oxide film 35 Trap film 36 Gate electrode 37 LOCOS oxide film 50 First gate electrode 51 Second gate electrode

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-64-74761 (JP, A)                 JP-A-1-179414 (JP, A)                 JP-A-58-84460 (JP, A)                 JP-A-58-223370 (JP, A)                 JP-A-48-60881 (JP, A)                 Actual opening 58-94199 (JP, U)

Claims (1)

(57) Claims 1. A charge is formed in a semiconductor substrate, wherein a channel region and a diffusion layer serving as a source region and a drain region are formed with the channel region interposed therebetween, and charges are accumulated on the channel region. A storage film is formed, a gate electrode is formed on the charge storage film, and a nonvolatile storage element that stores information by injecting and storing charge generated near a boundary between a channel region and a drain region in the charge storage film is: A plurality of arrays are arranged in an array, a word line is connected to the gate electrode, and a bit line is connected to the diffusion layer serving as the source region and the drain region in a form orthogonal to the word line . Long along the above bit line
Have been, a straight upper portion of the diffusion layer, is between the word line and the <br/> bit lines, forming selection acid <br/> of film for insulating between the both by LOCOS method Wherein the charge storage film is formed continuously over the channel regions of all the nonvolatile memory elements arranged in the array.