JP3471733B2 - Synchronous acquisition method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization acquisition method and apparatus for synchronizing a spread spectrum code generated by a spread code with a spread code generated on the receiving side, and a code sequence having a predetermined code pattern. The present invention relates to a synchronization acquisition method and apparatus for synchronizing a received signal that has been inserted into a target and a same code string generated on the receiving side.

[0002]

2. Description of the Related Art In a direct spread spectrum spread communication (DS-SS) receiver used in mobile communication, etc., a received signal spread by a spread code and a spread code generated on the receiving side are used. Must be synchronized (synchronization acquisition).
FIG. 10 shows a direct sequence spread spectrum communication system (DS-S
It is a block diagram which shows the 1st example of the conventional acquisition device in S). 1 is the Matched Filter
er), and takes the correlation with the spread spectrum received signal. The matched filter 1 uses the same spreading code as the spreading code on the transmitting side as the tap coefficient. As the tap coefficient, a code of +1 or -1 is usually used corresponding to 1,0 of the spread code. Reference numeral 41 is a maximum value selection and threshold comparison unit. The received spread spectrum signal r (t) is obtained by orthogonally demodulating the received digital modulation signal, frequency-converted into a baseband band, and passed through a bandpass filter. Normally, the IQ component with reference to the carrier phase is used. It is input to the matched filter 1 as an output.

FIG. 11 is a first explanatory diagram of the synchronization acquisition method in the prior art shown in FIG. The length (the number of taps) of the matched filter 1 is equal to the spread code period. A binary PN (Pseudo Noise) code is used as the spreading code, and the transmission signal is modulated with the PN code, for example, BP.
It is SK modulated. The output of the matched filter 1 is the received spread spectrum signal over one cycle of the spread code.
The correlation value between r (t) and the PN code is output to the maximum value selection / threshold comparison unit 41 for each chip cycle or for each cycle in which the chip cycle is oversampled.

The maximum value selecting / threshold comparing section 41 observes the correlation value output from the matched filter 1 and extracts the code phase offset timing having the maximum value from the observed correlation values. When the maximum value exceeds the predetermined threshold value, the offset timing is determined to be the synchronization point, and a signal indicating synchronization acquisition is output. When the above-mentioned threshold is not exceeded, the correlation value output from the matched filter 1 is observed again for the time of one cycle of the spreading code.
Repeat that.

In the fading environment, if the threshold value is fixed in advance, it is impossible to cope with the fluctuation of the received power level. Therefore, if the adaptive control threshold during operation, as an example, an average value of the output of the matched filter 1 during the observation period, there is a method of the gamma ₁ multiplied by the coefficient gamma ₀ on the average value with a threshold. However, the optimum value of γ ₀ is determined in advance by simulation. Alternatively, a matched filter that uses a code orthogonal to the spreading code as a coefficient is prepared separately, and the coefficient γ ₂ is added to the average value of its output.
There is a method in which γ ₃ multiplied by is used as a threshold value. In this case as well, γ ₂ is fixedly set in advance. In addition, the output of the matched filter 1 may be subjected to synchronous addition (also referred to as in-phase addition or ensemble averaging operation) with the cycle of the spreading code as one unit over a plurality of cycles of the spreading code. Since the time averaging process of the correlation value is performed, the influence of the correlation value due to fading distortion or noise is reduced, and the SN ratio is improved.

In the synchronization acquisition mode, when the threshold value is exceeded, the next confirmation mode is entered, and when the threshold value is not exceeded, the synchronization acquisition mode is restarted. In the confirmation mode, a sliding correlator multiplies the received spread spectrum signal and the spread code on the receiver side at the synchronization timing determined in the capture mode and integrates them to obtain a correlation output. The integration time is set to one to several cycles if the spreading code is a short code, and to a predetermined fraction of one cycle if the spreading code is a long code. This correlation detection is repeated multiple times. If the number of times the correlation value exceeds a certain threshold value is a predetermined number of times or more, it is determined that the synchronization point is correct, and the normal reception operation mode (operation mode) is entered. If not, start over from capture mode. The threshold value in this confirmation mode is also variable according to the power level of the received signal.

FIG. 12 is a second explanatory diagram of the synchronization acquisition method in the prior art shown in FIG. The example shown in the figure shows a synchronization acquisition method suitable when the length of the matched filter 1 is shorter than the cycle of the spread code. In this case, a part of the spread code is used as the coefficient of the matched filter 1. In the illustrated example, the code having the number of chips corresponding to the length of the matched filter is taken out from the rear part of the spread code, but the coded place may be taken anywhere. Even in this case, as in the synchronization acquisition method shown in FIG. 11, synchronization is achieved by observing the output of the matched filter 1 for one cycle of the spread code, with the chip cycle or the cycle of oversampling as a unit. Capturing can be done.

FIG. 13 is a block diagram showing a second example of a synchronization acquisition device using a conventional matched filter in direct sequence spread spectrum communication (DS-SS). In the figure,
21 _{0 to} 21 _J-1 are a plurality of matched filters,
The received spread spectrum signal r (t), which has been spread spectrum by the spread code, is commonly input, and correlation detection is performed in parallel. Reference numeral 51 is a maximum value selection and threshold comparison unit. In this conventional technique, a plurality of matched filters 21 _{0 are used.}
This is a method of selecting the maximum value from ~ 21 _J-1 and is suitable for detecting the correlation with the spreading code of the long code, and can reduce the synchronization acquisition time to 1 / J (1 / J).

FIG. 14 is a second explanatory diagram of the synchronization acquisition method in the prior art shown in FIG. The spread code is equally divided into the number corresponding to the number (J) of the matched filters 21 _{0 to} 21 _J-1 . Each of the J divided spread codes equally divided is used as a coefficient of the matched filters 21 _{0 to} 21 _J-1 . At this time, a further part of each divided spreading code may be taken out in the same length with the same length and used as the coefficients of the matched filters 21 _{0 to} 21 _J-1 . 21 _0-21 length of _J-1 of each matched filter, even shorter. FIG. 14 shows a case where the lengths of the matched filters 21 _{0 to} 21 _J-1 are shorter than the division spread code.

In the case of this synchronization acquisition method, the outputs of all the matched filters 21 _{0 to} 21 _J-1 are observed over a time period of 1 / J of the spread code period, or for each chip period or each period in which the chip period is oversampled. And from that,
The matched filter with the maximum value and its offset timing are extracted. And if it exceeds the threshold,
The divided spreading code corresponding to the matched filter having the maximum value determines that there is a synchronization point at the offset timing of the matched filter having the maximum correlation value, and outputs a signal indicating synchronization acquisition. In the illustrated example, the maximum value is detected in the output of the matched filter 21 ₁ and exceeds the threshold value. Note that synchronous addition can also be performed. For example, all outputs of the matched filter 21 ₀ over a time period of 1 / J of the spread code period are stored in a memory,
At the time of 1 / J of the next spreading code period, the output of the next matched filter 21 ₁ is synchronously added to the value stored in the above-mentioned memory in consideration of the advance of the received signal. At the time of 1 / J of the next spreading code period, the target of the synchronous addition is the output of the next matched filter 21 ₂ .

In a communication system such as mobile communication,
In addition to the above-described synchronization acquisition of the spread spectrum code, there is a method in which a code string having a predetermined code pattern is periodically inserted and transmitted at a predetermined time period (frame period).
That is, a known pattern used for initial synchronization acquisition and channel estimation (propagation path estimation) during communication is periodically inserted as a preamble. Even when the code sequence having such a predetermined code pattern is synchronously captured, the above-described code synchronous capture technique can be applied. The code string having the above-described predetermined code pattern is not necessarily the PN code.

FIG. 15 is an explanatory diagram showing a conventional synchronization acquisition method using a matched filter in a communication system in which preambles are periodically inserted. In this case, in order to detect the above-mentioned known code pattern and acquire frame synchronization, the same configuration as that of the spreading code shown in FIG. 10 can be used. In that case, a code string having a predetermined code pattern may be used as the coefficient of the matched filter 1 in FIG. The illustrated example is an example in which a code string having a predetermined code pattern is a preamble, and a frame synchronization is acquired using a matched filter having the code string of the preamble as a coefficient.

In any of the above-mentioned conventional techniques,
By setting a threshold for the level of the correlation value, the maximum value exceeding the threshold is set.
It is determined that there is a synchronization point at the offset timing to be taken.
It Since this threshold follows the fading environment,
Mean value of matched filter output at
Then, calculate the average value of the power level by the coefficient γ₀Doubled γ₁Ai
Is a matched filter whose coefficient is a code orthogonal to the spreading code.
The average value of the output of ₂Doubled γ₃, Refer to the threshold
Had decided. However, the coefficient γ₀, Γ₂Is
The value must be determined by simulation and fixed.
Yes. However, the coefficient γ₀, Γ₂Is the signal-to-noise ratio at that time
(SNR) changes the optimum value. Therefore, improve performance
To obtain the coefficient γ depending on the signal-to-noise ratio at that time,₀, Γ₂
It is better to change. However, the estimation of the signal-to-noise ratio
In order to do so, you must first be able to acquire synchronization
And this is impossible. Therefore, the coefficient γ₀, Γ₂Is
Relatively characteristic over the expected signal-to-noise ratio
The compromise is to choose the best one. for that reason
Even if the threshold is set, the offset timing detection is
There is a problem of weak sound.

If the threshold value is exceeded in the synchronization acquisition mode, the next confirmation mode is entered. If the threshold value is not exceeded, the synchronization acquisition mode is restarted. If the threshold value is set too low, the next synchronization mode is transitioned to the next confirmation mode, the synchronization point is found to be incorrect, and the synchronization acquisition mode is restarted. Therefore, the overall synchronization acquisition time becomes long. On the contrary, if the threshold value is set too high, if the number of times of reacquisition of the synchronization reaches the limit, the maximum value at that time is output as the synchronization point even if the number of times of the synchronization acquisition has reached the limit. That is, it is the same as when no threshold is provided. The maximum value at this time is not necessarily guaranteed to be the correct synchronization point. If it is not correct, as in the case described above, the mode is shifted to the confirmation mode and the synchronization acquisition mode is restarted.

As described above, in the prior art, it was necessary to set the threshold value for the output level of the correlation value in order to detect the maximum value. However, in practice, it is difficult to set this threshold optimally, so that the probability of erroneous synchronization acquisition is high due to noise or the like. On the other hand, the above-mentioned synchronous addition is effective as a measure for substantially lowering the signal-to-noise ratio.
When the synchronous addition is performed over a plurality of cycles, the peak waveform of the maximum value becomes steep. However, if the synchronous addition is continued for too long, the synchronous acquisition time becomes long. Then, not only it takes time to enter the operation mode, but also the propagation environment changes in mobile communication. That is, the optimum multipath path changes or the optimum base station changes. In such a situation, not only the data that has been synchronously added until then is wasted, but it is rather harmful to the new environment.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problems, and has a high accuracy of synchronously capturing a spread spectrum code or a code string having a predetermined code pattern. An object of the present invention is to provide a synchronization acquisition method and device that can reduce the time required for acquisition.

[0017]

[0018]

[0019]

According to a first aspect of the present invention, in the synchronization acquisition method, some or all of the divided spread codes obtained by dividing the spread code into J and the spread code. Correlation detection with the received signal spectrum-spread by is repeated over a period that is a multiple of a division period of 1 / J of the period of the spread code, and the divided spread code that gives the maximum correlation value in each divided period. Part or all of the code and offset timing are detected, part or all of the code of the divided spreading code that gives the maximum correlation value changes with the progress of the received signal, and the offset timing is It is determined that there is a synchronization point when they match twice consecutively. Therefore, the synchronization acquisition of the spread spectrum code can be performed with high accuracy by using the information in the time axis direction of the correlation output that has less fluctuation than the level fluctuation of the correlation output. As a result, it is possible to shorten the time required for the synchronization acquisition of the spread code. Since the code for synchronization detection is divided, the code length for correlation detection is reduced. As a result, the number of taps of the matched filter used for correlation detection can be reduced, and the processing load and circuit scale can be reduced.

According to a second aspect of the present invention, in the synchronization acquisition method, some or all of the divided spread codes obtained by dividing the spread code into J and the spread spectrum received by the spread code. Correlation detection with a signal is performed in parallel, and the supply of a plurality of correlation values by the correlation detection is changed to the next order each time a division period of 1 / J of the period of the spread code elapses. By performing a plurality of synchronous additions that are received while being switched, the synchronous additions are executed over a period that is a multiple of a division period of 1 / J of the spread code period, and the synchronous additions are repeated. Detecting a part or all of the code and the offset timing of the divided spread code that gives the maximum correlation value, and a part or all of the divided spread code that gives the maximum correlation value. No. is changed with the progress of the received signal, and, when a match of the offset timing is a predetermined number, it is to determine that there is a synchronization point.
Therefore, the synchronization acquisition of the spread spectrum code can be performed with high accuracy by using the information in the time axis direction of the correlation output that has less fluctuation than the level fluctuation of the correlation output. As a result, it is possible to shorten the time required for the synchronization acquisition of the spread code. Since the code for synchronization detection is divided, the code length for correlation detection is reduced. Therefore, the processing load and the circuit scale are reduced. Since the signal-to-noise ratio is improved by the synchronous addition, the synchronous acquisition can be performed with higher accuracy.

[0021]

[0022]

[0023]

[0024]

In a third aspect of the present invention, a synchronization having a plurality of correlation detectors for inputting a received signal spectrum-spread by a spread code and a determiner for receiving the outputs of the plurality of correlation detectors as inputs. In the capturing device, each of the correlation detectors is set with a code of a part or all of a spread spectrum code obtained by dividing the spread spectrum code into J, and one of the received signal and each of the spread spectrum codes is set. Correlation detection with a part or all codes is performed by 1 / J of the cycle of the spreading code.
Repeated over a plurality of cycles of the division cycle, the determiner compares the correlation values of the correlation detectors in each of the division cycles, and a part or all of the division spread code that gives the maximum correlation value. Of the divided spread code that gives the maximum correlation value, changes with the progress of the received signal, and the offset timing is continuous twice. When they match, it is determined that there is a synchronization point. Therefore, it is possible to realize the apparatus invention of claim 1, provides the same effect as the invention described in claim 1.

In a fourth aspect of the present invention, a synchronization having a plurality of correlation detectors for inputting a received signal spectrum-spread by a spread code, and a determiner for receiving the outputs of the plurality of correlation detectors as inputs. In the capturing device, each of the correlation detectors is set with a part or all of the divided spread codes obtained by dividing the spread code into J,
Correlation detection of the received signal and a part or all of the divided spread codes is performed, and the determiner supplies a plurality of correlation values by the correlation detection, respectively, by J of the cycle of the spread code. Each time one-half the division period elapses, a plurality of synchronous additions are performed while being switched to the next order, so that a period that is a multiple of the one-Jth division period of the spreading code is obtained. Performing synchronous addition, repeating the synchronous addition, comparing the values obtained by synchronously adding the correlation values of the correlation detectors in each of the synchronous additions, or a part of the divided spread code that gives the maximum correlation value or All codes and offset timing are specified, and some or all of the divided spread codes that give the maximum correlation value change as the received signal progresses, and the offset timing When the match grayed is a predetermined number, it is to determine that there is a synchronization point. Therefore, claim 2
It can be realized the invention described as an apparatus, according to claim 2
The same operation as the invention described in (1) is achieved.

[0027]

[0028]

[0029]

Figure 1 DETAILED DESCRIPTION OF THE INVENTION, in the embodiments of the present invention
It is a block diagram of a first premise configuration as a premise. 10, those parts that are the same as those corresponding parts in FIG. 10 are designated by the same reference numerals, and a description thereof will be omitted. A determiner 3 has a maximum value selection unit 4 and an offset timing comparison unit 5. Matched filter 1
Has the same spreading code as the transmission side set as its tap coefficient. A received signal spectrum-spread by the spread code is input, and correlation detection between the received signal and the spread code is repeated over a plurality of cycles of the spread code. The maximum value selection unit 4 detects the offset timing that gives the maximum correlation value in each cycle of the spreading code. When there is a predetermined number of coincidences in the offset timing, the offset timing comparison unit 5 determines that the offset timing has a synchronization point, and outputs a signal indicating that the synchronization has been acquired. The above-described predetermined number is, for example, two times, and when the offset timings match twice, it is determined that there is a synchronization point at the offset timings. Alternatively, the number of cycles for continuously observing the correlation value is also set, and when the number of times the offset timings match is a predetermined number of times or more during that period, it is determined that there is a synchronization point at the offset timings. Good.

FIG. 2 is an explanatory diagram showing a specific example of the synchronization acquisition method in the first premise structure shown in FIG. The matched filter 1 outputs a correlation value for each chip cycle or each cycle in which this chip cycle is oversampled.
The maximum value detection unit 4 observes this matched filter output over one cycle of the spread code, for example, twice. The offset timing comparison unit 5
The offset timing that maximizes the output of the matched filter 1 is compared. Comparison of each offset timing,
The comparison is performed by the phases (code phase offsets # 0, # 1) from the start of observation of each cycle to the offset timing. If they match, it is determined that synchronization has been achieved with the offset timing as the synchronization point. It is possible to make a more reliable judgment as compared with one-time maximum value selection.

If they do not match, we cannot trust them.
Start over. That is, the output of the matched filter is observed again for one cycle of the spread code, its offset timing is compared with the previous offset timing, and if they match, it is determined that synchronization has been achieved. If they do not match, the output of the matched filter is set to 1 of the spreading code again.
Observe over a period and make the same judgment. It is desirable to set a limit in advance on the number of times the correlation is detected again. When it is determined that the synchronization is achieved, the next confirmation mode is entered, as in the conventional case. However, in this synchronization acquisition mode, if the synchronization detection error rate is sufficiently small, the operation mode may be immediately entered.

The comparison of the above-mentioned offset timing is as follows.
The point that correlation detection is performed over a plurality of observation periods has something in common with the conventional synchronous addition. However, in the conventional synchronous addition, the noise level is reduced by averaging the output level of the correlation value, that is, the power level of the correlation value. On the other hand, the present invention has found that there is little fluctuation in the time axis direction of the correlation output, and based on this finding,
The offset timing is compared. As a result of the comparison, if the offset timings match a plurality of times, it is determined that the offset timings have a correct synchronization point.

In the above description, all chips of the spread code are used as the tap coefficients of the matched filter 1.
However, as described with reference to FIG. 12, partial correlation may be detected, and in this case, as the tap coefficient of the matched filter 1, a part of the spread code, for example, the code sequence of the rear part may be used. .

FIG. 3 is a premise of each embodiment of the present invention.
That is a block diagram of a second premise configuration. In the figure,
0, the same parts as those in FIG. The determiner 12 has a synchronous addition memory 11, and synchronously adds the outputs of the matched filter 1 and outputs the result to the maximum value selection unit 4. This embodiment is based on the first premise shown in FIG.
This is a structure to which the synchronous addition technology is applied. The synchronous addition memory 11 performs synchronous addition over a plurality of cycles of the spread code, and repeats this synchronous addition. The maximum value selection unit 4 detects the offset timing that gives the maximum correlation value from the correlation values stored in the synchronous addition memory for each synchronous addition. The offset timing comparison unit 5 compares the offset timing output from the maximum value selection unit 4, and when there is a predetermined number of coincidences in the above-described offset timing, determines that there is a synchronization point at the offset timing, and acquires the synchronization. It outputs a signal indicating that it has done.

More specifically, the synchronous addition memory 11 is
Matched filter 1 in the first cycle of the spreading code
Stores the correlation value output by each unit cycle (chip cycle or oversampled cycle),
In the cycle, the correlation value newly input from the matched filter 1 is added to the correlation value stored in each unit cycle, and the correlation value is stored again in the same position (address) in each unit cycle. is there. Such a storage operation is performed for a plurality of predetermined cycles, the result is output to the maximum value selection unit 4, the storage content is cleared, and the next synchronous addition is performed.

In each of the synchronous additions, the number of cycles of the spreading code to be synchronously added is determined in advance, but it is not always necessary to set the same predetermined number, and it may be different for each time. Further, the above-mentioned predetermined number is not limited to two consecutive times, but may be a plurality of consecutive two or more times, and the synchronous addition is performed a predetermined number of times B, and the offset timing is equal to or more than A times during B times. If so, it may be determined that there is a synchronization point. Also in this second premise configuration , as the tap coefficient of the matched filter 1, a part of the spread code, for example, a code sequence of the rear part may be used to perform the partial correlation detection.

FIG. 4 is a block diagram of the first embodiment of the present invention. 13, those parts that are the same as those corresponding parts in FIG. 13 are designated by the same reference numerals, and a description thereof will be omitted. A determiner 22 has a maximum value selection unit 23, a divided spreading code and an offset timing comparison unit 24. In this embodiment, similar to the conventional technique described with reference to FIG. 13, the correlation detection is performed by using the spread spectrum code. Each of the matched filters 21 _{0 to} 21 _J-1 is set with each division spreading code of equal length obtained by equally dividing the spreading code into J pieces as a tap coefficient, and reception spread spectrum is performed by the spreading code. By inputting a signal, the correlation detection between the received signal and each divided spread code is detected by a unit cycle (chip cycle or oversampling thereof) over a cycle that is a multiple of 1 / J of the spread code cycle. Every cycle) and repeatedly in parallel. The maximum value selection unit 23, in each division cycle, for each unit cycle, the matched filters 21 _{0 to} 21 _J-1.
The correlation values of the above are compared to identify one matched filter that has output the maximum correlation value and the offset timing.

The division spread code and offset timing comparison unit 24 specifies the division spread code that outputs the maximum correlation value from the tap coefficient of the specific matched filter output by the maximum value selection unit 23 for each division cycle. . At the same time, when the specified matched filter and the specified divided spreading code are moving with the progress of the received signal and the offset timings are coincident with each other, the coincidence is determined, and the coincidence is determined by a predetermined number. At some point, it is determined that there is a sync point.

FIG. 5 is an explanatory diagram showing a concrete example of the synchronization acquisition method in the embodiment shown in FIG. When the matched filters 21 _{0 to} 21 _J-1 detect the correlation over the time of 1 / J of the spread code period, a synchronization point synchronized with the spread code is detected. The maximum value selection unit 23 observes the outputs of all the matched filters 21 _{0 to} 21 _{J-1 in} the first observation period (1 / J cycle of the spread code), and selects the offset timing having the maximum value from among them. Take it out. In the illustrated example, it is assumed that the maximum value is found at the offset timing (code phase offset # 0) of the matched filter 21 ₀ . Over the next observation period, the outputs of all the matched filters 21 _{0 to} 21 _J-1 are observed again, and the offset timing having the maximum value is extracted from them. In the illustrated example, the maximum value is found at the offset timing (code phase offset # 1) of the matched filter 21 ₁ .

One observation period (1 / J cycle of spreading code)
, The input received signal is spread with a code that follows for a division period, so that the original spread code is equally divided and created.
Among the first to the plurality of divided spread codes, the correlation value with the divided spread code in the next order becomes the maximum. The plurality of divided spreading codes from the 0th to the (J-1) th are sequentially assigned as the coefficients of the matched filters 21 _{0 to} 21 _J- 1.
Each time the observation period (1 / J cycle of the spread code) elapses, the order of the matched filter that outputs the maximum correlation value also advances by one.

Therefore, the division spread code / offset timing comparison unit 24 not only matches the offset timings, but also the order of the matched filters that output the maximum value, in other words, the order of the division spread codes that output the maximum value. , Are also consecutively checked, and if these sequences are consecutive, it is determined that there is a synchronization point. In the illustrated example, since the matched filter 21 ₁ outputs the maximum value in the second observation period of the correlation detection, the order is continuous. Therefore, if the offset timings match (the code phase offsets # 0 and # 1 match) in the two observation periods of the correlation detection, it is determined that the synchronization has been acquired.

The above-mentioned offset timing is the offset timing based on the phase of the divided spread code,
It is a value that is repeated in the division cycle. Therefore, in other words, the offset timing based on the phase of the original spreading code (represented by the value repeated in the spreading period) is the offset timing obtained in each observation period as the progress of the input received signal. When changing, it is equivalent to determining that the synchronization has been acquired.

Also in this embodiment, the first prerequisite
The partial correlation similar to the above may be performed. As a tap coefficient for each of the matched filters 21 _{0 to} 21 _J-1 , a part of each divided spreading code, for example, a code sequence at the rear of each divided spreading code is used. In this case, the lengths of the code sequences extracted from the divided spread codes are the same. The extraction method from each divided spread code is also the same. When the extraction method is different, for example, a certain spreading code from the rear code sequence,
When the preceding code sequence is extracted from another divided spread code, the coincidence of the offset timing may be determined according to the phase difference between the extracted code sequences.

FIG. 6 is a block diagram of the second embodiment of the present invention. 13, those parts which are the same as those corresponding parts in FIGS. 13 and 4 are designated by the same reference numerals, and a description thereof will be omitted. 31 is a judging device, 3
Reference numeral 2 is a switching selection unit, and reference numerals 33 _{0 to} 33 _J-1 are synchronous addition memories. In this embodiment, the synchronous addition technique is applied to the first embodiment described with reference to FIGS. 4 and 5. Each of the matched filters 21 _{0 to} 21 _J-1 is set with each divided spreading code obtained by dividing the spreading code into J as a tap coefficient. The received signal spectrum-spread by the spread code is input, and the correlation detection between the received signal and each divided spread code is detected by a unit cycle (unit cycle (1 / J of the spread code cycle)) over a plurality of observation periods. It is repeated in parallel every chip cycle or a cycle in which it is oversampled.

In order to execute the synchronous addition, the switching selection section 32 causes the synchronous addition memories 33 _{0 to} 33 _J-1 to receive the correlation values from the matched filters 21 ₀ to 21 ₀ to 33 every time the division period described above elapses. 21 _{Switch J-1} to the next one. That is, the received signal is
It is spread with a code that follows only the division period. Therefore, each time the above-described division period elapses, the output of the matched filter whose tap coefficient is the code that follows in time is added to the output of the original matched filter stored in the synchronous addition memory to obtain the correlation. Remember the value.

A more specific description will be given. Similar to the first embodiment, the divided spreading codes from the 0th to the (J-1) th, which are created by dividing the original spreading code, are
It is assumed that they are sequentially assigned as the tap coefficients of the matched filters 21 _{0 to} 21 _J-1 . In the first cycle of the observation period, the synchronous addition memories 33 _{0 to} 33 _J-1 input the outputs of the matched filters 21 _{0 to} 21 _J-1 , respectively. In the next cycle, the synchronous addition memories 33 _{0 to} 33 _J-1
Inputs the outputs of the matched filters 21 _{1 to} 21 _J-1 and 21 ₀ . Further, in the next cycle, the synchronous addition memory 33 ₀
~ 33 _J-1 are matched filters 21 _{2 to} 21 respectively.
Input the output of _J-1 , 21 ₀ , 21 ₁ . In this way
With the number of times of synchronous addition, the switching selection unit 32 switches the input destination to the next matched filter.

The synchronous addition memories 33 _{0 to} 33 _J-1 carry out synchronous addition over a plurality of cycles with the division cycle as a unit as the received signal progresses, and this synchronous addition itself is repeated a plurality of times. The maximum value selection unit 23, at the end of each one-time synchronous addition, uses the synchronous addition memory 33.
_The correlation values stored in _{0 to} 33 _J-1 are compared to detect the specific synchronous addition memory that gives the maximum correlation value and the offset timing. The division spread code / offset timing comparison unit 24 outputs, from the specific matched filter output by the maximum value selection unit 23, each time the synchronous addition ends.
The divided spread code that outputs the maximum correlation value is specified, and its offset timing is stored. For each synchronous addition, the specified matched filter, that is, the specified split spreading code changes with the progress of the received signal,
When the offset timings match, it is determined that they match. Further, when there is a predetermined number of coincidences in the offset timing, it is determined that there is a synchronization point.

Here, the above-mentioned predetermined number is the above-mentioned second number.
Similar to the premise configuration , the number of times is not limited to two consecutive times, but may be two or more times consecutively. Further, if the offset timings match A times or more during B times of synchronous addition,
It may be determined that there is a synchronization point. However, at this time, the fact that the synchronous addition memory that outputs the maximum value is moving with the progress of the received signal is also added to the determination condition. In addition, in each time of the synchronous addition, the number of cycles for the synchronous addition may be arbitrary, and the number of cycles for the synchronous addition may be different for each of the synchronous additions. Also in this embodiment, partial correlation similar to that of the first embodiment may be performed. In the above description, the switching selection unit 32 is provided to switch the output destination of the matched filters 21 _{0 to} 21 _J-1 , but the switching selection unit 32 is not provided, and conversely, the matched filter 21 ₀ is not provided.
The tap coefficient of ~ 21 _J-1 may be switched.

FIG. 7 is an explanatory view schematically showing the operation of the embodiment shown in FIG. The spread code is equally divided into J = 4, and the divided spread codes are G ₀ , G ₁ , G ₂ , and G _3, and each divided spread code is a code having the same number of chips. It is assumed that the synchronous addition is performed over a period that is twice the division period and the offset timings in the two synchronous additions are compared. The upper row is an array of code sequences of the spread spectrum signal received so that the time progresses in the right direction. To simplify the explanation, the transmission information data is +
Since it is 1, the spread code appears as it is in the received spread spectrum code. 4 blocks the lower represents the matched filter 21 _{0-21 3} schematically, divided spreading codes described above is used as the coefficient of each matched filter 21 _{0-21 3.}

[0050] This figure with the progress of the observation period, while the matched filter 21 _{0-21 3} moves to the right,
It schematically shows how the correlation detection operation is performed by taking in the code sequence of the received spread spectrum signal immediately above. While the observation period elapses 1/4 of the spreading code period,
There is a timing at which one of the divided spread codes G _{0 to} G _{3 that} is the coefficient of each matched filter 21 _{0 to} 21 ₃ and the received spread spectrum signal match. In the first cycle of the observation period, the received signal and the divided spread code G ₁ match at the offset timing (hereinafter simply referred to as offset timing φ ₀ ) at which the code phase offset φ _{0 has} elapsed from the initial phase. At this time, among the matched filters 21 _{0 to} 21 ₃ , the matched filter 2 having the divided spreading code G ₁ as a coefficient
The correlation value output by 1 ₁ is the maximum. The output of the matched filter 21 ₁ (denoted as MF1 in FIG. 7) is stored in the synchronous addition memory 33 ₁ for each chip period via the switching selection unit 32.

In the second period of the observation period, since the received signal is advancing, the received signal and the next divided spread code G
₂ coincides with the offset timing φ ₀ from the initial phase. Since the division cycle is considered as a code phase, the initial phase is returned every time one division cycle elapses. At this time, in the matched filter 21 _{0-21 3,}
The correlation value (denoted as MF2) output by the matched filter 21 ₂ having the divided spread code G ₂ as a coefficient becomes maximum. Since the switching selection unit 32 switches so as to select the next matched filter, the output (MF2) of the matched filter 21 ₂ is output to the synchronous addition memory 33 ₁ via the switching selection unit 32. In the synchronous addition memory 33 ₁ , the output (MF2) of the matched filter 21 ₂ is added to the stored output (MF1) of the matched filter 21 ₁ for each chip cycle and is stored again.

With the above, the first synchronous addition is completed, and the maximum value is reached.
The selection unit 23 uses the synchronous addition memory 33. ₀~ 33₃In the
Huset timing φ₀, The maximum correlation output
Synchronous addition memory 33 to remember₁Specify. This time, minutes
Split spreading code G₂Offset timing of φ₀Has a sync point
is there. Synchronous addition memory 33₀~ 33₃Memory contents are deleted
Be done.

In the third period of the observation period, the received signal and the next divided spread code G ₃ match at the offset timing φ ₀ from the initial phase. At this time, in the matched filter 21 _{0-21 3,} divided spreading code correlation values matched filter 21 ₃ outputs a G ₃ a coefficient (M
(Denoted as F3) is the maximum. The output of the matched filter 21 ₃ is stored in the synchronous addition memory 33 ₁ for each chip cycle via the switching selection unit 32. In the fourth period of the observation period, the received signal and the next divided spread code G ₀ are offset timing φ ₀ from the initial phase.
Matches with. At this time, the matched filters 21 _{0 to} 21 ₃
Among them, the correlation value (denoted as MF0) output from the matched filter 21 ₀ having the division spread code G ₀ as a coefficient becomes the maximum. The output (MF0) of the matched filter 21 ₀ is
It is output to the synchronous addition memory 33 ₁ via the switching selection unit 32. In the synchronous addition memory 33 ₁ , the output (MF0) of the matched filter 21 ₀ is added to the stored output (MF3) of the matched filter 21 ₃ for each chip cycle and stored again.

With the above, the second synchronous addition is completed, and the maximum value is reached.
The selection unit 23 uses the synchronous addition memory 33. ₀~ 33₃In the
Huset timing φ₀, The maximum correlation output
Synchronous addition memory 33 to remember₁Specify. This time, minutes
Split spreading code G₀Offset timing of φ₀Has a sync point
is there. Synchronous addition memory 33₀~ 33₃Memory contents are deleted
Be done.

The division spread code and offset timing comparing section 24 determines the offset timing φ ₀ of the division spread code G ₂ which has the maximum correlation value in the first synchronous addition and the correlation value in the second synchronous addition. Is compared with the offset timing of the divided spread code G ₀ having the maximum value. Since the progress of the received signal from the end point of the first synchronous addition to the end point of the second synchronous addition was for two cycles of the observation period, the change in the divided spreading code with the maximum correlation value is Consistent with the progress. In addition, the offset timings are both φ ₀ and therefore match.
As a result, the division spread code and offset timing comparison unit 24 outputs a signal indicating synchronization acquisition. At this time, it can be seen that the synchronization point is located at the offset timing φ ₀ of the divided spread code G ₀ .

As described above, the direct spread spectrum received signal is input and the synchronization of the spread code is captured .
Similarly to the first and second preconditions and the first and second embodiments, a code having a predetermined code pattern is inputted by inputting a received signal in which a code string having a predetermined code pattern is periodically inserted. You can perform column synchronization. For that purpose, the “spread code” in the first and second prerequisite configurations and the first and second embodiments may be simply replaced with “a code string having a predetermined code pattern” and applied. Hereinafter, two application examples in the case where a code string having a predetermined code pattern is used as a preamble as a pilot signal will be described again as first and second related configurations .

FIG. 8 is an explanatory diagram showing a specific example of the synchronization acquisition method in the first related configuration of the present invention. The frame format has the same configuration as the conventional one shown in FIG. As the block configuration, the one shown in FIG. 1 is used, and the code of the preamble described above is used as the coefficient of the matched filter 1. Similar to FIG. 15, the length of the matched filter is set equal to the code length of the preamble. In FIG. 1, a matched filter 1 receives a reception signal in which a preamble code is periodically inserted at the beginning of one frame, repeats correlation detection over a plurality of frame periods, and outputs one correlation value for each unit period. . The maximum value selection unit 4 detects the offset timing that gives the maximum correlation value in each frame period, and the offset timing comparison unit 5 has a synchronization point with the preamble code when there is a predetermined number of matching offset timings. To determine.

In FIG. 8, the maximum value selection unit 4 sets the offset timing that gives the maximum correlation value in the first frame period of two consecutive frames from the initial phase at the start of observation to the code phase offset # 0. Detect in position. In the next frame period, detection is performed at the position of code phase offset # 1 from the initial phase at the start of observation. When the offset timings coincide with each other twice in succession, the offset timing comparison unit 5 determines that the offset timings have a synchronization point, and outputs a signal indicating synchronization acquisition.

Next, as the second related configuration , the above-mentioned first
On the premise of the related configuration of No. 1, the second described with reference to FIG.
The synchronous addition technique can be applied using the block configuration of the prerequisite configuration . That is, in FIG. 3, the matched filter 1 detects the correlation between the received signal and the preamble code by synchronous addition over a plurality of frame periods, and the maximum value selector 4 determines the maximum correlation value in each synchronous addition. The offset timing comparison unit 5 detects the offset timing to be given, and determines that there is a synchronization point when there is a predetermined number of matching offset timings. The number of frames to be synchronously added is arbitrary, and the number of frames to be synchronously added does not necessarily match in each of the plural times of synchronous addition. Also in the above-described first and second related configurations , the above-described predetermined number of times of matching offset timing is not limited to two consecutive times but may be a plurality of consecutive times. The determination may be performed B times, and if the offset timings match A times or more during this B times, it may be determined that there is a synchronization point.

FIG. 9 shows the case of using the spread code of the present invention.
It is the diagram which evaluated the synchronous acquisition characteristic about the 1st Embodiment which does not perform synchronous addition by the computer simulation. The PN code has a code length N of 32768, spread spectrum is performed by BPSK, the number of matched filters J is 8, and the tap length (code length) of the matched filters is 64. 9 (a) is under Gaussian noise, and FIG. 9 (b) is under 7-wave selective fading environment, respectively, the synchronization point detection error rate (Probabilility of f) with respect to SNR (Signal to Noise Ratio).
alse acquisition) is obtained. We used a model in which the average signal power of each fading path decreased exponentially from the leading path. For comparison, the conventional method (γ ₀ =
The synchronous acquisition characteristic of 16) is shown by the dotted line. However, the number of retries in the capture mode was limited to 20 each. In both environments, the method of the present invention exhibits superior characteristics to the conventional method. It can be seen that the synchronization acquisition method of the present invention is superior to the synchronization acquisition method according to the conventional technique, particularly in a good SNR (-5 dB or more).

In the above description, the case where the matched filter is operated with the chip cycle of the spread code as a unit has been described. On the other hand, there is an oversampling operation in which the matched filter is operated at a time interval of 1 / (integer) of the chip cycle. The oversampling operation can also be performed in each of the preconditions, embodiments , and related structures of the present invention. Correlation detection, maximum value detection, and offset timing determination, including offset timing comparison, are performed with an integral multiple of the chip timing of the spreading code, and the offset timing is determined to match when it is within a predetermined range. You may do it.

Specifically, the number of stages of the matched filter is a
(Integer) times, tap output is taken out at 1-chip intervals to perform correlation detection. The correlation output is the chip timing a.
The maximum value detection is also performed at this interval because the data is output at a time interval of one-half. Regarding the maximum value detection, the code phase offset can be known at a time interval of 1 / (integer) of the chip timing. Therefore, there are two determination methods when comparing the offset timings. The first method is to check the coincidence at a time interval of a (integer) times the chip timing. The second method is a method of determining that the offset timings are coincident with each other if the offset timing deviation is within a predetermined range, for example, within a predetermined range of less than one chip. In this example, when a = 4 times,
If there is a shift of two timings or less, it is considered that they match.

In the above description, the correlation detection is performed using the matched filter. Examples of the matched filter include an analog type or digital type transversal filter, a matched filter using a surface acoustic wave element (SAW), and a SAW convolver having a function equivalent to that of the matched filter. Alternatively, it is possible to detect the correlation using a sliding correlator. However, as the synchronization acquisition time becomes significantly long, the control for selecting the spreading code to be given to the sliding correlator from the memory becomes complicated.

[0064]

As is apparent from the above description, the present invention does not require a threshold value to be set for the level of a correlation value having a large fluctuation as in the prior art to make a judgment, but the correlation output with a small fluctuation in the time axis direction. The timing information is used to determine the offset timing at which the matched filter outputs the maximum value. Therefore, there is an effect that the accuracy of synchronously capturing a spread spectrum code or a code string having a predetermined code pattern is higher than in the past. As a result, it is possible to shorten the time required for these synchronization acquisitions.

[Brief description of drawings]

First premise underlying the respective embodiments of the present invention; FIG
It is a block diagram of a configuration.

FIG. 2 is an explanatory diagram showing a specific example of a synchronization acquisition method in the first premise configuration shown in FIG.

[Figure 3] a second premise is a premise of the embodiments of the present invention
It is a block diagram of a configuration.

FIG. 4 is a block configuration diagram of a first embodiment of the present invention.

5 is an explanatory diagram showing a specific example of a synchronization acquisition method in the embodiment shown in FIG.

FIG. 6 is a block configuration diagram of a second embodiment of the present invention.

FIG. 7 is an explanatory diagram schematically showing the operation in the embodiment shown in FIG.

FIG. 8 is an explanatory diagram showing a specific example of the synchronization acquisition method in the first related configuration of the present invention.

FIG. 9 is a diagram in which the synchronization acquisition characteristic of the first embodiment of the present invention is evaluated by computer simulation.

FIG. 10 is a block diagram showing a first example of a conventional synchronization acquisition device in a direct sequence spread spectrum communication system.

11 is a first explanatory diagram of the synchronization acquisition method in the conventional technique shown in FIG.

12 is a second explanatory diagram of the synchronization acquisition method in the conventional technique shown in FIG.

FIG. 13 is a block diagram showing a second example of a conventional synchronization acquisition device in a direct sequence spread spectrum communication system.

FIG. 14 is a second explanatory diagram of the synchronization acquisition method in the conventional technique shown in FIG.

FIG. 15 is an explanatory diagram showing a conventional synchronization acquisition method in a communication system in which a preamble is periodically inserted.

[Explanation of symbols]

1,21 _{0 to} 21 _J-1 ... Matched filter, 3, 12, 2
2, 31 ... Judgment device, 4, 23 ... Maximum value selection unit, 5 ... Offset timing comparison unit, 11 ... Synchronous addition memory, 24 ...
Division spread code and offset timing comparison unit, 32
... Switching selection section, 33 _{0 to} 33 _J-1 ... Synchronous addition memory

Continuation of the front page (56) Reference JP-A-8-307314 (JP, A) JP-A-7-297805 (JP, A) JP-A-11-289276 (JP, A) JP-A-10-190619 (JP , A) Makoto Yamada, A Study on Synchronous Acquisition Using Multiple Matched Filters, Proc. Of the 2000 IEICE General Conference, March 7, 2000, Communications 1,449, B-5-64 (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69-1/713 H04L ⁷ /00-7/10

Claims (4)

(57) [Claims] 1. A correlation detection between a part or all of each divided spread code obtained by dividing a spread code into J and a received signal spectrum-spread by the spread code is detected by a cycle of the spread code. Repeated over a period that is a multiple of one Jth division period, and in each of the division periods, a part or all of the division spread codes that give the maximum correlation value and the offset timing are detected, and the maximum correlation is detected. It is determined that there is a synchronization point when a part or all of the divided spread codes that give a value change as the received signal progresses and the offset timings match twice in succession. A synchronization acquisition method characterized by: 2. Correlation detection of a part or all of the divided spread codes obtained by dividing the spread code into J and a received signal spectrum-spread by the spread code is performed in parallel, and the correlation is obtained. Supply of multiple correlation values by detection,
Each time a division period of 1 / J of the spread code period elapses, a plurality of synchronous additions are performed while being switched to the next order, so that 1 / J of the spread code period is obtained. Of the divided spread code that provides the maximum correlation value and the offset timing are detected in each of the synchronous additions. However, a part or all of the division spread codes that give the maximum correlation value change with the progress of the received signal, and when there is a predetermined number of coincidences of the offset timing, there is a synchronization point. A synchronization acquisition method characterized by: determining. 3. A synchronization acquisition device comprising: a plurality of correlation detectors that receive a spread spectrum signal by a spread code; and a determiner that receives the outputs of the plurality of correlation detectors. In the correlation detector, some or all of the divided spread codes obtained by dividing the spread code into J are set,
The correlation detection between the received signal and a part or all of the divided spread codes is repeated over a period that is a multiple of a division period of 1 / J of the period of the spread code. In each division period, the correlation values of the correlation detectors are compared to identify a part or all of the division spread codes that give the maximum correlation value and the offset timing, and give the maximum correlation value. It is determined that there is a synchronization point when some or all of the divided spread codes change with the progress of the received signal and the offset timings match twice in succession. Synchronization acquisition device. 4. A synchronization acquisition device comprising: a plurality of correlation detectors that receive a spread spectrum signal by a spread code; and a determiner that receives the outputs of the plurality of correlation detectors as inputs. In the correlation detector, some or all of the divided spread codes obtained by dividing the spread code into J are set, and the received signal and the codes of some or all of the divided spread codes are set. Correlation detection is performed, and the determination unit switches the supply of a plurality of correlation values by the correlation detection to the next order each time a division period of J / J of the period of the spread code elapses. By performing a plurality of synchronous additions that are received while being performed, the synchronous additions are performed over a period that is a multiple of a division period of 1 / J of the spreading code period, and the synchronous additions are repeated. By comparing the values obtained by synchronously adding the correlation values of the respective correlation detectors, a part or all of the division spread codes that give the maximum correlation value and offset timing are specified, and the maximum correlation value is given. A synchronization acquisition device, which determines that there is a synchronization point when a part or all of the divided spread codes change with the progress of the received signal and there is a predetermined number of coincidences of the offset timings. .