JP3467167B2 - Interrupt processing method and apparatus in programming language processing system and recording medium thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method, an apparatus and a recording medium for a programming language processing system, and particularly to efficiently process a request from a user at any time in a programming language processing system. The present invention relates to an interrupt processing method, device and recording medium in a programming language processing system.

[0002]

2. Description of the Related Art As one of typical methods for realizing a high-level language processing system, a virtual computer suitable for executing the high-level language is assumed, and a program written in the high-level language is virtualized by the virtual computer. A virtual computer program that translates into an instruction sequence and interprets and executes the virtual instruction of the virtual computer is realized on a normal computer (hereinafter, referred to as a host computer), and the virtual instruction sequence is executed by the virtual computer program. There is something.

Lisp and Prolog
In the symbol processing language represented by og), the implementation method of such a processing system has been widely adopted. Further, recently, the realization of the programming language Java is premised on the use of a virtual computer.

Now, in implementing a language processing system, it is necessary to deal with the case where the user tries to interrupt the execution of the program by using a means such as pressing down the control key from the keyboard at any time. There is a need to.

In a general program, such processing can be achieved by creating an interrupt processing unit to be executed when an interrupt request from a user is detected and registering this processing unit.

During execution of the virtual computer program, in order to guarantee the correct execution of the language processing system, it is necessary to perform an interrupt process at a time when the execution of the virtual computer program is not affected. Specifically, if interrupt processing is performed during execution of one virtual instruction, it is not possible to guarantee that the state of the virtual machine is consistent before and after the interrupt processing. It is necessary to perform an embedded process.

In order to realize such a request, an area for recording the detection of an interrupt is prepared in the virtual computer program, and as an instruction string to be executed when the interrupt is detected, An instruction string that records the fact that an interrupt is detected is registered in the area for recording the detection of the interrupt, and the interrupt is recorded at the beginning of repeated interpretation / execution of virtual instructions of the virtual computer program. A technique has been considered in which the content of the detection recording area is examined, and if it is recorded that an interrupt is detected, the formal interrupt processing in the virtual computer program is executed again.

An example of realizing a virtual machine using such a conventional interrupt processing method will be described with reference to the drawings. It should be noted that the drawings used below show only the minimum necessary components necessary for explaining the present invention, and do not prevent inclusion of other components.

First, reference numeral 100 in FIG. 8 is a host computer that executes a virtual computer program. Reference numerals 110 and 120 are CPs of this host computer, respectively.
U is a memory area. The CPU 110 includes a program counter 111, a register 112, and an interrupt detection circuit 113. As for the CPU 110, only the portion related to the description here is shown.

In the memory area 120, the interrupt detection circuit 1
Reference numeral 13 denotes a first CPU save area 180 for saving the state of the CPU at the time of interrupt detection, and a first area for registering the start address of an instruction sequence to be executed at interrupt detection. The head address storage area 170 of the instruction sequence of is reserved.

An external storage device 130 is connected to the host computer 100. The external storage device 130 stores a virtual computer program 131, and a virtual computer instruction sequence 132 in which a program written in a high-level language is translated into the virtual computer. Is stored.

Further, a display device 140 and an input device 150 are connected to the host computer 100, and a user starts / ends / ends a program while using these devices.
Give instructions such as interrupts.

When the user gives an instruction to execute the virtual instruction sequence, the host computer 100 executes the virtual computer program 1
31 is stored in the memory area 120, and this program is executed using the CPU 110.

The virtual computer program 131 stores the virtual computer instruction sequence 132 in the memory area 120 and interprets / executes the instructions of the virtual computer instruction sequence 132 one by one to achieve the execution of the virtual computer instruction sequence 132. .

FIG. 9 shows in detail the contents of the memory area 120 of the host computer 100 when the virtual computer instruction sequence 132 is executed using the virtual computer program 131. The virtual computer program 131
Uses other memory areas, but they are omitted because they are not directly related to the description here.

When the user tries to execute the virtual machine instruction sequence 132 also shown in FIG. 8 by using the virtual machine program 131 shown in FIG. 8, first, the virtual machine program 131 is expanded on the memory, and as a result, , Virtual instruction interpretation execution unit 210, interrupt processing unit 220, virtual computer interrupt processing unit 260, virtual computer initialization unit 240, virtual computer instruction sequence storage area 250, and an interrupt detection flag indicating whether an interrupt has been detected. The storage area 230 is created.

Subsequently, the virtual machine initialization unit 240 is executed, and the head of the interrupt processing unit 220 is stored in the head address storage area 170 of the first command string which stores the head address of the command string to be executed when the interrupt occurs. 8 is registered, the virtual computer instruction sequence 132 stored in the external storage device 130 shown in FIG. 8 is expanded in the virtual computer instruction sequence storage area 250 on the memory area 120, and this is executed by the virtual instruction interpretation execution unit 210. Use and execute.

FIG. 10 is a flow chart showing an outline of the operation of the virtual instruction interpretation execution unit 210 shown in FIG. First, in step 101, the contents of the interrupt detection flag storage area 230 shown in FIG. 9 are confirmed. If no interrupt is detected, the process proceeds to step 102, the virtual instruction to be executed next is taken out, the virtual instruction is interpreted / executed in step 103, and the process returns to step 101.

When the presence of an interrupt is detected by the interrupt detection flag in the interrupt detection flag storage area 230 in step 101 (the establishment of the interrupt detection flag at the time of interrupt will be described later), the interrupt detection is performed in step 104. The flag is set to no interrupt, and the process proceeds to step 105, where the virtual computer interrupt processing unit 260 shown in FIG. 9 executes the interrupt process in the virtual computer. As a specific processing content of the virtual machine interrupt processing unit 260, it is conceivable that the user is asked to confirm the intention to continue after displaying the intermediate status of the processing, but since it is not directly related to the present invention. , Omitted.

When the user uses the input device 150 to issue an interrupt request, the interrupt detection circuit 11 in the CPU 110.
3 detects this, saves the current state of the CPU 110 in the first CPU save area 180, and executes the instruction sequence from the first address registered in the first address storage area 170 of the first instruction sequence, that is, , And transfers control to the interrupt processing unit 220.

C stored in the first CPU save area 180
As the state of the PU 110, the CPU 110 shown in FIG.
Program counter 111, register 112, and the like. Since such an interrupt processing mechanism is provided in common to most CPUs and is considered to be known, its details are omitted.

FIG. 11 shows the interrupt processing unit 220 shown in FIG.
3 is a flowchart showing an outline of the operation of FIG. First, in step 1101, the presence of an interrupt is set in the interrupt detection flag storage area 230, and in step 1102, the first C shown in FIG.
Based on the information in the PU save area 180, the CPU 110 is returned to the state at the time of the interrupt, and the execution of the instruction at the time of detecting the interrupt is returned.

As described above, when the user's interrupt is detected during execution of the virtual computer program, only the interrupt processing instruction sequence is executed by the interrupt processing unit 220 regardless of the state of the virtual computer (interrupt. Establishment of detection flag), and then execution of the virtual machine is resumed. Therefore, the state of the virtual machine is consistent before and after the execution of this interrupt processing instruction sequence. Then, when proceeding to the interpretation and execution of the next virtual instruction, it is detected that there is another interrupt, and the interrupt processing in the virtual computer is executed.

[0024]

In the above-mentioned interrupt processing method in the conventional programming language processing system, it is necessary to confirm whether or not there is an interrupt from the user each time each virtual instruction is executed. It has the drawback of imposing a heavy burden on the interpretation and execution of virtual instructions.

An object of the present invention is to replace the head instruction of the iterative processing of the virtual instruction interpreting and executing section with an undefined instruction and continue the processing when there is an interrupt from the user during execution of the virtual instruction. By eliminating the interrupt confirmation process by causing the virtual machine to perform interrupt processing only when an undefined instruction is found, the efficiency of interrupt processing can be significantly improved compared to the past, and the efficiency of virtual instruction interpretation and execution can be improved. Another object of the present invention is to provide an interrupt processing method, device and recording medium thereof in a programming language processing system which can be greatly improved.

[0026]

An interrupt processing method in a programming language processing system according to a first aspect of the present invention is a user interrupt.
When a request is detected, the program state is temporarily saved and registered in advance.
Interrupt processing function to execute the specified instruction sequence and undefined instruction
When detected, the state of the program is temporarily saved and registered in advance
A computer having an undefined instruction processing function for executing an instruction sequence
To run a program written in a high-level language
In order to improve the program written in the high-level language,
Of a virtual instruction by translating it into a virtual instruction sequence suitable for executing
Using a virtual computer program that repeatedly executes interpretation and execution
By executing the virtual instruction sequence, the high-level language
A user in a programming language processor that achieves execution
A method of processing an interrupt request of the virtual computer
When starting the program, the virtual computer program
Is stored in the start address and the start address
Stores the start instruction and stores the start address in the interrupt processing function.
Instruction is rewritten to an undefined instruction to return from interrupt processing
Register the instruction sequence to be executed and undefine it in the undefined instruction processing function.
If the address where the instruction occurred is the above-mentioned address,
Write back the contents of the address to the first instruction
Register the instruction sequence to execute the interrupt processing in
When a user interrupt request is detected during the interpretation and execution of an instruction,
Activates the interrupt processing function and undefines the instruction at the first address
Rewrite to instruction Return to execution of virtual instruction
Return to the beginning of the iteration to start executing the instruction
At that time, the undefined instruction at the start address is detected and the undefined instruction
Start the processing function and change the instruction at the start address to the start instruction.
By writing back to the
The user's interrupt request to the break of virtual instruction
It is characterized by performing in.

Further, a recording medium for recording an interrupt processing method in the programming language processing system of the second invention, con
A machine that records a program for a computer
A readable recording medium written in a high-level language
Virtual instruction sequence suitable for executing the high-level language
And interpret and execute the virtual instruction of the virtual instruction sequence.
Virtual machine control function that performs return processing and user interrupt
Temporarily saves the state of running programs when a request is detected
An interrupt detection processing function that executes a pre-registered instruction sequence,
The status of the program being executed when an undefined instruction is detected
Undefined instruction that temporarily saves and executes a pre-registered instruction sequence
When the detection processing function and the virtual computer control function are activated
Is stored in the first address of the repeated processing and the first address
Function to memorize the start instruction that is stored and the interrupt detection processor
However, even if the instruction at the above start address is rewritten to an undefined instruction,
Interrupt process to register the process to return to the execution of the program
Function and the undefined instruction processing function
When it occurs at the head address, the content of the address is changed to the above
Write back to and execute the interrupt process in the virtual machine.
It has an undefined instruction processing function to register the processing to be performed.
And are characterized.

The interrupt processing device in the programming language processing system of the third invention is a program written in a high-level language.
Program into a virtual instruction sequence suitable for executing the high-level language.
Virtual computer instruction sequence case that stores translated virtual computer instruction sequence
Storage means and a virtual computer that executes the virtual computer instruction sequence
Control program storing means for storing the control program of
The virtual computer instruction sequence storage means and the control program
The information is read from the storage means and the virtual instruction is interpreted and executed.
Virtual instruction interpretation and execution means for repeatedly processing the virtual instruction
It stores the start address of the iterative process of the command interpretation execution means.
Return processing start address storage means and the repeat processing start address
Repeat to store the instruction of the first address stored in the address storage means.
Return processing start command storage means and user interrupt request detection
Temporarily save the state of the virtual instruction interpretation execution means at the time of output,
Destination stored in the repeat processing start address storage means
The instruction at the head address was rewritten to an undefined instruction and temporarily saved
When the state of the virtual instruction interpretation execution means is interrupted by data
When an undefined instruction is detected and an interrupt detection action means to return to
The state of the virtual instruction interpretation execution means is temporarily saved in
The meaningful instruction is stored in the repeating processing start address storage means.
If an error occurs at a certain address, repeat the instruction for that address.
Return processing Write to the instruction stored in the first instruction storage means
In other words, the virtual machine performs interrupt processing to
Restores the state of the instruction interpretation execution unit when an undefined instruction is detected.
Include undefined instructions and interrupt processing means
Is characterized by.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an interrupt processing method in a programming language processing system according to the first embodiment of the present invention. The host computer 100 is a CPU1
10 and memory area 120, CPU 110 has a program counter 111, a register 112 and an interrupt detection circuit 113 as in the conventional case, and memory area 120 of the CPU at that time when interrupt detection circuit 113 detects an interrupt. The first CPU save area 180 for saving the state and the first address storage area 170 of the first instruction string which is an area for registering the first address of the instruction string to be executed at the time of interrupt detection.
8 is the same as the conventional example of FIG. 8, but in the present embodiment, the undefined instruction detection circuit 510 in the CPU 110 and the CPU at that time when an undefined instruction in the memory area 120 is detected. Second CPU save area 530, which is an area for saving the state of, and the start address of the second instruction string, which is an area for registering the start address of the instruction string to be executed when an undefined instruction is detected. The storage area 520 is included. The external storage device 130 also stores a virtual computer program 540 that implements the method of the present embodiment and a virtual computer instruction sequence 132.

The details of the memory area 120 when the virtual computer instruction sequence 132 is executed by using the virtual computer program 540 registered in the external storage device 130 by using the host computer 100 shown in FIG. 1 are shown. The one is shown in FIG.

When the user tries to execute the virtual machine instruction sequence 132 using the virtual machine program 540, first, the virtual machine program 540 is expanded in the memory area 120, and as a result, the virtual instruction interpretation execution unit 610 and the interrupt are executed. Processing unit 620, virtual computer interrupt processing unit 630, virtual computer initialization unit 640, undefined instruction processing unit 650, repeated processing start address storage area 660, repeated processing start instruction storage area 670, and virtual machine instruction sequence storage area 6
80 is created.

Subsequently, the virtual machine initialization unit 640 is executed, and the interrupt processing unit 620 is stored in the first address storage area 170 of the first instruction sequence that stores the first address of the instruction sequence to be executed when the interrupt occurs. The first address is registered, and the first address of the undefined instruction processing unit 650 is registered in the first address storage area 520 of the second instruction sequence that stores the first address of the instruction sequence to be executed when the undefined instruction is detected, Repeated process start address storage area 6
The head address of the iterative process of the virtual command interpretation execution unit 610 is stored in 60, and the command of the head address of the iterative process is stored in the head command storage area 670 of the iterative process. Next, the virtual machine instruction sequence 132 is set in the memory area 1
20 is expanded in the virtual machine instruction sequence storage area 680 on the computer 20 and executed by the virtual instruction interpretation execution unit 610.

FIG. 3 is a flowchart showing an outline of the operation of the virtual instruction interpretation / execution unit 610. In step 301, the instruction to be executed next is taken out, and in step 302, the instruction is interpreted / executed.

When the user uses the input device 150 to request an interrupt, the interrupt detection circuit 11 in the CPU 110.
3 detects this, saves the current state of the CPU 110 in the first CPU save area 180, and executes the instruction sequence from the first address registered in the first address storage area 170 of the first instruction sequence, that is, The control is transferred to the interrupt processing unit 620.

FIG. 4 is a flow chart showing an outline of the operation of the interrupt processing unit 620 when an interrupt request is detected during execution of the virtual computer program. In step 401,
The contents of the head address of the iterative processing of the virtual instruction interpretation execution unit 610 recorded in the head address storage area 660 of the iterative processing shown in FIG. 2 are rewritten to an undefined instruction, and in step 402, the first CPU save area 180 The CPU 110 is restored to the state at the time of the interruption by the information in the table, and the execution of the instruction at the time of detecting the interruption is restored.

Next, the operation when the CPU 110 detects an undefined instruction will be described. This is similar to when an interrupt is detected, and when the undefined instruction detection circuit 510 in the CPU detects an undefined instruction, the current CPU state is changed to the second C
The address is stored in the PU save area 530 and the address registered in the head address storage area 520 of the second instruction sequence is executed, that is, control is transferred to the undefined instruction processing unit 650.

C saved in the second CPU save area 530
As the state of PU, the program counter 11 of the CPU
1, a register 112, and the like. Such an undefined instruction detection mechanism is also commonly provided in most CPUs and is considered to be a known one.
The details are omitted.

FIG. 5 is a flow chart showing an outline of the operation of the undefined instruction processing section 650 when an undefined instruction is detected. In step 501, the address in which the undefined instruction is detected is the start address storage area 6 of the repeating process shown in FIG.
If it is equal to the start address of the iterative process of the virtual instruction interpretation execution unit 610 recorded in 60, the process proceeds to step 502, and the start address of the iterative process of the virtual instruction interpretation execution unit 610 rewritten in step 401 of FIG. 2 is written back to the contents of the first instruction storage area 670 of the iterative processing shown in FIG. 2, and in step 503, the virtual computer interrupt processing unit 630 shown in FIG. 2 executes the interrupt processing in the virtual computer. . Then in step 504,
The information in the second CPU save area 530 shown in FIG. 2 causes the CPU 110 to return to the state when the undefined instruction was detected, and to return to the execution of the contents of the instruction address when the undefined instruction was detected.

If the address at which the undefined instruction is detected in step 501 is different from the start address of the iterative process of the virtual instruction interpretation executing unit 610 recorded in the start address storage area 660 of the iterative process shown in FIG. , And proceeds to step 505 to process a normal undefined instruction. Since the contents of the processing here are not directly related to the present invention, the description thereof will be omitted.

As described above, according to the interrupt processing method in the programming language processing system of this embodiment, when an interrupt is received from the user during the execution of the virtual instruction, the virtual instruction interpretation and execution unit repeats the processing. Replaces the first instruction of the command with an undefined instruction and continues the process, and the interrupt confirmation process of the virtual machine is eliminated by executing the interrupt process of the virtual machine only when this undefined instruction is found. The efficiency of interrupt processing can be improved, and the efficiency of interpreting and executing virtual instructions can be significantly improved.

Next, a recording medium recording a program for realizing the interrupt processing method in the programming language processing system according to the second embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the recording medium of the second embodiment.

A recording medium 1000 recording a program that realizes an interrupt processing method in a programming language processing system according to the second embodiment of the present invention, as shown in FIG. 6, stores a program written in a high-level language. A virtual machine control function 1010 for achieving the execution of a program written in a high level language by repeatedly executing the interpretation and execution of virtual instructions of a virtual machine instruction sequence translated into a virtual instruction sequence of a virtual machine suitable for executing the high level language. , Virtual computer control function 1010
A function 1011 for storing the start address and the start instruction of a repeated process of interpreting and executing a virtual instruction when the program is activated, and a function being executed when a user interrupt request generated at any time during the execution of the program is detected. An interrupt detection processing function 1012 that temporarily saves the state of the program and executes an interrupt processing instruction sequence starting from a pre-specified address, and temporarily saves the state of the program being executed when an undefined instruction is executed Then, the undefined instruction detection processing function 1014 that executes an undefined instruction processing instruction sequence starting from a pre-specified address and the interpretation and execution of the virtual instruction stored at the time of starting the virtual computer control function as an interrupt processing instruction sequence are repeatedly executed. An interrupt processing function 1013 for returning to the original program execution even if the head instruction of the processing is rewritten to an undefined instruction that cannot be executed by the computer.
And the address where the undefined instruction as the undefined instruction processing instruction sequence is stored is the beginning address of the iteration processing of the virtual computer control function, and the interpretation and execution of the virtual instruction of the virtual computer control function is repeated The program for causing the computer to realize the undefined instruction processing function 1015 for executing the interrupt processing in the virtual machine by writing back the first instruction of the above to the first instruction stored at the time of starting the virtual machine control function is recorded. It is configured.

The contents recorded in the recording medium 1000 are read by the host computer 100, and the virtual computer control function 1010, the start address and start instruction storage function 1011 of the repeated processing, the interrupt detection processing function 1012 and the undefined instruction detection are performed. The processing function 1014 is realized on the host computer 100.

When the virtual machine control function 1010 is activated, first, the start address and the start instruction of the virtual instruction interpretation and execution iterative process are stored by the storage function 1011 of the virtual instruction interpretation and execution. The program written in the language is executed.

When a user requests an interrupt at any time during execution, the interrupt detection processing function 1012 detects the interrupt, saves the current state of the virtual computer program, and then interrupts. The control is transferred to the processing function 1013, and the interrupt processing instruction sequence is executed. Among these, the instruction at the head address of the virtual instruction interpretation / execution repetitive processing is rewritten to an undefined instruction to return to the execution at the time when the interrupt is detected.

When the execution control is transferred to the beginning of the next iterative process of interpreting / executing the virtual instruction, the undefined instruction detection processing function 1014 detects an undefined instruction and determines the current state of the virtual computer program. After saving, the control is transferred to the undefined instruction processing function 1015 to execute the undefined instruction processing instruction sequence. Among them, the head of the iterative processing of the interpretation / execution of the virtual instruction is returned to the head instruction of the iterative processing of the interpretation / execution of the virtual instruction recorded at the time when the execution of the virtual computer control function 1010 is started. Efficient interrupt processing is realized by processing the interrupt request to the virtual machine.

The above-mentioned processing is performed by the recording medium 1 as described above.
It is executed by the computer under the control of the program recorded in 000.

A third embodiment of the present invention will be described with reference to the drawings.

FIG. 7 is a block diagram showing the configuration of the interrupt processing device in the programming language processing system of the third embodiment. As shown in FIG. 7, the interrupt processor in the programming language processing system according to the third embodiment translates a program written in a high-level language into a virtual instruction string of a virtual computer suitable for executing the high-level language. A virtual machine instruction sequence storage unit 1002 for storing a computer instruction sequence, and a virtual computer control program storage unit 1001 for storing a control program of a virtual computer for executing the virtual computer instruction sequence stored in the virtual computer instruction sequence storage unit 1002. A virtual instruction interpretation execution unit 1003 that reads data from the virtual computer control program storage unit 1001 and the virtual computer instruction sequence storage unit 1002 and repeatedly executes the interpretation execution of the virtual instruction.
A iterative process head command storage unit 1007 that stores the head command of the repetitive execution process in the virtual command interpretation execution unit 1003; and a virtual computer control program storage that stores the head command of the repetitive execution process in the virtual command interpretation execution unit 1003. The repeated process start address storage unit 1006 for storing the address of the unit 1001 and the repeated process start address storage unit 1006 for temporarily saving the interrupted state of the virtual instruction interpretation execution unit 1003 in response to an interrupt request from the outside. An interrupt detection processing section that restores the state of the virtual instruction interpretation execution section 1003 at the time of interruption by referring to the data stored in the virtual machine control program storage section 1001 by rewriting the instruction stored in the corresponding address in the virtual machine control program storage section 1001 to an undefined instruction. 1004 and the virtual instruction interpretation execution unit 1003 are activated when an undefined instruction is detected. The state when the undefined instruction is detected by the virtual instruction interpretation execution unit 1003 is temporarily saved, and then the storage address of the undefined instruction in the virtual machine control program storage unit 1001 becomes the address stored in the repeated processing start address storage unit 1006. When they are equal, the iterative processing start instruction storage unit 1007 is referred to and the contents stored in the address stored in the iterative processing start address storage unit 1006 of the virtual machine control program storage unit 1001 are written according to the instruction stored here. An undefined instruction and interrupt processing unit 1005 which performs a normal undefined instruction process when the state of the virtual instruction interpretation execution unit 1003 is restored by the data saved after performing the interrupt process when the undefined instruction is detected.
It is configured to include and.

The operation of the interrupt processing device in the programming language processing system of the third embodiment will be described with reference to FIG.

In the normal processing, the virtual instruction interpretation execution unit 1003 reads data from the virtual computer control program storage unit 1001 and the virtual computer instruction sequence storage unit 1002, interprets and executes the virtual instruction, and executes the virtual computer instruction sequence storage unit. The processing requested by 1002 is performed.

Next, the case where there is an interrupt request from the outside will be described. When the interrupt detection processing unit 1004 detects the interrupt request, the virtual instruction interpretation execution unit 100
The data stored in the virtual machine control program storage unit 1001 is temporarily saved in the interrupt state of No. 3 by referring to the start address storage unit 1006, and the instruction stored in the corresponding address in the virtual machine control program storage unit 1001 is rewritten to an undefined instruction and then saved. Thus, the state of the virtual instruction interpretation execution unit 1003 is restored at the time of interruption, and the operation of the virtual instruction interpretation execution unit 1003 is continued from the time of interruption.

In the virtual instruction interpretation execution unit 1003, when the head of the first repetitive processing from the time of interruption is reached, the contents of the address corresponding to the repetitive processing start address storage unit 1006 are read from the virtual computer control program storage unit 1001. Will be there. As described above, this content is rewritten by the interrupt detection processing unit 1004 into an undefined instruction. Therefore, the virtual instruction interpretation execution unit 1003 discovers this and activates the undefined instruction and interrupt processing unit 1005. Of course, even when the undefined instruction is detected by the virtual instruction interpretation execution unit 1003 in other cases than the above, the undefined instruction and interrupt processing unit 1005 is activated.

The undefined instruction and interrupt processing unit 1005 activated in response to the detection of an undefined instruction by the virtual instruction interpretation and execution unit 1003 first temporarily sets the state of the virtual instruction interpretation and execution unit 1003 when the undefined instruction is detected. After saving, it is checked whether the storage address of the undefined instruction in the virtual computer control program storage unit 1001 is equal to the address stored in the repeated processing start address storage unit 1006, and when they are equal, the interrupt detection processing unit. When it is determined that the undefined instruction is rewritten by 1004, the interrupt processing is started.

The undefined instruction and the interrupt processing of the interrupt processing unit 1005 are as follows.
The content of the address of the virtual machine control program storage unit 1001 (currently an undefined instruction) corresponding to the address stored in is referred to by the repetitive processing head instruction storage unit 1007, and the repetitive processing head instruction storage unit 1007. Rewrite to the instruction stored in. After that, the processing corresponding to the interrupt request requested from the outside is performed, and after the completion of the processing, the state saved in the virtual instruction interpretation execution unit 1003 is restored when the undefined instruction is detected, and the virtual instruction interpretation execution unit 10 is restored.
03 operation is continued.

In the undefined instruction and interrupt processing unit 1005, the virtual computer control program storage unit 1 of the undefined instruction
It is checked whether the storage address in 001 is equal to the address stored in the repeated processing start address storage unit 1006, and if they are not equal, the interrupt detection processing unit 1004.
It is determined that the undefined instruction has not been rewritten by, and normal undefined instruction processing is performed.

As described above, the interrupt processing device in the programming language processing system of the third embodiment, when there is an interrupt from the user during the execution of the virtual instruction, the virtual computer control program storage section. In the confirmation processing of the interrupt by replacing the head instruction of the iteration processing of the virtual instruction interpretation and execution unit with the undefined instruction and continuing the processing, and causing the virtual computer to perform the interrupt processing only when the undefined instruction is found. By eliminating the above, the efficiency of interrupt processing can be remarkably improved and the efficiency of interpreting and executing virtual instructions can be greatly improved.

[0059]

As described above, the interrupt processing method, device, and recording medium thereof in the programming language processing system of the present invention provide a virtual computer suitable for executing a program written in a high-level language. A virtual language in a programming language processing system that achieves program execution by executing the translated instruction sequence using a virtual computer program that translates into an instruction sequence and interprets / executes the instructions of the virtual computer one by one. In implementing the computer program, if there is an interrupt from the user during the execution of the virtual instruction, the first instruction of the iterative process of the virtual instruction interpretation and execution unit is replaced with an undefined instruction to continue the process. The interrupt confirmation processing is eliminated by causing the virtual machine to execute interrupt processing only when a definition command is found. Has the effect of significantly improving the efficiency of the interrupt processing, the efficiency of the interpretation and execution of the virtual instruction may greatly improved compared to.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of a memory area according to the first embodiment.

FIG. 3 is a flowchart showing an operation of a virtual instruction interpretation and execution unit according to the first exemplary embodiment.

FIG. 4 is a flowchart showing an operation of an interrupt processing unit according to the first embodiment.

FIG. 5 is a flowchart showing an operation of an undefined instruction processing unit of the first exemplary embodiment.

FIG. 6 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of an example of an interrupt processing method in a conventional programming language processing system.

FIG. 9 is a detailed block diagram of a memory area of an interrupt processing method in a conventional programming language processing system.

FIG. 10 is a flowchart showing an operation of a virtual instruction interpretation execution unit of an interrupt processing method in a conventional programming language processing system.

FIG. 11 is a flowchart showing an operation of an interrupt processing unit of an interrupt processing method in a conventional programming language processing system.

[Explanation of symbols]

100 host computer 110 CPU 111 program counter 112 registers 113 Interrupt detection circuit 120 memory areas 130 external storage device 131, 540 Virtual computer program 132 Virtual machine instruction sequence 140 Display Device 150 input device 170 First address storage area of first instruction sequence 180 First CPU save area 210, 610, 1003 Virtual instruction interpretation execution unit 220, 620 Interrupt processing unit 230 Interrupt detection flag storage area 240, 640 Virtual computer initialization unit 250, 680 Virtual computer instruction sequence storage area 260, 630 Virtual computer interrupt processing unit 510 Undefined instruction detection circuit 520 First address storage area of second instruction sequence 530 Second CPU save area 650 Undefined instruction processing unit 660 Start address storage area for repeated processing 670 Leading instruction storage area for repeated processing 1001 Virtual computer control program storage section 1002 Virtual machine instruction sequence storage unit 1004 Interrupt detection treatment section 1005 Undefined instruction and interrupt processing unit 1006 Repeat processing start address storage unit 1007 Iterative processing start instruction storage unit

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Claims (3)

(57) [Claims] 1. A program when a user interrupt request is detected.
To save the state of the
Embedded processing function and program status when undefined instruction is detected
Undefined instruction that temporarily saves and executes a pre-registered instruction sequence
Written in a high-level language using a computer equipped with an instruction processing function
The program written in the high-level language in order to execute the program written in the high-level language.
Translate into a virtual instruction sequence suitable for execution, interpret and execute virtual instructions
The virtual computer program that repeats
Achieve the execution of the high-level language by executing a sequence of instructions
User's interruption in programming language processing system
An interrupt processing method for processing a request, wherein when the virtual computer program is started, the virtual total
At the start address and the start address of the computer program
The stored head instruction is stored and the instruction at the head address is made an undefined instruction in the interrupt processing function.
Register the instruction sequence to rewrite and return from the interrupt processing, and the address where the undefined instruction occurs in the undefined instruction processing function.
If it is the first address, change the contents of the address to the first address.
Write back to the instruction and execute the interrupt processing in the virtual machine.
An instruction sequence for executing a line is registered, and a user interrupt request is detected during execution of interpretation of a virtual instruction.
At this time, the interrupt processing function is activated to execute the instruction at the start address.
Rewrite to undefined instruction Return to virtual instruction interpretation execution, then
Of the iteration process to start execution of the virtual instruction of
When it returns to, the undefined instruction at the start address is detected and undefined
Start the instruction processing function and set the instruction at the above-mentioned start address to the above
Write back to the head instruction and perform interrupt processing of the virtual machine
Therefore, the user's interrupt request is turned off by repeating the virtual instruction.
An interrupt processing method in a programming language processing system characterized by being performed by the eye . 2. A program written in a high-level language
Translate into a virtual instruction sequence suitable for execution of high-level language,
It is assumed that the virtual instruction of the instruction sequence is repeatedly interpreted and executed.
Memory control function and the state of the program being executed when the user's interrupt request is detected
Interrupt detection that temporarily saves and executes a pre-registered instruction sequence
The processing function and the state of the program being executed when an undefined instruction is detected
Undefined instruction that temporarily saves and executes a pre-registered instruction sequence
The detection processing function and repeated processing when the virtual computer control function is activated
The start address and the start instruction stored in that start address
The function of storing and the instruction of the start address are not defined in the interrupt detection processing function.
Processing to return to the execution of the original program by rewriting it
The interrupt processing function for registering an undefined instruction in the undefined instruction processing function
When it occurs, write back the contents of the address to the head instruction.
Processing for executing the interrupt processing in the virtual machine.
A machine-readable recording medium that records a program that causes a computer to realize an undefined command processing function for registering a process . 3. A program written in a high-level language
Virtual computation translated into virtual instruction sequences suitable for high-level language execution
Virtual computer instruction sequence storage means for storing a computer instruction sequence, and a virtual computer control processor for executing the virtual computer instruction sequence
Program storing means for storing a program, the virtual computer instruction sequence storing means, and the control program case.
The information is read from the storage means and the virtual instruction is interpreted and executed.
The virtual instruction interpretation / execution means for returning processing , and the start address of the repeated processing of the virtual instruction interpretation / execution means
Iterative process start address storing means for storing, and the start number stored in the repeat process starting address storage means
Repeating process head instruction storing means for storing a local instruction, and the virtual instruction interpretation executing means at the time of detecting an interrupt request from the user.
The state is saved temporarily rewriting the instruction of the start address stored in said iterate over the top address storage means in undefined instruction, the state of the virtual instruction interpretation execution means upon interruption by the shunting is not data Status of the interrupt detection processing means to be restored and the virtual instruction interpretation execution means when an undefined instruction is detected
Is temporarily saved, and the undefined instruction is the start address of the repeat processing.
If it occurs at the address stored in the storage means,
The instruction of the address is repeatedly stored in the head instruction storing means.
It is rewritten to the stored instruction and interrupt processing in the virtual machine is performed.
And the state of the virtual instruction interpretation execution means is undefined.
Instruction and interrupt processing means to be restored when a command is detected
And an interrupt processing device in a programming language processing system characterized by including