JP3463890B2 - Neural circuit mimic element - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neural circuit mimicking element for a neural computer which imitates a nerve cell.

[0002]

2. Description of the Related Art The aim of parallel processing of information is to imitate the function of a nerve cell (neuron), which is a basic unit of information processing of a living body, and further to make this "nerve cell mimicking element" a network, and to process information in parallel. This is a so-called neural network. Although it is easy to perform character recognition, associative memory, motion control, etc. in a living body, there are many things that conventional Neumann computers cannot easily achieve. Many attempts have been made to solve these problems by imitating the nervous system of the living body, particularly the functions peculiar to the living body, that is, parallel processing, self-learning and the like. Many of these attempts are carried out by computer simulation, and parallel processing is required to realize the original function, and for that purpose, the neural network must be implemented as hardware.

Among them, one realized by an electric circuit is disclosed in, for example, Japanese Patent Laid-Open No. 62-295188. However, this is basically an analog method. That is, the input / output amount is represented by a current value or a voltage value, and all internal calculations are performed in analog. In the case of such an analog system, it is difficult to operate with high accuracy and stability due to, for example, temperature characteristics and drift immediately after power-on. Also, for neural networks,
The number of amplifiers is required to be at least several hundreds, and nonlinear operation is performed, so stability is particularly required.

For this reason, the digital representation of the neural network is the communication technique ICD88-130.
As described above, this is an emulation of a conventional analog system, and the circuit is slightly complicated, such as using a counter.

In order to solve such a drawback, a digital neuron model, more specifically, as a kind of digital system, a pulse density type neuron model with a learning function for expressing a signal by a pulse train is disclosed in JP-A-4-549. Publication (basic of forward process), JP-A-4-111
No. 185 (Basic of learning process) and the like have been proposed by the applicant.

However, in the case of the proposed neuron model, for example, when the input is "0", the output is always "0", so that the input is "0". At the time of, it cannot correspond to the one that requires "1" as the output.

Therefore, the applicant of the present invention has proposed a method in which an offset signal is introduced into the neuron as a second input to enhance the processing capability, such as Japanese Patent Laid-Open No. 6356/1993.

On the other hand, when the logic operation of the signal represented by the pulse train is basically used as in the above-mentioned proposed neuron model, in order to update the value of the coupling coefficient by self-learning, the value of the coupling coefficient is changed to the pulse train. It is indispensable to express and memorize by, and in reality, a register or memory for the required pulse length is required. Here, when performing calculation with high accuracy, the pulse length must be long.
For example, considering a signal precision of about 7 bits, a random pulse train having a length of about 128 (= 2 ⁷ ) bits is required. Therefore, in order to store the value of the coupling coefficient as it is, a register or a memory of 128 bits for one coupling, or 128.n-bit length for a neuron having n inputs is required. Therefore, in order to realize a neuron having a large number of input signals by hardware using a digital logic circuit, it is necessary to connect these neurons in a mesh form in units of hundreds to thousands to form a neural network. It requires a huge number of registers or memories. As a result, the scale of hardware increases, which is a major obstacle in terms of manufacturing cost.

For this reason, the value of the coupling coefficient is stored as a binary number, and the value of the coupling coefficient is stored as it is in the pulse train representation by converting the value into the coupling coefficient represented by the pulse train at the time of calculation. A device in which the circuit scale can be made smaller than that in JP-A-5-165987 is proposed by the present applicant.

[0010]

[Patent Document 1] Japanese Patent Laid-Open No. 5-6
It is expected that the combination of the offset signal system disclosed in Japanese Patent No. 356, 356 and the binary storage of the coupling coefficient value and the pulse train conversion output system disclosed in Japanese Patent Laid-Open No. 5-165987 will be more effective. It However, there is a tendency that the circuit scale becomes large only by combining both types, which goes against the demand for miniaturization of the circuit scale.

[0011]

A neural circuit mimicking element according to claim 1, wherein the value of the coupling coefficient is set in the neural circuit mimicking element in which each neuron is coupled by synapse using a signal expressed by a pulse train as a signal transmission means. A first random number generating circuit including a memory for storing the binary number and a linear feedback shift register capable of selecting a generating polynomial, and a random number generated by the first random number generating circuit for the value of the coupling coefficient stored in the memory. A numerical value / pulse train conversion device equipped with a comparator that outputs a coupling coefficient represented by a pulse train in comparison with the above, and each of the synapses is provided with an offset signal generation for generating an offset input pulse train having a pulse density of "0.5". The offset signal generated by this offset signal generation circuit is the random number generated by the circuit and the linear feedback shift register. A second random number generation circuit which outputs for generating polynomial selection of the input pulse train generator and said first random number generating circuit in which is provided to each neuron.

According to a second aspect of the present invention, the neural circuit mimicking element has a second random number generating circuit including a linear feedback shift register in addition to the offset signal generating circuit in place of the neuron configuration of the neural circuit mimicking element according to the first aspect. And an offset input pulse train generation by the offset signal generation circuit and the first random number output from the second random number generation circuit as input
Each neuron is provided with a shift register for outputting the generator polynomial of the random number generator circuit.

A neural circuit mimicking element according to claims 3 and 4 is:
In each of the neural circuit mimicking elements according to claim 1 or 2, a logical product circuit for calculating and weighting a logical product of an input signal pulse train and a coupling coefficient pulse train for a neuron is added in each synapse, and is connected to each neuron. A logical sum circuit for calculating a logical sum of all synapses for the input signal pulse train weighted by the coefficient pulse train is added.

According to a fifth aspect of the present invention, the neural circuit mimicking element stores the absolute value of the coupling coefficient as a binary number in the neural circuit mimicking element in which each neuron is coupled by a synapse using a signal represented by a pulse train as a signal transmission means. A first random number generation circuit including a memory, a code memory for storing positive and negative signs of the coupling coefficient, a linear feedback shift register in which a generator polynomial is selectable, and a value of the coupling coefficient stored in the memory are stored in the first random number generation circuit. Numerical value / pulse train converter equipped with a comparator that outputs the coupling coefficient expressed by a pulse train by comparing it with the random number generated by the random number generation circuit, and calculates the logical product of the input signal pulse train for the neuron and the coupling coefficient pulse train. An AND circuit for performing weighting is provided for each synapse, and the input signal pattern weighted by the coupling coefficient pulse train is provided. A logical sum circuit for calculating the logical sum of all synaptic fraction in code-specific of the coupling coefficient for the scan sequence,
An offset signal generation circuit that generates an offset input pulse train having a pulse density of "0.5" and the logical sum result calculated for each sign of the coupling coefficient match each other, and the offset input pulse train is output, and when they do not match each other. An output selection circuit for outputting a pulse train resulting from the logical sum of the coupling coefficients having a positive sign, a random number generated by a linear feedback shift register, an offset input pulse train generation by the offset signal generation circuit, and the first random number generation circuit. And a second random number generation circuit for outputting the generator polynomial of (3) is provided in each neuron.

The neural circuit mimicking element according to claim 6 is a linear feedback shift register in addition to the OR circuit, the offset signal generating circuit and the output selecting circuit, in place of the neuron configuration in the neural circuit mimicking element according to claim 5. And a second random number generation circuit including the second random number generation circuit, and using a predetermined bit with the random number output from the second random number generation circuit as an input, the offset signal generation circuit generates the offset input pulse train and the first random number generation circuit. Each neuron is provided with a shift register for outputting a polynomial selection.

A neural circuit mimicking element according to claim 7 or 8,
In place of the memory and the code memory in each synapse in the neural circuit mimicking element according to claim 5 or 6, respectively, a memory for storing two kinds of coupling coefficient values indicating excitability and inhibitory property in a binary number, A code memory for storing positive and negative signs corresponding to excitability / inhibition of the coupling coefficient is provided.

[0017]

Various combinations of the offset input introduction method as shown in each of the neural circuit mimicking elements according to any one of claims 1 to 8 and the method of storing the value of the coupling coefficient in a binary number and converting it into a pulse train for calculation. In the above, a predetermined number of shift registers having the second random number generation circuit composed of the linear feedback shift register provided in each neuron or the output of the linear feedback shift register forming the second random number generation circuit as the input is determined in advance. The generated bits are shared for the generation of the offset input pulse train in the neuron and the generation polynomial selection of the first random number generation circuit in the synapse. Therefore, it is possible to prevent the circuit scale from increasing and combine them.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. The neural circuit mimicking element of the present invention uses a signal represented by a pulse train as a signal transmitting means, and further, the above-mentioned Japanese Patent Laid-Open No.
It is based on a combined configuration of the system of 6356 and the system of Japanese Patent Laid-Open No. 165987/1993. First, an outline of the algorithm will be described.

The input signal y _i to the neuron is, for example,
It is represented by a pulse train signal as shown in FIG. That is, the example of FIG. 2 represents “101101” = 4/6, and the signal is 4 “1” and 2 “0” in 6 synchronization pulses. That is, it is determined whether the input signal is "0" or "1" when the sync pulse rises or falls. At this time, it is desirable that the arrangement of "1" and "0" is random. The same applies to the output signal from the neuron.

On the other hand, the coupling coefficient W _ij indicating the degree of coupling between the neurons is also represented by a pulse train. The example of FIG. 3 is an expression representing “101010” = 3/6. In this case as well, it is determined whether the input signal is "0" or "1" at the rising or falling of the sync pulse, and also "1".
It is desirable that the arrangement of "0" and "0" is random.

The weighting of the input signal y _{i by} the coupling coefficient W _ij is realized by the logical product of these pulse trains, that is, y _i ∩W _ij ............ (1). According to the examples shown in FIGS. 2 and 3, the input signal weighted by the coupling coefficient is “10100”.
0 ″ = 2/6. Here, the pulse density resulting from such a logical product is approximately the product of the pulse density of the input signal y _{i and} the pulse density of the coupling coefficient W _ij , which is the analog type. It has a function similar to that of the coupling coefficient, and has a function closer to a product of numerical values as the signal sequence is longer and the arrangement of “1” and “0” is random. If the coupling coefficient pulse train is shorter than the input signal pulse train and there is no data to be read, the head of the data may be returned to and the reading may be repeated.

Next, the spatial sum corresponding to the synapse connecting the neurons is realized by a logical sum circuit for calculating the logical sum of the pulse trains. That is, since one neuron has multiple inputs, there are many "logical products of the input signal pulse train and the coupling coefficient pulse train" described above, and the logical sum of these is taken.
This logical sum operation corresponds to the sum calculation and the non-linear function (sigmoid function) part in the analog calculation. That is, when the pulse density is low, the pulse density of the logical sum thereof approximately matches the sum of the pulse densities. As the pulse density increases, the logical sum output gradually becomes saturated, so that it does not match the sum of the pulse densities, and nonlinearity appears. In the case of the logical sum, the pulse density does not become larger than 1 and does not become smaller than 0, and is a monotonically increasing function, which is approximately equivalent to the sigmoid function.

Here, the coupling has excitability and inhibition, but in the digital system, this is represented by the positive / negative sign of the coupling coefficient W _ij . Therefore, each connection is divided into two groups of excitatory connection and inhibitory connection according to the sign of the connection coefficient W _ij , and the logical sum is calculated for each group. The result of the logical sum of excitability groups thus obtained is y _Fj ,
Assuming that the logical sum result of the inhibitory groups is y _Ij , they are respectively expressed by equations (2) and (3).

[0024]

[Equation 1]

Alternatively, a coupling coefficient W _{ij (+)} representing excitability and a coupling coefficient W representing inhibitory property with respect to one input signal y _{i
Both ij (-)} and both are ANDed (y _i ∩W
_{ij (+)} , y _i ∩W _{ij (-)} ). Furthermore, the logical sum of these logical product results is taken. If the logical sum result of the excitatory group thus obtained is y _Fj and the logical sum result of the inhibitory group is y _Ij , they are respectively expressed by the equations (4) and (5).

[0026]

[Equation 2]

If the logical sum result y _Fj of the excitatory group and the logical sum result y _Ij of the inhibitory group thus obtained do not match, the result of the excitatory group is logically summed y _Fj to the neuron output. And That is, if the OR result y _Fj of the excitatory group is “0” and the OR result y _Ij of the inhibitory group is “1”, “0” is output, and conversely, the OR result of the excitatory group is output. If y _Fj is “1” and the OR result y _Ij of the inhibitory group is “0”, “1” is output.
On the other hand, when the logical sum result y _Fj of the excitatory group and the logical sum result y _Ij of the inhibitory group match, the separately prepared pulse density is “0.5” (or about “0.
5 ″) offset input pulse train signal y _Hj is used as a neuron output. That is, when expressed by a mathematical expression, the output signal y _j from the neuron is expressed by the mathematical expression (6).

[0028]

[Equation 3]

The network of neurons is hierarchical. If the entire network is synchronized, each layer can be calculated by the functions described above.

A configuration example based on the above algorithm will be described below. FIG. 4 shows a schematic configuration example of the entire hierarchical network, in which a large number of neurons 1 are appropriately connected by synapses 2. Here, the synapse 2 part is constructed as shown in FIG. 5 or FIG.
The part is constructed as shown in FIG.

First, FIG. 5 showing an example of the structure of the synapse 2 portion will be described. The input signal y _i is represented by a pulse train as described with reference to FIG. Further, the memory 3 for storing the value of the coupling coefficient W _ij as shown in FIG. 3 as a numerical value, specifically, an absolute value in binary number is provided. A numerical value → pulse train conversion circuit (numerical value / pulse train conversion device) 4 is connected to the read output side of the memory 3. here,
The memory 3 and the numerical value → pulse train conversion circuit 4 are connected by the number (bit width) n required to express the numerical value. Further, although not shown in the figure, signals necessary for reading and writing such as an output enable signal and a write enable signal are given to the memory 3. A logical product (ie, the logical product of the input signal y _i and the coupling coefficient W _ij converted into the pulse train representation by the numerical value → pulse train conversion circuit 4 (that is,
An AND gate (logical product circuit) 5 for calculating the equation (1) is provided. The output of the AND gate 5 has to be grouped according to whether the coupling is excitatory or inhibitory, but the output signals y _Fij and y _Iij to each group are previously _set.
It is more versatile to prepare and to switch the output. Therefore, a bit indicating whether the coupling is excitatory or inhibitory is stored in a grouping memory (code memory) 6 having a 1-bit configuration, and the information is used to switch by the switching gate circuit 7. The switching gate circuit 7 is composed of two AND gates 7a and 7b and an inverter 7c interposed at one input.

When it is not necessary to switch, they may be fixed. This means that it is equivalent to fixing the grouping memory 6 to either "0" or "1" in FIG.

For one input signal y _i , both a memory for the coupling coefficient W _{ij (+)} indicating excitability and a memory for the coupling coefficient W _{ij (-)} indicating inhibition are prepared. You may. FIG. 6 shows this example as another example of the configuration of the synapse 2 portion. In the figure, 3F is a memory for storing the value of a coupling coefficient representing excitability in a binary number (absolute value), and 3I is a memory for storing the value of a coupling coefficient representing an inhibitory property in a binary number (absolute value). 5, the numerical value → pulse train conversion circuits 4F and 4I are connected as in the case of FIG. An AND gate 5F for weighting the logical product of the coupling coefficients W _{ij (+)} and W _{ij (-)} pulse-converted by the numerical value → pulse train conversion circuits 4F and 4I and the input signal y _i , respectively.
5I is provided so that excitatory and inhibitory output signals y _Fij and y _Iij are separately obtained.

Next, FIG. 7 showing a configuration example of the neuron 1 portion will be described. First, for a pulse train of input signals (output signals from synapse 2) y _Fij , y _Iij weighted by the coupling coefficients W _{ij (+)} and W _{ij (-)} of the pulse train representation, excitability is calculated for the OR of all synapses. OR gates (logical sum circuits) 8F and 8I are provided for each group of inhibiting properties. That is, the OR gate 8F performs the logical operation of the equation (2) or (4), and the OR gate 8I performs the logical operation of the equation (3) or the equation (5). These O
A gate circuit (output selection circuit) 9 is connected to the output sides of the R gates 8F and 8I. The gate circuit 9 receives the offset input pulse train y _{Hj of the} pulse train expression having the pulse density of “0.5” from the offset input signal generator (offset signal generator) 10 as input, and performs the logical operation shown in the equation (6). It is something to do. Therefore, the two inverters 9
a and 9b, three AND gates 9c, 9d and 9e, and one OR gate 9f. Therefore, the OR gate 9f of the gate circuit 9 outputs the offset input pulse train y _Hj when the OR results y _Fj and y _Ij calculated for excitability and inhibitory property match each other.
When they do not match, a pulse train y _{Fj that} is the logical sum of the coupling coefficients having a positive sign is output.

Here, the numerical value → pulse train conversion circuit 4 (4
F and 4I are also the same), for example, as shown in FIG. 8, a random number generation device (first random number generation circuit) 11 and a binary combination coefficient value from the memory 3 are used as random numbers by this random number generation device 11. It is configured by a comparator 12 that compares and outputs the coupling coefficient represented by the pulse train to the AND gate 5 and the like.
The random number generation device 11, for example, as shown in FIG. 9, includes a 7-bit shift register 13 that generates a random number in synchronization with a reference clock, its most significant bit (b6) data, and the remaining appropriate bit data. Linear feedback shift register (LFSR) 1 with exclusive OR gate 14 which sequentially updates the least significant bit (b0)
It is composed of 5. As a result, 0- (2 ^ m-
1) A uniform random number up to (m is the number of bits of the shift register 13) can be obtained. There are a plurality of generator polynomials of the LFSR 15, and it is possible to obtain a more random random number sequence by appropriately switching the circuits. The comparator 12 compares the random number value generated by the random number generator 11 (LFSR15) with the coupling coefficient value from the memory 3, and outputs "1" when the data from the memory 3 is larger and "0" when the data is smaller. It is what is output. As a result, the pulse density becomes (data of memory 3/2 ^ m)
A coupling coefficient by the pulse train is obtained.

Since such an LFSR 15 (random number generator 11) exists for each synapse 2, each LFSR 15 (random number generator 11) of each synapse 2 generates a different random number sequence. Good. For this reason, each LFSR 15 is provided with a switch 16 for switching which bit of b0, b1, b4, b5 is input to the exclusive OR gate 14, and the generator polynomial can be switched.

Further, as shown in FIG. 1, each LFSR 15
, A generator polynomial selection shift register (second random number generator) 17 for determining which generator polynomial is selected is provided on the neuron 1 side separately from the LFSR 15 in the LFSR configuration. The register 17 is configured to use a random number. The shift register 17 for generating polynomial selection is LFS.
Similar to R15, the shift register 18 having a 7-bit structure that generates a random number in synchronization with the reference clock, the data of the most significant bit (b6) and the data of the remaining appropriate bits are input and the least significant bit (b0) is input. Exclusive O that updates sequentially
It has an LFSR configuration with an R gate 19, and a switching device 20 for selectively switching the multiple generation formulas is added.

To select the generator polynomial of the LFSR 15 by the random numbers generated by the generator polynomial selection shift register 17 as described above, bits (part of) of the shift register 18 in the generator polynomial selection shift register 17 are used. Well, or alternatively, this generator polynomial selection shift register 17
It is also possible to input the output of (1) to a multi-stage shift register and use (a part of) a predetermined bit of this shift register. Further, it is not always necessary to prepare one generator polynomial selection shift register 17 for each LFSR 15, and one generator polynomial selection shift register 17 may be provided for a plurality of LFSRs 15. In FIG. 1, a plurality of stages of shift registers 21 that receive the output of the generator polynomial selection shift register 17 are provided,
For example, LFSR1s of n synapses 2 of 2 bits each
5 also shows an example of distribution for selecting 5 polynomials.

The offset input signal generator 10 for generating and outputting the offset input pulse train y _Hj in the pulse train representation having the pulse density of “0.5” is basically a random number using the LFSR as in the case of the numerical value → pulse train conversion circuit 4. Can be generated based on. It is desirable that this random number sequence be independent of the random numbers on the side of the synapse 2, but if the offset input signal generator 10 is provided with a dedicated LFSR, the circuit scale becomes large. Therefore, in this embodiment, the generator polynomial selection shift register 17 provided for selecting the generator polynomial for the synapse 2 as described above is also used for generating the offset input pulse train y _{Hj in} the offset input signal generator 10. It is a thing.

As described above, the method of expressing a signal with a pulse density is useful not only for actual circuits but also for simulation on a computer. On the computer, the calculation is performed serially, but compared with the calculation using an analog value, only the binary logical calculation of "0" and "1" is performed, so that the calculation speed is significantly improved. Generally, the real number arithmetic operations require many machine cycles for one calculation, but the number of arithmetic operations is small. In addition, it is also easy to use low-level languages for high-speed processing when only logical operations are performed. Further, when implementing the above-described method, it is not necessary to make all of them into circuits, and some or all of them may be performed by software. Also,
The circuit configuration itself is not limited to the illustrated one, and may be replaced with another circuit having an equivalent logic, or may be replaced with a negative logic.

Now, a specific example of application to a self-learning character recognition device will be described. As shown in FIG. 4, the network is configured in a three-layer structure. The first layer has 256 pieces and the second layer has 20 pieces.
And the third layer has a structure of 5 neurons. Here, the neurons 1 are all connected to each other between the first and second layers and between the second and third layers. Handwritten characters were input to such a network and character recognition was performed. First, read the handwritten characters with a scanner, and as shown in FIG.
Mesh, and the mesh with letters is "1",
The non-existent mesh was set to "0". The 256 pieces of data were input to the network (first layer). Each of the five neurons 1 in the output layer is made to correspond to "1" to "5", and when the number is input, the output of the corresponding neuron 1 becomes "1" and the outputs of the other neurons 1 become "0". I learned to become. The learning was performed by using the Rummelhart backpropagation method (error backpropagation method) by computer simulation. A 7-bit LFSR 15 is used as the random number generator 11. Furthermore, this L
The FSR 15 was made accessible from the outside, and a random value was loaded as an initial value. Then, the learned coupling coefficient is multiplied by 127 (the LFSR is 7 bits),
Loaded into memory 3 for coupling coefficient. In this embodiment, since the input is "0" or "1", the input signal pulse train is always simple at L level or H level. Initially, if each coupling coefficient is set at random, the output result will not necessarily be a desired value. Therefore, the self-learning function is used to newly obtain each coupling coefficient, and this is repeated several times so that a desired output can be obtained. Here, the final output is connected to the LED via the transistor,
When the level is H, it is turned off, and when the level is H, it is turned on. Since the synchronization clock is set to 1000 kHz, the brightness of the LED looks different to the human eye according to the pulse density, and therefore the brightest LED part is the answer. A recognition rate of 100% was obtained for a sufficiently learned character.

[0042]

According to the neural circuit mimicking element of the invention described in claims 1 to 8, the offset input introduction method and the value of the coupling coefficient as shown in each claim are stored in a binary number and converted into a pulse train. In various combination configurations with a method for performing calculation, a random number generated by a second random number generation circuit that is a linear feedback shift register provided in each neuron, or a linear feedback shift register that configures the second random number generation circuit. Since a predetermined bit of the shift register having the output as an input is shared for the generation of the offset input pulse train in the neuron and the generation polynomial selection of the first random number generation circuit in the synapse, while preventing an increase in the circuit scale, It is possible to improve the processing capacity and facilitate the storage of the coupling coefficient.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a generator polynomial selection shift register showing an embodiment of the present invention.

FIG. 2 is a timing chart showing an input signal pulse train.

FIG. 3 is a timing chart showing a coupling coefficient pulse train.

FIG. 4 is a schematic diagram showing a network configuration example.

FIG. 5 is a block diagram showing an example of a configuration example of a synapse portion.

FIG. 6 is a block diagram showing another example of a configuration example of a synapse portion.

FIG. 7 is a logic circuit diagram showing a configuration example of a neuron portion.

FIG. 8 is a circuit diagram showing a configuration of a numerical value → pulse train conversion circuit.

FIG. 9 is a circuit diagram showing a configuration of a random number generation device.

FIG. 10 is an explanatory diagram showing an example of handwritten characters.

[Explanation of symbols]

1 neuron 2 synapse 3 memory 4 Numerical value / pulse train conversion means 5 AND circuit 6 code memory 8 OR circuit 9 Output selection circuit 10 Offset signal generation circuit 11 First random number generation circuit 12 Comparator 15 Linear feedback shift register 17 Second random number generation circuit 21 shift register

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-20292 (JP, A) JP-A-7-334478 (JP, A) Eguchi Hirotoshi, et al. Hardening, IEICE Technical Report, Japan, The Institute of Electronics, Information and Communication Engineers, October 25, 1990, Vol. 90, No. 273, p.63-70 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06G 7/60 G06N 3/06

Claims (8)

(57) [Claims] 1. In a neural circuit mimicking device in which neurons are connected by synapses using a signal represented by a pulse train as a signal transmission means, a memory for storing the value of a coupling coefficient in a binary number, and a linear generator for selecting a generator polynomial A first random number generation circuit composed of a feedback shift register and a value of the coupling coefficient stored in the memory are compared with a random number generated by the first random number generation circuit to output a coupling coefficient represented by a pulse train. A numerical value / pulse train converter equipped with a converter is provided at each of the synapses, and an offset signal generating circuit for generating an offset input pulse train having a pulse density of "0.5" and a random number generated by a linear feedback shift register are generated. Offset input pulse train generation by offset signal generation circuit and generation of the first random number generation circuit A neural circuit mimicking element characterized in that each neuron is provided with a second random number generation circuit for outputting for polynomial selection. 2. In a neural circuit mimicking element in which each neuron is connected by synapse using a signal expressed by a pulse train as a signal transmission means, a memory for storing the value of a coupling coefficient in a binary number, and a generator polynomial selectable linear A first random number generation circuit composed of a feedback shift register and a value of the coupling coefficient stored in the memory are compared with a random number generated by the first random number generation circuit to output a coupling coefficient represented by a pulse train. A second random number generation circuit including a linear feedback shift register and an offset signal generation circuit for generating an offset input pulse train having a pulse density of "0.5" by providing a numerical value / pulse train conversion device equipped with a converter at each synapse. And a random number output from the second random number generation circuit as an input to turn the off A neural circuit mimicking element, characterized in that each neuron is provided with a shift register for outputting an offset input pulse train by a set signal generating circuit and selecting the generator polynomial of the first random number generating circuit. 3. In a neural circuit mimicking element in which each neuron is connected by synapses using a signal expressed by a pulse train as a signal transmission means, a memory for storing the value of a coupling coefficient in binary number, and a generator polynomial selectable linear A first random number generation circuit composed of a feedback shift register and a value of the coupling coefficient stored in the memory are compared with a random number generated by the first random number generation circuit to output a coupling coefficient represented by a pulse train. And pulse train conversion device equipped with a multiplier and a logical product circuit for weighting the logical product of the input signal pulse train for the neuron and the coupling coefficient pulse train are provided in each synapse, and the input weighted by the coupling coefficient pulse train is provided. A logical sum circuit that calculates the logical sum of all synapses for the signal pulse train, and "0.5"
An offset signal generating circuit for generating an offset input pulse train having a pulse density of, and a random number generated by a linear feedback shift register for generating an offset input pulse train by this offset signal generating circuit and selecting a generator polynomial of the first random number generating circuit. A neural circuit mimicking element, characterized in that each neuron is provided with a second random number generating circuit for outputting to each neuron. 4. A neural circuit mimicking element in which neurons are connected by synapses using a signal represented by a pulse train as a signal transmission means, a memory for storing the value of a coupling coefficient in binary number, and a linear generator for selecting a generator polynomial. A first random number generation circuit composed of a feedback shift register and a value of the coupling coefficient stored in the memory are compared with a random number generated by the first random number generation circuit to output a coupling coefficient represented by a pulse train. And pulse train conversion device equipped with a multiplier and a logical product circuit for weighting the logical product of the input signal pulse train for the neuron and the coupling coefficient pulse train are provided in each synapse, and the input weighted by the coupling coefficient pulse train is provided. A logical sum circuit that calculates the logical sum of all synapses for the signal pulse train, and "0.5"
An offset signal generation circuit for generating an offset input pulse train having a pulse density of, a second random number generation circuit composed of a linear feedback shift register, and a predetermined bit with a random number output from the second random number generation circuit as an input. A neural circuit mimicking element, characterized in that each neuron is provided with a shift register which is used to generate an offset input pulse train by the offset signal generating circuit and to output for generating polynomial selection of the first random number generating circuit. 5. A neural circuit mimicking element in which neurons are coupled by synapses using a signal represented by a pulse train as a signal transmitting means, a memory for storing the absolute value of the coupling coefficient in a binary number, and a positive or negative sign of the coupling coefficient. A first random number generation circuit including a code memory for storing a code and a linear feedback shift register in which a generator polynomial is selectable, and a value of the coupling coefficient stored in the memory is a random number generated by the first random number generation circuit. A numerical value / pulse train conversion device including a comparator that outputs a coupling coefficient represented by a pulse train in comparison with the above, and a logical product circuit that calculates the logical product of the input signal pulse train for the neuron and the coupling coefficient pulse train to perform weighting. Is provided for each synapse, and the logical sum of all synapses is added to the input signal pulse train weighted by the coupling coefficient pulse train. Is calculated for each sign of the coupling coefficient, an offset signal generating circuit for generating an offset input pulse train having a pulse density of "0.5", and the logical sum result calculated for each sign of the coupling coefficient are Output pulse output circuit that outputs the offset input pulse train, and outputs a pulse train that is the logical sum of the coupling coefficient with a positive sign when they do not match, and a random number generated by a linear feedback shift register, which generates the offset signal. A neural circuit mimicking element, characterized in that each neuron is provided with a second random number generating circuit for generating an offset input pulse train by the circuit and selecting the generating polynomial of the first random number generating circuit. 6. A neural circuit mimicking element in which neurons are coupled by synapses using a signal represented by a pulse train as a signal transmission means, a memory for storing the absolute value of the coupling coefficient in a binary number, and a positive or negative sign of the coupling coefficient. A first random number generation circuit including a code memory for storing a code and a linear feedback shift register in which a generator polynomial is selectable, and a value of the coupling coefficient stored in the memory is a random number generated by the first random number generation circuit. A numerical value / pulse train conversion device including a comparator that outputs a coupling coefficient represented by a pulse train in comparison with the above, and a logical product circuit that calculates the logical product of the input signal pulse train for the neuron and the coupling coefficient pulse train to perform weighting. Is provided for each synapse, and the logical sum of all synapses is added to the input signal pulse train weighted by the coupling coefficient pulse train. Is calculated for each sign of the coupling coefficient, an offset signal generating circuit for generating an offset input pulse train having a pulse density of "0.5", and the logical sum result calculated for each sign of the coupling coefficient are The output input circuit outputs the offset input pulse train, and outputs a pulse train resulting from the logical sum of the coupling coefficients having a positive sign when they do not match, a second random number generation circuit including a linear feedback shift register, and The offset input pulse train generation by the offset signal generation circuit and the first by using a predetermined bit with the random number output from the second random number generation circuit as an input.
A neural circuit mimicking element characterized in that each neuron is provided with a shift register for outputting for generating polynomial selection of the random number generating circuit. 7. A neural circuit mimicking device in which neurons are connected by synapses using a signal represented by a pulse train as signal transmission means, and two types of coupling coefficient values indicating excitability and inhibitory property are stored in binary numbers. Memory, a code memory for storing positive and negative signs corresponding to excitability / inhibition of the coupling coefficient, a first random number generation circuit including a linear feedback shift register with selectable generator polynomials, and the memory are stored in the memory. A numerical value / pulse train converter having a comparator for comparing the value of the coupling coefficient with the random number generated by the first random number generation circuit and outputting the coupling coefficient represented by a pulse train; and an input signal pulse train for the neuron. A logical product circuit for calculating a logical product with the coupling coefficient pulse train to perform weighting is provided in each synapse, and weighted by the coupling coefficient pulse train. A logical sum circuit for calculating the logical sum of all synapses of the input signal pulse train by the sign of the coupling coefficient, an offset signal generation circuit that generates an offset input pulse train having a pulse density of "0.5", and the coupling coefficient An output selection circuit that outputs the offset input pulse train when the results of the logical sums calculated according to the signs of the two match, and outputs a pulse train that is the result of the logical sum of the coupling coefficient having a positive sign when the results do not match; and a linear feedback shift Each neuron is provided with a second random number generation circuit that outputs a random number generated by a register for the offset input pulse train generation by the offset signal generation circuit and the generation polynomial selection of the first random number generation circuit. A neural circuit mimicking element. 8. A neural circuit mimicking device in which neurons are coupled by synapses using a signal represented by a pulse train as a signal transmission means, and two types of coupling coefficient values indicating excitability and inhibitory property are stored as binary numbers. Memory, a code memory for storing positive and negative signs corresponding to excitability / inhibition of the coupling coefficient, a first random number generation circuit including a linear feedback shift register with selectable generator polynomials, and the memory are stored in the memory. A numerical value / pulse train converter having a comparator for comparing the value of the coupling coefficient with the random number generated by the first random number generation circuit and outputting the coupling coefficient represented by a pulse train; and an input signal pulse train for the neuron. A logical product circuit for calculating a logical product with the coupling coefficient pulse train to perform weighting is provided in each synapse, and weighted by the coupling coefficient pulse train. A logical sum circuit for calculating the logical sum of all synapses of the input signal pulse train by the sign of the coupling coefficient, an offset signal generation circuit that generates an offset input pulse train having a pulse density of "0.5", and the coupling coefficient An output selection circuit that outputs the offset input pulse train when the results of the logical sums calculated according to the signs of the two match, and outputs a pulse train that is the result of the logical sum of the coupling coefficient having a positive sign when the results do not match; and a linear feedback shift A second random number generation circuit composed of a register and an offset input pulse train generation by the offset signal generation circuit and a first random number output using the random number output from the second random number generation circuit as an input.
A neural circuit mimicking element characterized in that each neuron is provided with a shift register for outputting for generating polynomial selection of the random number generating circuit.