JP3450071B2 - PC card - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to P C card used as a semiconductor external storage card.

[0002]

2. Description of the Related Art As an external storage card for electronic equipment such as a personal computer (hereinafter referred to as a host system) and a card-shaped device for realizing an I / O function,
PC cards have become popular in recent years. Specification of P C card, in Japan JEIDA (Japan Electronic Industry Development Association), the standardized PCMCIA is a center in the United States has been promoted. In the present application, the guidelines Ver. 4.2, PC card ATA specification Release 1.02 compliant (hereinafter PC
-Use an ATA card. ) As an example.

A conventional ATA specification using a block erase type flash memory 6 (see FIG. 1) that can be erased only in data transfer units, that is, in blocks of sector units.
In the PC card, as shown in FIG. 10, whether or not the data stored in each block 14 in the flash memory 6 is invalid is turned on (ON) or off (O).
1-bit data invalid bit 20 notified by FF)
Is provided. A general write operation in the conventional PC card having the flash memory 6 configured as above will be described. As shown the flow of a write operation of the data in FIG. 11, when the data rewrite request from the host system occurs, P C card, first, confirm that there was a write request from the host system (step S1), the data invalid bit 20 of the block 14 in which the invalid data to be rewritten is stored is turned on (step S2), the update data is written to a new empty block (step S3), and the data invalid bit of the block is written. A method of writing data by turning off 20 (step S4) is generally used.

[0004]

When data is rewritten by the above-described method, if the number of rewritings increases, the data is stored in all writable blocks, and empty blocks are lost. In that case (step S5), the temporary write operation is interrupted during the write operation to search for an invalid block in which the data invalid bit is turned on (step S6), and the invalid data is erased (step S5). S7), it is necessary to secure a new empty block, but if the erase operation (steps S6 and S7) for securing the new empty block occurs, the host system cannot perform the write operation to the card during that time. The writing operation is delayed until the erasing operation is completed, which increases the writing time to the card. There has been a Utoyuu problem.

[0005] The present invention has been made to solve the above problems, the access request from the host system P C card when there is no "non-access state" a later predetermined time in the free block reserved Erase operation (hereinafter, background erase operation) is performed, and when there is a write request to the card from the host system, the data can be immediately written to the reserved empty block and the card is written. aims at obtaining a P C card to increase the speed of writing time to.

[0006]

According to a first aspect of the present invention, a nonvolatile semiconductor memory divided into a plurality of blocks for storing data, and an access indicating whether the host system is in an access state or not. Interface means for receiving a status signal, erasing means for starting an erasing operation for erasing unnecessary data stored in a block of a nonvolatile semiconductor memory when the access status signal is at a non-accessing state level, and erasing operation Interface during implementation
Access means receives an access status signal at the access status level.
And an interruption means for interrupting the erase operation when receiving
Is a P C card.

[0007]

[0008]

[0009]

[0010]

[0011] According to a second aspect of the invention, after interrupting the erase operation by interrupting means, when the interface unit receives the access status signal of the non-access state level, P C having a resuming means for resuming the erase operation was interrupted It's a card.

[0012]

[0013] The invention of claim 3 is provided in the interface unit, a P C cards with selector that can select whether the erase operation is performed by the erasing means during configuration.

[0014]

According to the first aspect of the present invention, while the host system is in the non-access state, an erasing operation for erasing unnecessary data stored in a block for securing an empty block in the nonvolatile semiconductor memory is executed. If there is a write request from the host system, the data is written in the reserved free block. Furthermore, erase
During the remote operation, the receiving means can access from the host system.
The erase operation is interrupted when a signal at the
Since an erasing operation is being carried out, a means for interrupting
When there is an access request from the host system
The erase operation is interrupted and the process is given priority.

[0015]

[0016]

[0017]

[0018]

According to the second aspect of the invention, since the resuming means for resuming the interrupted erase operation is provided, the erase operation is restarted when the host system becomes inaccessible again after the interruption. Let

[0020]

According to the third aspect of the present invention, since the selection unit for selecting whether or not the erasing operation by the erasing means is performed at the time of configuration is provided, the erasing operation can be performed by the user's selection at the time of configuration. Set whether to perform or not.

[0022]

EXAMPLES Example 1. An embodiment of the PC card according to the present invention will be described. P C card and the host system and the interface, as described above, is defined by the guidelines of the JEIDA, it has been standardized. Figure 1 shows the structure of P C card of the present invention. As shown in FIG. 1, the PC card 30
The, an interface control unit 1 for controlling the interaction with the host system 7, P C card 30
Configuration and Configuration section 2 for performing (initial setting operations for performing the various functions provided in the P C card 30), the register group 3
Doo is provided, they constitute performs standardized interface P C card 30 under the provisions of the JEIDA, an interface means for performing the configuration operations described below with respect to the interior of P C card 30 ing.

In the configuration section 2, PC
An attribute memory 15 (see FIG. 7) in which attribute information such as various functions of the card is written is provided. Further, in the register group 3, various registers such as a configuration register 8 and an ATA register 9 are provided. Configuration register 7
Is a register for functions to be performed in P C card 30 selected from various functions in the attribute memory 15 by the host system 7 during configuration is written, also, ATA register 9
Is a register for writing, for example, a command such as a write request from the host system 7 and an address parameter indicating an address in the flash memory 6 in which data is written. In addition, in the ATA register 9,
A status register (not shown) is provided, and by setting the D7 bit (BUSY bit) of the status register to "H", it is possible to indicate to the host system 7 that processing is being executed inside the card. it can.

Further, the P C card 30, the command processing and mosquito from the host system 7 - Microprocessor 4 is provided to perform the de control internally performs processing,
The internal bus 19 is connected to the above-mentioned interface means. As shown in the figure, the microprocessor 4 includes a ROM 22 storing an execution program of the microprocessor 4 and a nonvolatile memory having a plurality of blocks 14 (see FIG. 3) for storing data, which are divided into sectors. Memory 6 which is a flexible semiconductor memory
And an address conversion unit 17 for converting the address parameter written in the ATA register 9 into an actual address of the flash memory 6 such as 0000H to FFFFH are connected by an internal bus 19. A data buffer 5 for temporarily holding data input from the host system 7 is connected between the interface unit and the flash memory 6.

The operation will be described. In FIG. 1, first, the host system 7 includes the configuration unit 2
It reads the contents of the attribute memory 15 of the inner, based on its content, and select the function to be performed in P C card 30, writes it to the configuration register 8 in the register group 3, which is executable only its functions performing P C card 30 inside the initially set to. This operation is generally called configuration. After configuration, the signal from the host system 7 is P
The C-ATA specification interface signal is input to the interface control unit 1, the configuration unit 2, the register group 3, or the data buffer 5, and the signal causes the PC card 30 to execute the function set at the time of configuration. .

Next, a description will be given background erase and write operations to ensure the free block for writing data in the P C card 30 of this embodiment. The flow is shown in FIG. In the P C card of the ATA specification pursuant to the provisions of the JEIDA, the host system 7
Is "H" when requesting access such as write operation
Level card enable signal (-CE1, -CE2)
The interface control of P C card 30 part 1
To enter. While the host system 7 does not make an access request, a card enable signal (-CE1, -CE
2) is fixed to the “L” level (inactive), and is in a standby state until the next access request from the host system 7. Here, the card enable signal (-CE
1, -CE2) constitutes an access status signal indicating whether or not the host system 7 is in the access status.

First, the background erase operation will be described. As shown in the flow chart of FIG. 2, the host system 7 is in the non-access state (card enable signal (-
It is detected by the interface control unit 1 that CE1, -CE2) is "L" (inactive), and it is reported to the microprocessor 4 (steps S100 and S).
101). Based on the operation program stored in the ROM 22, the microprocessor 4 sets the status register of the ATA register 9 to "H" after a lapse of a predetermined time (step S102), and an invalid block storing invalid data which is unnecessary data. 14 (see FIG. 10) is detected (step S6), and the erase operation is started (step S).
7). As described above, in this embodiment, the microprocessor 4 performs the erase operation (steps S6 and S7).
The host system 7 waits for a predetermined time before starting the command processing. This is because the card enable signal (-CE1) is temporarily changed for another processing in the host system 7 while the host system 7 continuously requests the command processing. , -CE2) may be set to "L" (inactive) in order to prevent the background erase operation from being mistakenly started at that time. Here, the microprocessor 22 and the ROM 22 storing the operation program for the microprocessor 4 constitute an erasing means for starting the erasing operation when the host system 7 is in the non-access state.

Next, the write operation will be described. When the host system 7 is in the non-access state, the data in the invalid block 14 in the flash memory 6 is erased to reserve an empty block. Therefore, when a write request is issued from the host system 7, The interface control unit 1 detects it, reports it to the microprocessor 4, and when the microprocessor 4 confirms it (step S1), the data invalid bit 20 of the invalid block 14 in which invalid data is stored (see FIG. 10). ) Is turned on (step S2), the update data is immediately written to the empty block 14 secured during the non-access state (step S3), and the data invalid bit 20 of the block 14 in which the data is written is turned off (step S2). Step S4).

As described above, in this embodiment, while the host system 7 is in the non-access state, the PC card 3
Since 0 reserves the empty block 14 in the flash memory 6, when a write request is issued from the host system 7, data can be immediately written to the secured empty block 14. , The empty block 14 during the write operation as described in the conventional example.
It is not necessary to perform an erasing operation for ensuring the above, and it is possible to shorten the writing time and speed up the operation.

Example 2. In the above-described first embodiment, the example in which the 1-bit data invalid bit 20 indicating only the information indicating whether the block 14 of the flash memory 6 is invalid is provided for each block 14 has been described. In the example, as shown in FIG. 3, a block status confirmation area 10 is provided in the first several sectors in each flash memory 6, and a block area 11 composed of blocks 14 for storing data in the remaining memory space is provided. I decided to provide it. The block status confirmation area 10 stores block state data 12 and erase count data 13 for each block 14 in the block area 11. The block state data 12, the erase count data 13, and the erasable block 14 have a one-to-one correspondence. The block state data 12 and the erase count data 13 are alternately arranged as shown in the figure, and the arranged position is recognized by the microprocessor 4. The block state data 12 has four states (empty block,
(Invalid block, valid block, erasing), and the microprocessor 4 monitors the four states and writes the block state data 12. The erase count data 13 is incremented by 1 after the microprocessor 4 performs the erase operation. Here, the area for storing the block status data 12 in the block status confirmation area 10 constitutes a block status data storage means for storing data indicating the status of each block,
The area for storing the erase count data 13 in the block status confirmation area 10 constitutes erase count data storage means for storing data indicating the erase count of each block.

A flow chart showing the operation of the second embodiment is shown in FIG. In this flow, only step S102 and subsequent steps in FIG. 2 are described for simplification, but other operations are similar to those in FIG. When a predetermined time elapses after confirming that the host system 7 is in the non-access state, the microprocessor 4 sets the D7 bit (BUSY bit) of the status register in the ATA register 9 of the register group 3 to "H" ( Step S102). Next, the microprocessor 4 reads the contents of the block status data 12 in the block status confirmation area 10 provided for each block 14 in the flash memory 6, thereby detecting the invalid block 14 (step S201), and detecting the invalid block 14. The block having the smallest erase count is detected from the contents of the erase count data 13 among the invalid blocks 14 (step S202), and the erase operation is started for that block (step S203). After confirming the end of the erase operation (step S204), the microprocessor 4 again reads the contents of the block state data 12 in the block status confirmation area 10 (step S201), and the invalid block 1
The same erasing operation as described above is repeated until 4 is eliminated. Here, the microprocessor 4 and the ROM 22 storing the operation program thereof constitute detection means for reading data from the block state data storage means and the erase count data storage means and detecting a block to be erased. is doing.

Since the flash memory 6 is generally limited in the number of times data can be erased, if the same block 14 is repeatedly erased, that block 14 will be consumed and other blocks 14 will not be erased. Even if the flash memory 6 is not consumed, the entire flash memory 6 may become unusable. In this embodiment, as described above, the block status confirmation area 10 is set in the flash memory 6.
Since the block count data 13 indicating the state of each block 14 is stored together with the erase count data 13, the data of the block having the smallest erase count data 13 is erased. It is possible to prevent the erase operation from being performed many times, and it is possible to extend the life of the flash memory 6.
At the same time, the background erasing operation is performed in the non-access state in this embodiment as well, so that the same effect as that of the first embodiment can be obtained.

Example 3. In this embodiment, the access request (card enable signals (-CE1, -CE2) from the host system 7 is "H" (during the background erase operation by the microprocessor 4 shown in the first or second embodiment). The operation in the case of "activity") will be described.
The flow is shown in FIG. When there is an access request from the host system 7 (step S301), the microprocessor 4 receives the report from the interface control unit 1 and confirms it (step S302).
At that point, the microprocessor 4 gives an instruction to suspend the background erase operation (step S303). This instruction waits for the completion of the erase operation of the block 14 which is currently executing the background erase operation, and then waits for the next block 1.
4 does not shift to the background erasing operation and stops all the internal processing, and the microprocessor 4 sets the D7 bit (BUSY bit) of the status register in the ATA register 9 of the register group 3 to "L". (Step S304), wait for an access request from the host system 7, and give priority to the processing (step S30).
5). Here, the microprocessor 4 and the ROM 22 storing the operation program for the microprocessor 4 constitute an interrupting means for interrupting the erase operation when an access request is issued from the host system 7 during the erase operation.

In the above description, when an instruction to interrupt the background erase operation is issued (step S303), the background erase operation of the block 14 in which the erase operation is being executed at that time is not stopped and is ended. However, not limited to this case, the erase operation of the block 14 currently being erased is immediately interrupted,
When the processing of the access request from the host system 7 is finished and the erase operation is restarted, the block 14 in which the erase operation is interrupted may be continued to be erased.
In that case, the block state data 12 for the block 14 under the erasing operation remains "erasing" even if the erasing operation is interrupted. This is because the microprocessor 4 can detect the block 14 in which the erasing is suspended when resuming the erasing operation, and prohibit access to the block 14. For the method of restarting the erase operation, refer to Example 4 described later.

In this embodiment, as described above, when there is an access request from the host system 7 during the background erase operation performed in the non-access state of the host system 7 shown in the first or second embodiment. In this case, the background erasing operation is interrupted and the processing of the access request from the host system 7 is prioritized.
The same effect as that of the first or second embodiment can be obtained, and the access request from the host system 7 during the background erasing operation can be promptly performed, so that the system speed can be increased.

Example 4. In this embodiment, after the background erase operation by the microprocessor 4 is interrupted by the access request from the host system 7 in the third embodiment, the host system 7 is in the non-access state (-CE1 and -CE2 are inactive) again.
The operation in the case of will be described. The flow is shown in Figure 6.
Shown in. Host system 7 is in non-access state (-CE
When 1, -CE2 becomes inactive (step S40)
1), the interface control unit 1 reports it to the microprocessor 4 (step S402).
As in the case of the first embodiment, the microprocessor 4, after a predetermined time has passed, the D7 bit (BUSY bit) of the status register in the ATA register 9 of the register group 3.
Is set to "H" (step S403), and the background erase operation is restarted (step S404). Here, the microprocessor 4 and the ROM 22 storing the operation program for the microprocessor 4 restart the interrupted erase operation when the host system 7 becomes inaccessible again after interrupting the erase operation by the interrupting means. It constitutes a restarting means.

As a method of resuming the erase operation, when the background erase operation is interrupted in the third embodiment (step S303), only the erase operation for the block 14 in which the erase operation is being performed at that time is performed. Is to be completed, the next erase is performed in block 14
Search (step S6 in FIG. 2 or step S2 in FIG. 4)
01) and in Example 3 above,
In the case where even the erase operation for the block 14 which is being erased at the time of interruption is suspended,
The microprocessor 4 detects the block 14 in which the erasing is interrupted, that is, the block 14 in which the block state data 12 is "erasing", and the erasing operation is performed again for the block 14 (step S7 in FIG. 2 or FIG. Four
Step S203).

In this embodiment, the erasing operation interrupted by the access request from the host system 7 in the above-mentioned third embodiment is restarted after the host system 7 is put into the non-access state again. If there is an access request from the host system 7, the processing can be performed promptly, and like the first to third embodiments described above, the erase operation for securing a free block during the write operation is not required, and the system speed is increased. Can be promoted.

Example 5. In this embodiment, during non-access state of the host system 7, whether or not to implement the background erase operation for securing the free blocks in the interior of P C card 30, the host system 7, the configuration of the propriety It is something that can be selected at times. As shown in FIG. 7, the attribute memory 15 in this embodiment is composed of tuples 16, which are data blocks of variable length chain structure. Each tuple 16 has been written configurable various functions of P C card 30, respectively, the host system 7, select the tuples 16 to be set to function during configuration, the tuple 16 in the configuration register 8 Write the configuration index number. Here, the tuple 16 constitutes a selection unit that makes it possible to select whether or not to perform the background erasing operation by the erasing means at the time of configuration.

The operation of this embodiment will be described. First, in the attribute memory 15 of P C card 30,
A tuple 16 is prepared to enable the background erase operation for securing an empty block while the host system 7 is in the non-access state. The host system 7 is PC
Since one tuple 16 to be configured is selected when the card 30 is configured, the host system 7 determines here whether or not the background erase operation can be performed. Host system 7
Writes the configuration index number of the selected tuple 16 to the card configuration register 8 in the register group 3. The PC card 30 confirms the contents of the configuration register 8 selected by the host system 7, and performs the configuration operation inside the card.

In this embodiment, at the time of configuration, it is possible to select whether or not to perform the background erase operation for securing an empty block which is performed when the host system 7 is not accessed as described in the first embodiment. So
Since the user can select whether or not to perform the background erasing operation depending on the usage status, the convenience of the system can be improved.

Example 6. In this embodiment, the background erasing operation performed during the non-access state of the host system 7 shown in the first embodiment and the like can be executed even when a command is input from the host system 7. A flow showing the operation is shown in FIG. When the background erase operation start command is input from the host system 7 to the interface control unit 1 (step S501), the interface control unit 1 decodes it and reports it to the microprocessor 4 (step S502) to confirm the erase operation. It starts (step S503). The erase operation follows any one of the flows shown in the first to fourth embodiments. Here, the interface control section 1 constitutes a command input section for inputting from the host system 7 a command for the erasing means to start the erasing operation.

[0043] In this embodiment, as shown in the above Example 1 or the like, for P C card 30 automatically empty block ensuring after a predetermined time has elapsed if the host system 7 becomes non-access state performs background erase operation. Thus it is also possible to perform the erase operation by a command input from the host system 7, P C card 30 from between the host system 7 for some time
When it is not necessary to make an access request to the device, if the user inputs a command, it is possible to start the erase operation for securing a free block without waiting for a predetermined time.

In this embodiment, the background erasing operation can be started even by a command from the user, so that the user can use the PC card 3
If it is not necessary to make an access request to 0 for a while, the background erase operation can be started without waiting for a predetermined time if the background erase operation is executed by a command. And the efficiency can be further improved.

Example 7. In the second embodiment, the flash memory 6 is provided with a block status confirmation area 10 including block state data 12 and erase count data 13 for each block 14,
The host system 7 determines the block 14 to be background erased by reading the block status confirmation area 10 in the flash memory 6, but in this embodiment, as shown in FIG. RAM 18 connected to the internal bus 19
A block management table 18a is provided in the memory space for storing the data having the same contents as the data in the block status confirmation area 10 in order to increase the processing speed in the microprocessor 4. did.

In the second embodiment, when one block 14 to be background erased is determined, the erase operation is performed for it, and when the erase operation is completed, the next block 14 to be background erased is searched for. However, in this embodiment, the data of the block management table 18a provided in the RAM 18 are collectively searched to determine a plurality of blocks 14 to be erased, and the determined plurality of blocks 14 are sequentially searched. Since the erase operation can be successively performed, the erase time can be shortened. The microprocessor 4 rewrites the contents of the block status confirmation area 10 each time the erase operation is completed, and at the same time, the block management table 18a
Rewrite the contents of.

As shown in the fifth embodiment, the block management table 1 is stored in the attribute memory 15.
A tuple 16 that enables the search of the block 14 according to the content of 8a is provided, and the content of the block status confirmation area 10 is read to perform the background erasing operation, or the content of the block management table 18a is read and the background is read. The user may be allowed to select during the configuration whether the erase operation is performed.

Furthermore, the third and fourth embodiments described above may be combined with this embodiment so that when an access request is issued from the host system 7 in the middle of an erasing operation, the processing can be prioritized.

In the above Examples 1 to 7, JEID
Guideline Ver. 4.2, P
That conform to the C Card ATA specification Release1.02 (hereinafter referred to as PC-ATA card.) Things has been described as an example, not limited to this case, the present invention is also applicable to other P C Card You can Further, in the above-mentioned first to seventh embodiments, the flash memory is mentioned as an example of the non-volatile semiconductor memory, but the present invention is not limited to this case, and the present invention is not limited to such non-volatile semiconductor memory such as EEPROM and ROM. It can also be applied to volatile memory.

[0050]

According to the first aspect of the present invention, while the host system is in the non-access state, the erasing operation for erasing the unnecessary data stored in the block for securing the empty block in the non-volatile semiconductor memory. The operation is performed in advance, and when there is a write request from the host system, the data is written in the reserved empty block. Therefore, the erase operation for securing the empty block during the write operation. It is not necessary to perform the above operation, and the write operation time can be shortened and the speed can be increased accordingly. During the erase operation, the interface
Access to the access level from the host system.
When the signal is received, the interruption means to interrupt the erase operation
Since it has been prepared, the host system
Erase operation is interrupted when there is an access request from the system
I decided to prioritize that process, so the system
The effect of being able to improve the efficiency of
It

[0051]

[0052]

[0053]

[0054]

According to the second aspect of the present invention, since the resuming means for resuming the interrupted erasing operation is provided, if the host system becomes inaccessible again after the interruption, the erasing operation is performed. Since it is restarted, if there is an access request from the host system, it will promptly do it, and after that, when it becomes a non-access state, the erase operation to secure the empty block will start, so the system speed is high. The effect is that it can be realized.

[0056]

According to the third aspect of the present invention, since the selection unit is provided for selecting whether or not the erasing operation is performed by the erasing means at the time of configuration, the erasing operation is performed by the user's selection at the time of configuration. Since it is possible to set whether or not it is possible to make a selection according to the user's usage requirements, it is possible to improve convenience.

[Brief description of drawings]

1 is a block diagram showing the structure of P C card in Examples 1-6 of the present invention.

2 is a flowchart showing the operation of the P C card in Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a structure of a flash memory according to a second embodiment of the present invention.

4 is a flowchart showing the operation of the P C card in the second embodiment.

5 is a flowchart showing the operation of the P C cards in the third embodiment of the present invention.

6 is a flowchart showing the operation of the P C card in Embodiment 4 of the present invention.

7 is a diagram showing the structure of attribute memory of P C card in a fifth embodiment of the present invention.

8 is a flowchart showing the operation of the P C card in a sixth embodiment of the present invention.

9 is a block diagram showing the structure of P C card in the seventh embodiment of the present invention.

FIG. 10 is a diagram showing a structure of a flash memory in a conventional PC card.

FIG. 11 is a flowchart showing the operation of a conventional PC card.

[Explanation of symbols]

1 interface control part, 2 configuration part, 3 register group, 4 microprocessor, 6 flash memory, 10 block status confirmation area, 15 attribute memory, 16 tuple, 18
RAM, 18a block management table, 22 RO
M.

Claims (3)

(57) [Claims] 1. A semiconductor memory divided into a plurality of blocks for storing data, interface means for receiving an access status signal from a host system indicating whether or not the access status is present, and the access status signal is At the access status level,
Erase means for starting an erase operation for erasing unnecessary data stored in the block of the semiconductor memory, and the interface means for accessing during the erase operation.
Cleared when an access status signal at the access status level is received
And an interruption means for interrupting the operation.
PC card. 2. The resuming means for resuming the suspended erase operation when the interface means receives an access state signal of a non-access state level after the erase operation is suspended by the suspending means. P C card according to claim 1, wherein. 3. The interface means is provided,
P C card according to claim 1 or 2, further comprising a selection unit that can select whether the erase operation is performed by the erasing means during configuration.