JP3442331B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device manufactured by an SOI-CMOS process.

[0002]

2. Description of the Related Art Currently, as a semiconductor integrated circuit, a CMOS-IC (Compr) which is excellent in low power consumption and high integration
elementary Metal Oxide Semi
conductor-Integrated Circ
UIT) is the mainstream, but SOI (Silicon-O) is used to realize even lower power consumption and higher current gain.
A technique called "n-Insulator" has been used.

CMOS using SOI technology (hereinafter referred to as "S
OI-CMOS ". ) Structure, as will be described later, the bottom and side surfaces of the device are LOCOS (LOCal O
xidation of Silicon) oxide film. Since the bottom surface is also insulated from the substrate by the oxide film, the junction leakage current can be reduced, and the delay of the circuit operation due to the parasitic capacitance is eliminated due to the reduction of the junction capacitance, resulting in low power consumption and high speed driving. Can be compatible with both.

By the way, in the case of the SOI-CMOS structure, there is a problem that the electrostatic breakdown preventing protection circuit conventionally used cannot be used as it is. Surge resistance per element unit area in the SOI-CMOS structure is CMOS
This is because it is lower than in the case of the structure. The reason for this will be described below. In the following description, "P
The "channel MOS" is referred to as "PMOS", and the N-channel MOS is referred to as "NMOS".

As shown in FIG. 14, a semiconductor device having an electrostatic breakdown prevention circuit has PMOSs connected in series.
Output transistor 50 and NMOS output transistor 5
For 1, the PMOS protection transistor 52 and the NMOS protection transistor 53 are connected in series in parallel with these. Note that reference numeral 100 in FIG. 14 represents an output terminal, reference numeral 200 represents a power supply terminal, and reference numeral 300 represents a ground terminal for external connection. In this way, by connecting the output transistor and the protection transistor in parallel, the electrostatic surge that has entered from the outside is shunted to the output transistor and the protection transistor, thereby ensuring a predetermined resistance to the electrostatic surge.

Regarding the portion where the NMOS output transistor 51 and the NMOS protection transistor 53 of the conventional output protection circuit are formed, the CMOS structure and the SOI-CMOS are provided.
The difference from the structure will be described with reference to FIGS.

As shown in FIG. 15, the conventional CMOS structure has a source 51s and a drain 51d of an NMOS output transistor 51, an N-type impurity diffusion region corresponding to the source 53s and a drain 53d of an NMOS protection transistor 53, and an N-type impurity diffusion region. A P-type substrate 60, which is a channel region sandwiched between the type impurity diffusion regions, and a gate electrode 5 formed with a thin gate oxide film 74 sandwiched so as to cover the upper portion of the channel region.
It is composed of 1 g and 53 g.

Source 5 of NMOS output transistor 51
Side surfaces of the 1s and the drain 51d are separated from an adjacent element by the oxide film 70. Similarly, NMO
Source 53s and drain 5 of S protection transistor 53
The side surface of 3d is separated from the adjacent element by the oxide film 70. NMOS output transistor 51 and NM
The entire P-type substrate 60 below the channel region of the OS protection transistor 53 is connected.

On the other hand, in the conventional SOI-CMOS structure, as shown in FIG. 16, the structure of the NMOS transistor itself is the same as the CMOS structure, but the bottom surfaces of the NMOS output transistor 51 and the NMOS output transistor 53 are also made of an oxide film. It is covered with 80. Therefore, unlike the CMOS structure, the P-type substrate 60 under the channel region is also completely separated from the adjacent element.

NMOS output transistor 51 and NMOS
The reason why the protection transistor 53 is destroyed by the electrostatic surge is that the PN junction of the drain or the source is physically damaged by the Joule heat generated by the surge current, and the Joule heat generated at the PN junction interface causes heat. The more difficult the structure is to diffuse, the more likely it is to be destroyed.

In the case of the CMOS structure, as shown in FIG. 15, since the entire substrate itself is connected, Joule heat generated at the PN junction interface of the source or drain is apt to cause thermal diffusion, whereas the SOI- In the case of the CMOS structure, as shown in FIG. 16, the bottom surface portion of the protection transistor is also separated by the oxide film, so that the Joule heat generated at the PN junction interface hardly causes thermal diffusion. Therefore, P
The critical temperature at which the N-junction breaks is easily reached, and the N-junction breaks more easily than the CMOS structure. For the above reasons
In the case of the SOI-CMOS structure, the resistance to electrostatic surge per unit area is extremely reduced.

[0012]

The present invention has been made in view of the above problems and other problems of the conventional semiconductor device, and an object of the present invention is to provide an SOI-CMO.
In the S process, while suppressing the increase of the protection circuit area,
It is possible to achieve the same level of electrostatic breakdown resistance as before.
It is to provide a new and improved semiconductor device.

[0013]

According to a first aspect of the present invention, in a semiconductor device manufactured by an SOI-CMOS process, a first power supply terminal for supplying a first power supply potential and a first power supply terminal are provided. 1st which outputs the power supply potential of 1
A conductive type output transistor, a low-concentration impurity diffusion region of a first conductivity type having high-concentration impurity diffusion regions formed at both ends, and a gate electrode formed above the low-concentration impurity diffusion region via a gate oxide film. A first protective element and an output terminal, the source terminal of the first conductivity type output transistor is connected to the first power supply terminal, and the drain terminal of the first conductivity type output transistor is the first protection element. The high-concentration impurity diffusion region of the element is connected to one end, and the high-concentration impurity diffusion region of the first protection element is connected to the output terminal at the other end.
A semiconductor device is provided in which the gate electrode of the first protection element is connected to the first power supply terminal.

Generally, the output transistor is easily destroyed when an electrostatic surge corresponding to the opposite direction of the PN junction of the drain enters. According to the above configuration, since the first protection element that behaves as an insulating element against an electrostatic surge, that is, the low-concentration impurity diffusion region, the high-concentration impurity diffusion regions at both ends, and the gate electrode are provided, an output is generated from the electrostatic surge that is easily broken. The transistor can be effectively protected.

In the first protection element, the gate is always fixed to the ground potential during the normal operation, so the first protection element is the first protection element.
The conductivity type low concentration diffusion region maintains the first conductivity type and serves as a resistor. Although this resistor serves as a limiting resistor of the output current for the first conductivity type output transistor, the resistance value can be set by two design elements, that is, the resistance width and the resistance length. Since the resistance value can be designed to be as low as a level that does not cause a problem in actual operation, the decrease in output current during actual operation can be suppressed to a slight extent.

Further, as described in claim 2, one end of the high-concentration impurity diffusion region of the first protection element and the high-concentration impurity diffusion region forming the drain terminal of the output transistor of the first conductivity type are integrated. Is preferably formed on the substrate.

According to this structure, the high-concentration impurity diffusion region at one end of the first protection element and the drain of the output transistor are integrally formed in the same impurity diffusion region, so that the metal wiring connecting them is not required. It is possible to reduce the pattern area.

According to a third aspect of the present invention, the semiconductor device has a first-conductivity-type protection transistor whose gate is always off, and a first-conductivity-type transistor having high-concentration impurity diffusion regions at both ends. And a second protective element including a low-concentration impurity diffusion region and a gate electrode formed above the low-concentration impurity diffusion region via a gate oxide film,
The source terminal of the first conductivity type protection transistor is connected to the first power supply terminal, and the drain terminal of the first conductivity type protection transistor is connected to one end of the high-concentration impurity diffusion region of the second protection element. The other end of the high-concentration impurity diffusion region of the second protection element may be connected to the output terminal, and the gate electrode of the second protection element may be connected to the first power supply terminal.

According to this structure, the electrostatic surge current that has entered the output terminal is shunted between the protection transistor side and the output transistor side, and the protection transistor side is also connected with the same protection means as the output transistor side in series. Therefore, it is possible to prevent the protection transistor side from being destroyed first.

Further, as described in claim 4, one end of the high-concentration impurity diffusion region of the first protection element, a high-concentration impurity diffusion region forming a drain terminal of the first conductivity type output transistor, and One of the high-concentration impurity diffusion regions of the second protection element and at least two high-concentration impurity diffusion regions of the high-concentration impurity diffusion regions forming the drain terminal of the first conductivity type protection transistor are formed on one substrate. Preferably.

According to this structure, for example, the high-concentration impurity diffusion region at one end of the second protection element and the drain of the protection transistor are integrally formed in the same impurity diffusion region, so that the metal wiring connecting them can be formed. It becomes unnecessary and the pattern area can be reduced.

According to the present invention, the second power supply terminal for supplying the second power supply potential, the second protection type second protection transistor whose gate is always off, and the high-concentration impurity at both ends. A third protection element including a second-conductivity-type low-concentration impurity diffusion region in which a diffusion region is formed and a gate electrode formed above the low-concentration impurity diffusion region through a gate oxide film, The source terminal of the two-conductivity-type protection transistor is connected to the first power supply terminal, and the drain terminal of the second-conductivity-type protection transistor is connected to one end of the high-concentration impurity diffusion region of the third protection element. The gate terminal of the conductivity type protection transistor is connected to the second power supply terminal, the other end of the high-concentration impurity diffusion region of the third protection element is connected to the output terminal, and the gate electrode of the third protection element is Second power supply terminal It may be configured to be connected.

According to this structure, the second protection transistor of the second conductivity type is provided with the third protection element, and when the first protection element and the second protection element behave as the insulation elements, the third protection element is provided. The third protection element behaves as a resistance element, and when the first protection element and the second protection element behave as resistance elements, the third protection element behaves as an insulating element. This makes it possible to obtain good resistance to electrostatic surges against both the positive electrode electrostatic surge and the negative electrode electrostatic surge. In the second conductivity type protection transistor, the gate is connected to the second power supply terminal,
Since it is always off, it has no effect during actual operation.

Further, as described in claim 6, one end of the high-concentration impurity diffusion region of the first protection element, a high-concentration impurity diffusion region forming a drain terminal of the first conductivity type output transistor, and A high-concentration impurity diffusion region of the second protection element, a high-concentration impurity diffusion region forming a drain terminal of the first conductivity type protection transistor, an end of a high-concentration impurity diffusion region of the third protection element, Of the high-concentration impurity diffusion regions forming the drain terminal of the two-conductivity-type protection transistor, at least two high-concentration impurity diffusion regions are preferably formed on one substrate. According to this structure, for example, the high-concentration impurity diffusion region at one end of the third protection element and the drain of the protection transistor are integrally formed in the same impurity diffusion region, so that the metal wiring connecting them is not required. It is possible to reduce the area.

Furthermore, as in the semiconductor device according to claim 7, the first power supply terminal and the output terminal may be connected via a diode. At this time, the forward barrier voltage of the diode is set higher than the voltage applied between the first power supply terminal and the output terminal in the normal operation so that the current does not normally flow through the diode. With this configuration, when an electrostatic surge enters the output terminal, a current flows between the output terminal and the first power supply terminal through the diode, and the entered electrostatic surge disappears. Therefore,
The output transistor can be protected more effectively from electrostatic surge.

[0026]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of a semiconductor device according to the present invention will be described in detail. In the present specification and the drawings, constituent elements having substantially the same functional configuration are designated by the same reference numerals, and duplicate description will be omitted.

(First Embodiment) A semiconductor device 1000 according to the first embodiment will be described with reference to FIGS. 1 is a circuit diagram, FIG. 2A and FIG.
2B is a plan view, and FIG. 3 is a sectional view taken along line XX ′ in FIG.

As shown in FIG. 1, the semiconductor device 1000 includes a ground terminal 300 for external connection, an NMOS output transistor 7, and N-type low-concentration impurities in which high-concentration impurity diffusion regions 4 and 6 are formed at both ends. A first protection element A including a gate electrode 5g formed on the diffusion region 5 and the low-concentration impurity diffusion region 5 via a gate oxide film, and an external connection output terminal 100 are provided. In this embodiment, an example in which the output transistor is an NMOS transistor will be described, but the present invention is not limited to such a case. The substantially similar concept can be applied even when the output transistor is a PMOS transistor.

The source terminal 7s of the NMOS output transistor 7 is connected to the external connection ground terminal 300 by the connection line 3, the drain terminal 7d is connected to one end 6 of the high-concentration impurity diffusion region of the first protection element A, and the gate The terminal 7g is connected to the output drive signal line 8. First protection element A
The other end 4 of the high-concentration impurity diffusion region is connected to the external connection output terminal 100 by the connection line 1. The gate electrode 5g of the first protection element A is connected to the external connection ground terminal 300 by the connection line 3.

As shown in FIGS. 2A and 3, the first protection element A and the NMOS output transistor 7 are SO.
It is provided on a substrate having an I-CMOS process structure.
One end 6 of the high-concentration N-type impurity diffusion region of the first protection element A
And the drain 7d of the NMOS output transistor 7 are integrally formed in the same impurity diffusion region as shown in FIG. In FIG. 2, reference numerals 101 to 105 represent the first layer metal, reference numerals 106 to 107 represent polysilicon,
Reference numerals 109 to 110 represent N-type impurity diffusion layers, and reference numeral 1
Reference numeral 23 represents the second layer metal, and reference numerals 113 to 116 are the first.
A layer metal-diffusion interlayer connection hole is represented by reference numerals 117 to 118
Represents the first-layer metal-polysilicon connection hole, and the reference numeral 1
19 to 120 represent second-layer metal-first-layer metal connection holes, reference numeral 121 represents a low-concentration N-type impurity diffusion region,
Reference numeral 121 represents a low concentration P-type impurity diffusion region.

The upper portion of the low concentration impurity diffusion region 5 is shown in FIG.
5, the gate electrode 5g is arranged in parallel with the high concentration impurity diffusion region 4 or the high concentration impurity diffusion region 6 so as to completely cross the low concentration impurity diffusion region via the gate oxide film 74. The first protection element A composed of the low-concentration impurity diffusion region 5, the high-concentration impurity diffusion regions 4 and 6 and the gate electrode 5g operates as a protection device for the NMOS output transistor 7. Incidentally, reference numeral 7 in FIG.
Reference numeral 0 represents a field oxide film, reference numerals 71 to 72 represent interlayer insulating films, reference numeral 73 represents a surface protective film, reference numeral 80 represents a buried oxide film, and reference numeral 90 represents a P-type substrate.

The operation of the semiconductor device 1000 having the above structure will be described with reference to FIGS. In the following, the first protection element A when the negative electrode electrostatic surge is applied
Will be described with reference to FIG. 4, and the first protection element A when the positive electrode electrostatic surge is applied will be described with reference to FIG.

FIG. 4 is a schematic diagram showing a section taken along the line YY ′ in FIG. 2 when the negative electrode electrostatic surge enters the output terminal 100. When the negative electrode electrostatic surge enters the output terminal 100, as shown in FIG.
Since a relatively positive voltage is applied to the gate 5g connected to, the low-concentration impurity diffusion region 5 under the gate 5g becomes an N-type accumulation layer, and the high-concentration impurity diffusion region 4 causes Since the diffusion region 6 is integrated into the N type, it functions as a resistor.

On the other hand, when a positive electrostatic surge enters the output terminal 100, a relatively negative voltage is applied to the gate 5g connected to the external connection ground terminal 300, as shown in FIG. As a result, the low-concentration impurity diffusion region 5 under the gate 5g is turned into a P-type inversion layer, and the N-type high-concentration impurity diffusion region 4 and the high-concentration impurity diffusion region 6 are electrically insulated.

As described above, the low-concentration impurity diffusion region 5 connected in series between the output line 1 and the NMOS output transistor 7 behaves as a resistance element against a negative electrostatic surge and acts as a positive electrostatic surge. On the other hand, it behaves as an electrically insulating element. Therefore, the external connection output terminal 1
00 and the external connection ground terminal 300, a surge current flows through the NMOS output transistor when a negative electrostatic surge enters, and a positive surge does not easily flow when a positive electrostatic surge enters.

Generally, the NMOS output transistor is easily destroyed when an electrostatic surge of the positive electrode corresponding to the opposite direction of the PN junction of the drain enters. According to the semiconductor device 1 of the present embodiment, since the protection element A that acts as an insulating element against the positive electrode electrostatic surge is provided, the NMOS output transistor 7 is effectively protected from the positive electrode electrostatic surge that is easily damaged. can do.

Further, in the protective element A, during normal operation, the gate 5g is always fixed to the ground potential, so that the low concentration impurity diffusion region 5 maintains the N type and serves as a resistor. Although this resistor serves as a limiting resistor for the output current for the NMOS output transistor 7, the resistance value can be set by two design elements, that is, the resistance width and the resistance length, and the resistance value can be reduced by widening the resistance width and shortening the resistance length. Since it can be designed to be suppressed to a level that does not cause a problem in actual operation, the decrease in output current during actual operation can be suppressed to a slight extent.

Further, as shown in FIG. 2B, the high-concentration N-type impurity diffusion region 6 and NM at one end of the first protection element A are formed.
Since the drain 7d of the OS output transistor 7 and the drain 7d are integrally formed in the same impurity diffusion region, it is possible to reduce the pattern area by eliminating the need for metal wiring connecting them.

(Second Embodiment) A semiconductor device 2000 according to a second embodiment is shown in FIG. 6, FIG. 7 (A), and FIG.
This will be described with reference to (B). 6 is a circuit diagram, FIG.
7A and 7B are plan views. The semiconductor device 2000 is characterized in that it has a second protective element B in addition to the first protective element A.

As shown in FIG. 6, the semiconductor device 2000 includes a ground terminal 300 for external connection, an NMOS output transistor 7, and N-conductivity type low-concentration regions having high-concentration impurity diffusion regions 4 and 6 formed at both ends. A first protection element A including an impurity diffusion region 5 and a gate electrode 5g formed above the low concentration impurity diffusion region 5 via a gate oxide film, and an external connection output terminal 100 are provided. Semiconductor device 1
Common with 000.

Further, in the semiconductor device 2000, the NMOS protection transistor 12 whose gate is always off, the N-type low-concentration impurity diffusion region 10 and the low-concentration impurity diffusion region 10 in which the high-concentration impurity diffusion regions 9 and 11 are formed at both ends. Area 1
And a second protection element B formed of a gate electrode 10g formed on the upper part of 0 through a gate oxide film.

The source terminal 7s of the NMOS output transistor 7 is connected to the external connection ground terminal 300 by the connection line 3, the drain terminal 7d is connected to one end 6 of the high-concentration impurity diffusion region of the first protection element A, and the gate The terminal 7g is connected to the output drive signal line 8. First protection element A
The other end 4 of the high-concentration impurity diffusion region is connected to the external connection output terminal 100 by the connection line 1. The gate electrode 5g of the first protection element A is connected to the external connection ground terminal 300 by the connection line 3.

The source terminal 12s and the gate terminal 12g of the NMOS protection transistor 12 are connected to the external connection ground terminal 300 by the connection line 3, and the drain terminal 12d is connected to one end 11 of the high-concentration impurity diffusion region of the second protection element B. It is connected. The other end 9 of the high-concentration impurity diffusion region of the second protection element B is connected to the external connection output terminal 1 by the connection line 1.
Connected to 00. The gate electrode 10g of the second protection element B is connected to the external connection ground terminal 300 by the connection line 3.

As shown in FIG. 7A, the first protection element A and the NMOS output transistor 7 and the second protection element B and the NMOS protection transistor 12 are SOI-
It is integrally provided on a substrate having a CMOS process structure. In FIG. 7A, reference numerals 101 to 105 represent first layer metals, reference numerals 106 to 107 represent polysilicon, reference numerals 109 to 112 represent N-type impurity diffusion layers, and reference numeral 123 represents a second layer. Reference numeral 113 to 118 represents a metal, and reference numerals 117 to 118 represent first layer metal-diffusion interlayer connection holes.
Reference numeral 18 denotes a first layer metal-polysilicon connection hole, reference numerals 119 to 120 denote second layer metal-first layer metal connection holes, reference numeral 121 denotes a low concentration N-type impurity diffusion region, and reference numeral 122. Indicates a low concentration P-type impurity diffusion region.

Above the low-concentration impurity diffusion region 10, the high-concentration impurity diffusion region 9 or the high-concentration impurity diffusion region 11 is formed.
In parallel with the above, a gate electrode 10g is arranged via a gate oxide film so as to completely cross the low-concentration impurity diffusion region, and the gate electrode 10g is connected to the ground line 3.
Such an arrangement is substantially the same as that of the gate electrode 3g shown in FIG. The second protection element B composed of the low-concentration impurity diffusion region 10, the high-concentration impurity diffusion regions 9 and 11 and the gate electrode 10g operates as a protection element of the NMOS protection transistor 12.

According to the semiconductor device 2000 having the above structure, the NMOS protection transistor 12 provided for alleviating the surge current flowing per unit area of the NMOS output transistor 7 is destroyed as compared with the first embodiment. The electrostatic surge current can be effectively shunted between the NMOS protection transistor 12 and the output transistor 7 side while being prevented by the same protection element B.

The electrostatic surge current that has entered the output terminal is divided into the protective transistor side and the output transistor side,
Moreover, since the same protection means as the output transistor side is connected in series to the protection transistor side, the protection transistor side is not destroyed first. In the present embodiment, when the surge current per unit area flowing through the output transistor 7 exceeds the breakdown current value, the protection transistor 12 is installed in parallel in order to alleviate the breakdown current value. It can be prevented from being destroyed.

Further, the first protection element A and the NMOS output transistor 7 and the second protection element B and the NMOS protection transistor 12 are as shown in FIG. 7B.
Since it is integrally formed on the substrate having the SOI-CMOS process structure, it is possible to reduce the pattern area because the metal wiring connecting the both is unnecessary.

(Third Embodiment) A semiconductor device 3000 according to a third embodiment will be described with reference to FIGS. 8 is a circuit diagram, FIG. 9 is a plan view, and FIG. 10 is a sectional view taken along the line ZZ 'in FIG. The semiconductor device 3 is characterized in that it further includes a third protection element C in addition to the first protection element A and the second protection element B.

As shown in FIG. 8, the semiconductor device 3000 includes an N-type low-concentration grounding terminal 300 for external connection, an NMOS output transistor 7, and high-concentration impurity diffusion regions 4 and 6 formed at both ends. The first protection element A is formed of an impurity diffusion region 5 and a gate electrode 5g formed above the low concentration impurity diffusion region 5 via a gate oxide film, and an external connection output terminal 100.

In the semiconductor device 3000, the NMOS protection transistor 12 whose gate is always off, the N-type low-concentration impurity diffusion region 10 and the low-concentration impurity diffusion region 10 in which the high-concentration impurity diffusion regions 9 and 11 are formed at both ends. Area 1
Further, the second protection element B including the gate electrode 10g formed on the upper part of 0 through the gate oxide film is further provided. The above points are common to the semiconductor device 2000.

Further, in the semiconductor device 3000, the power supply terminal 200 for external connection and the PMO in which the gate is always off.
An S protection transistor 16, a P-type low-concentration impurity diffusion region 14 in which high-concentration impurity diffusion regions 13 and 15 are formed at both ends, and a gate electrode formed above the low-concentration impurity diffusion region 14 via a gate oxide film. 3rd consisting of 14g
And the protection element C.

The source terminal 7s of the NMOS output transistor 7 is connected to the external connection ground terminal 300 by the connection line 3, the drain terminal 7d is connected to one end 6 of the high concentration impurity diffusion region of the first protection element A, and the gate The terminal 7g is connected to the output drive signal line 8. First protection element A
The other end 4 of the high-concentration impurity diffusion region is connected to the external connection output terminal 100 by the connection line 1. The gate electrode 5g of the first protection element A is connected to the external connection ground terminal 300 by the connection line 3.

The source terminal 12s and the gate terminal 12g of the NMOS protection transistor 12 are connected to the external connection ground terminal 300 by the connection line 3, and the drain terminal 12d is connected to one end 11 of the high-concentration impurity diffusion region of the second protection element B. It is connected. The other end 9 of the high-concentration impurity diffusion region of the second protection element B is connected to the external connection output terminal 1 by the connection line 1.
Connected to 00. The gate electrode 10g of the second protection element B is connected to the external connection ground terminal 300 by the connection line 3.

The source terminal 16s of the PMOS protection transistor 16 is connected to the connection terminal 300 for external connection by the connection line 3, the drain terminal 16d is connected to one end 15 of the high-concentration impurity diffusion region of the third protection element C, and the gate thereof. The terminal 12g is connected to the external connection power supply terminal 200 by the connection line 2. The other end 13 of the high-concentration impurity region of the third protection element C is connected to the external connection output terminal 100 by the connection line 1.
It is connected to the. Gate electrode 14 of third protection element C
g is connected to the external connection power supply terminal 200 by the connection line 2.

The third protection element C and the PMOS output transistor 16 (reference numeral 3000a in FIG. 8) are provided on the substrate of the SOI-CMOS process structure as shown in FIG. Note that reference numerals 101 and 131 to 133 represent the first layer metal, reference numeral 134 represents polysilicon,
Reference numerals 135 to 136 represent P-type impurity diffusion layers, and reference numeral 1
Reference numerals 137 to 14 denote second layer metals 23 and 124.
Reference numeral 141 represents a first layer metal-diffusion interlayer connection hole.
Represents the first-layer metal-polysilicon connection hole, and the reference numeral 1
Reference numerals 143 and 143 denote second-layer metal-first-layer metal connection holes, reference numeral 143 denotes a low-concentration P-type impurity diffusion region,
Reference numeral 144 represents a low concentration N-type impurity diffusion region.

Further, the first protection element A and the NMOS output transistor 7, the second protection element B and the NMOS protection transistor 12, the third protection element C and the PMOS.
The protection transistor 16 is, as shown in FIG.
It is also possible to integrally provide it on the substrate of the OI-CMOS process structure. Incidentally, reference numerals 101 to 105 in FIG.
Represents the first layer metal, reference numerals 106 to 108 represent polysilicon, reference numeral 109 represents an N type impurity diffusion layer, reference numeral 110 represents a P type impurity diffusion layer, and reference numerals 123 to 12
Reference numeral 4 denotes a second layer metal, reference numerals 113 to 118 denote first layer metal-diffusion interlayer connection holes, reference numerals 119 to 121 denote first layer metal-polysilicon connection holes, and reference numeral 12
Reference numerals 5 to 128 represent second-layer metal-first layer metal connection holes, reference numeral 129 represents a low-concentration N-type impurity diffusion region, and reference numeral 130 represents a low-concentration P-type impurity diffusion region.

As shown in FIG. 10, above the low-concentration impurity diffusion region 14, the low-concentration impurity diffusion region 13 and the high-concentration impurity diffusion region 15 are completely crossed in parallel with the low-concentration impurity diffusion region. The gate electrode 14g is arranged via the gate oxide film 74, and the gate electrode 14g
Is connected to the power line 2. Low concentration impurity diffusion region 1
4, high-concentration impurity diffusion regions 13 and 15, and gate electrode 14
The third protection element C formed by g and g operates as a protection element of the PMOS protection transistor 16. In addition,
Reference numeral 70 in FIG. 10 represents a field oxide film, and reference numeral 7
1 to 72 represent an interlayer insulating film, reference numeral 73 represents a surface protective film, reference numeral 80 represents a buried oxide film, and reference numeral 90 represents P.
It represents a mold substrate.

The operation of the semiconductor device 3000 having the above structure will be described with reference to FIGS. 11 and 12. In addition,
In the following, the protective element C when the positive electrode electrostatic surge is applied
Will be described with reference to FIG. 11, and the protection element C when a negative electrode electrostatic surge is applied will be described with reference to FIG.

FIG. 11 schematically shows a cross section taken along the line WW ′ in FIG. 9 when the positive electrode electrostatic surge enters the output terminal 100. When a positive electrostatic surge enters the output terminal 100, the gate 14 connected to the power line 2
Since a relatively negative voltage is applied to g, the low-concentration impurity diffusion region 14 under the gate 14g becomes a P-type accumulation layer, and P from the high-concentration impurity diffusion region 13 to the high-concentration impurity diffusion region 15 is formed. It works as a resistor because it is integrated into the mold.

On the other hand, when a negative electrostatic surge enters the output terminal 100, a relatively positive voltage is applied to the gate 14g connected to the external connection power supply terminal 200, as shown in FIG. As a result, the low-concentration impurity diffusion region 5 under the gate 14g is turned into an N-type inversion layer, and the P-type high-concentration impurity diffusion region 13 and the high-concentration impurity diffusion region 15 are electrically insulated.

As described above, the low-concentration impurity diffusion region 14 connected in series between the output line 1 and the PMOS protection transistor 16 behaves as a resistance element against the electrostatic surge of the positive electrode and the electrostatic surge of the negative electrode. On the other hand, it behaves as an electrically insulating element. Therefore, when a negative electrostatic surge enters between the external connection output terminal 100 and the external connection ground terminal 300, the first protective element A or the second protective element B becomes a resistance element, and the protective element C becomes Since it serves as an insulating element, a surge current does not flow to the side of the PMOS protection transistor 16 that is easily destroyed by a negative electrostatic surge, and a surge current flows through the side of the NMOS output transistor 7 or the NMOS protection transistor 12 that is difficult to be destroyed.

On the other hand, when the electrostatic surge current of the positive electrode enters, the third protection element C becomes a resistance element, and the first and second protection elements C and C
Since the protection elements A and B of FIG. 6 are insulating elements, a surge current flows on the side of the PMOS protection transistor 16 and makes it difficult for the surge current to flow on the side of the NMOS output transistor 7 or the NMOS protection transistor 12.

Generally, an NMOS output transistor and an NM
In the OS protection transistor, the positive electrode electrostatic surge corresponding to the direction opposite to the drain PN junction is easily destroyed, and the PMOS protection transistor is easily destroyed by the negative electrode electrostatic surge. According to the invention,
Since the first and second protection elements A and B, which act as insulating elements against the electrostatic surge of the positive electrode, are connected in series to the NMOS output transistor 7 and the NMOS protection transistor 12, it is difficult for the surge current to flow on the NMOS side. A PMOS whose PN junction is in the forward direction with respect to this positive surge
A surge current is allowed to flow by providing a third protection element C, which is a resistance element due to a positive surge, on the protection transistor 16 side. Since a surge current flows on the PMOS side where the PN junction is in the forward direction with respect to the positive surge, good electrostatic surge resistance can be obtained.

On the other hand, regarding the resistance to the electrostatic surge of the negative electrode, since the first and second protection elements A and B are resistance elements, the NMOS output transistor 7 or the protection transistor 12 sends a surge current in the forward direction, Since the third protection element C serves as an insulating element, the PN junction hits in the opposite direction P
Since the surge current is prevented from flowing to the MOS protection transistor 16 side, good electrostatic surge resistance can be obtained also on the negative electrode side. Here, since the gate 16g of the PMOS protection transistor 16 is fixed to the power supply line 2 and is always in the off state, it does not affect the actual operation.

Further, as shown in FIG. 13, the high-concentration P-type impurity diffusion region 15 and the PM at one end of the third protection element C and PM.
Since the drain 16d of the OS protection transistor 16 is integrally formed in the same impurity diffusion region, it is possible to reduce the pattern area because the metal wiring connecting them is unnecessary.

The preferred embodiments of the semiconductor device according to the present invention have been described above with reference to the accompanying drawings.
The present invention is not limited to such an example. It is obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and naturally, these are also within the technical scope of the present invention. It is understood that it belongs.

For example, in the above-mentioned embodiments, C
Although the NMOS output transistor side in the MOS process has been described, a similar circuit can be realized on the PMOS output side. Therefore, it is needless to say that the present invention can be applied to a CMOS output circuit in which an NMOS output and a PMOS output are drawn out by a common output line, and further to an input / output terminal that connects a part of the output line to an input gate. .

Further, in the above-mentioned embodiments, an example of integrally forming the high-concentration impurity diffusion regions has been described in each of the embodiments, but the present invention is not limited to this. One end of the high-concentration impurity diffusion region of the first protection element,
High-concentration impurity diffusion region forming the drain terminal of the first conductivity type output transistor, one end of the high-concentration impurity diffusion region of the second protection element, and high concentration impurity forming the drain terminal of the first conductivity type protection transistor The impurity diffusion region, one end of the high concentration impurity diffusion region of the third protection element, and at least two high concentration impurity diffusion regions of the high concentration impurity diffusion region forming the drain terminal of the second conductivity type protection transistor are The present invention is also applicable by being integrally formed.

(Fourth Embodiment) FIG. 17 is a circuit diagram for explaining a semiconductor device according to a fourth embodiment of the present invention. The semiconductor device according to the fourth embodiment of the present invention will be described below with reference to FIG.

This semiconductor device has a first power supply terminal 101.
A circuit including an output terminal 199, a transistor 198, a first pinch-off resistor 111, and a first diode 121.

The anode of the first diode 121 is connected to the first power supply terminal 101, and the first diode 1
The cathode of 21 is connected to the output terminal 199, the source terminal of the transistor 198 is connected to the first power supply terminal 101, and the drain terminal of the transistor 198 is connected to one main electrode of the first pinch-off resistor 111. The other main electrode of the pinch-off resistor 111 of 1 is the output terminal 19
9 and the gate electrode of the first pinch-off resistor 111 is connected to the first power supply terminal 101.

The first pinch-off resistor 111 has a P-type semiconductor in which the end portions facing each other contain a higher concentration of P-type impurities than the central portion, and the first pinch-off resistor 111 has the gate oxide film interposed therebetween. This is an element having a gate electrode formed so as to be in contact with the central portion of the semiconductor and having opposite end portions as main electrodes, respectively.

The forward barrier voltage of the first diode 121 is set higher than the voltage applied between the first power supply terminal 101 and the output terminal 199 in the normal operation, and normally the first diode 121 is normally used. Prevent current from flowing through 121.

When a negative electrostatic surge enters the output terminal 199 of this circuit, the potential of the first power supply terminal 101 rises relative to the output terminal 199. Then the first
The electric potential of the gate electrode of the pinch-off resistor 111 rises above the electric potential of the main electrode of the first pinch-off resistor 111.
At this time, the conductivity type of the central portion of the P-type semiconductor of the first pinch-off resistor 111 changes to N-type. Therefore, the first
Both main electrodes of the pinch-off resistor 111 are insulated from each other.
Therefore, no surge current flows through the transistor 198. Moreover, a current flows between the output terminal 199 and the first power supply terminal 101 through the first diode 121, and the negative electrostatic surge is extinguished.

As described above, in the semiconductor device according to the fourth embodiment of the present invention, when a negative electrostatic surge enters the output terminal 199 of this circuit, this circuit operates as described above, The transistor 198 is effectively protected from electrostatic surge.

The conductivity type of the impurities contained in the first pinch-off resistor 111 may be N-type, and the connection direction of the first diode 121 may be reversed. in this case,
This circuit operates in the same manner as above when the positive electrostatic surge enters the output terminal 199, and can protect the transistor 198 from the electrostatic surge.

(Fifth Embodiment) FIG. 18 is a circuit diagram for explaining a semiconductor device according to a fifth embodiment of the present invention. The semiconductor device according to the fifth embodiment of the present invention will be described below with reference to FIG.

This semiconductor device is a circuit including the second power supply terminal 202, the second pinch-off resistor 212, and the second diode 222 in the semiconductor device of the fourth embodiment of the present invention.

The anode of the second diode 222 is connected to the output terminal 299, and the second diode 29
The cathode of 9 is connected to the first power supply terminal 201, and the first pinch-off resistor 211 and the first diode 221 are connected to the second
Output terminal 29 through the main electrode of the pinch-off resistor 212 of
9, and the gate electrode of the second pinch-off resistor 212 is connected to the second power supply terminal 202.

The second pinch-off resistor 212 has the same structure as the first pinch-off resistor 211, and is an element in which the conductivity type of impurities contained is N type.

The forward barrier voltage of the second diode 222 is set higher than the voltage applied between the first power supply terminal 201 and the output terminal 299 in the normal operation, and normally the second diode is used. Make sure that no current flows through 222.

When a positive electrostatic surge invades the output terminal 299 of this circuit, the potential of the second power supply terminal 202 becomes relatively lower than that of the output terminal 299. Then, the second
The electric potential of the gate electrode of the pinch-off resistor 212 is lower than the electric potential of the main electrode of the second pinch-off resistor 212.
At this time, the conductivity type of the central portion of the N-type semiconductor of the second pinch-off resistor 212 changes to P-type. Therefore, the second
The two main electrodes of the pinch-off resistor 212 are insulated from each other.
Therefore, no surge current flows through the transistor. Moreover, simultaneously with the above operation, a current flows between the output terminal 299 and the first power supply terminal 201 through the second diode 222, and the positive electrostatic surge disappears.

On the other hand, when a negative electrostatic surge enters the output terminal 299 of this circuit, the potential of the second power supply terminal 202 rises relative to the output terminal. Then, the second
The potential of the 212 gate electrode of the pinch-off resistor 212 of above rises higher than the potential of the main electrode of the second pinch-off resistor 212.
At this time, the conductivity type of the central portion of the N-type semiconductor of the second pinch-off resistor 212 is still N-type. Therefore, the two main electrodes of the second pinch-off resistor 212 are not insulated from each other. However, at the same time, the potential of the first power supply terminal 201 also rises relatively as compared with the output terminal 299.
First pinch-off resistor 211 and first diode 22
1 operates as described in the description of the semiconductor device according to the fourth embodiment of the present invention. Therefore, no surge current flows through the transistor 298. Then, a current flows between the output terminal 299 and the first power supply terminal 201 through the first diode 221, and the negative electrostatic surge is extinguished.

As described above, the semiconductor device of the fifth embodiment of the present invention has the same effect as the semiconductor device of the fourth embodiment. Further, when a positive electrostatic surge enters the output terminal of this circuit, this circuit operates as described above, and the transistor 298 can be effectively protected from the electrostatic surge.

(Sixth Embodiment) FIG. 19 is a circuit diagram for explaining a semiconductor device according to a sixth embodiment of the present invention. The semiconductor device according to the sixth embodiment of the present invention will be described below with reference to FIG.

This semiconductor device is a circuit provided with the third pinch-off resistor 313 in the semiconductor device of the fifth embodiment of the present invention.

The second diode 322 is connected to the output terminal 399 via the main electrode of the third pinch-off resistor 313, and the gate electrode of the third pinch-off resistor 313 is connected to the output terminal 399.

The third pinch-off resistor 313 is an element having the same structure as the second pinch-off resistor 312.

When a positive electrostatic surge enters the output terminal 399 of this circuit, the elements other than the third pinch-off resistor 313 operate as described in the description of the semiconductor device of the fifth embodiment of the present invention. To do. Therefore, no surge current flows through the transistor 398. Furthermore, the potential of the first power supply terminal 301 is relatively lower than the potential of the output terminal 399. Then, the third pinch-off resistor 313
Potential of the gate electrode of the second pinch-off resistor 313 rises higher than that of the main electrode of the third pinch-off resistor 313. At this time, the conductivity type of the central portion of the N-type semiconductor of the third pinch-off resistor 313 is still N-type. Therefore, both main electrodes of the third pinch-off resistor 313 are not insulated from each other. Therefore, a current flows between the output terminal 399 and the first power supply terminal 301 through the second diode 322, and the positive electrostatic surge disappears.

On the other hand, when a negative electrostatic surge enters the output terminal 399 of this circuit, the potential of the first power supply terminal 301 rises relatively as compared with the output terminal 399. Then, the potential of the gate electrode of the third pinch-off resistor 313 becomes lower than the potential of the main electrode of the third pinch-off resistor 313. At this time, N of the third pinch-off resistor 313
The conductivity type of the central part of the semiconductor of the type changes to P type. Therefore, both main electrodes of the third pinch-off resistor 313 are insulated from each other. Therefore, no voltage is applied to the second diode 322 in the reverse direction. Moreover, the elements other than the third pinch-off resistor 313 operate as described in the description of the semiconductor device according to the fourth embodiment of the present invention. Therefore, no surge current flows through the transistor. Moreover, a current flows between the output terminal 399 and the first power supply terminal 301 through the first diode 321, and the negative electrostatic surge is extinguished.

As described above, the semiconductor device of the sixth embodiment of the present invention has the same effect as the semiconductor device of the fifth embodiment. Furthermore, if a positive electrostatic surge enters the output terminal of this circuit, the third pinch-off resistor 3
Since the two main electrodes of 13 are insulated, the second transistor 322 can also be protected from electrostatic surge.

The second diode 322 is connected to the first power supply terminal 30 via the main electrode of the third pinch-off resistor 313.
Even if it is connected to 1, the effect of the semiconductor device of the third embodiment of the present invention does not change.

Further, the third pinch-off resistance is a fourth element (not shown) having the same structure as the first pinch-off resistance.
Even if the gate electrode of the fourth pinch-off resistance is connected to the first power supply terminal, the effect of the semiconductor device of the third embodiment of the present invention does not change.

(Seventh Embodiment) FIG. 20 is a circuit diagram for explaining a semiconductor device according to a seventh embodiment of the present invention. The semiconductor device according to the seventh embodiment of the present invention will be described below with reference to FIG.

This semiconductor device has a third power supply terminal 403,
The fourth power supply terminal 404 and the fifth pinch-off resistor 415
And a third diode 423.

The anode of the third diode 423 is connected to the third power supply terminal 403, the cathode of the third diode 423 is connected to the fourth power supply terminal 404, and the third diode 423 is connected to the fifth pinch-off resistance. It is connected to the third power supply terminal 403 via the main electrode of 415, and the gate electrode of the fifth pinch-off resistor 415 is connected to the fourth power supply terminal 40.
It is connected with 4.

The fifth pinch-off resistor 415 is the first pinch-off resistor 11 in the first embodiment of the present invention.
This is an element having the same structure as 1.

Further, the forward barrier voltage of the third diode 423 is set higher than the voltage applied between the third power supply terminal 403 and the fourth power supply terminal 404 in the normal operation, and usually the third barrier voltage. The current is prevented from flowing through the diode 423 of FIG.

When a positive electrostatic surge enters the third power supply terminal 403 of this circuit, the potential of the third power supply terminal 403 rises relative to the potential of the fourth power supply terminal 404. Then, the potential of the gate electrode of the fifth pinch-off resistor 415 becomes lower than the potential of the main electrode of the fourth pinch-off resistor 415. At this time, the fifth pinch-off resistor 41
The conductivity type of the central portion of the P-type semiconductor of No. 5 is still P-type. Therefore, both main electrodes of the fifth pinch-off resistor 415 are not insulated from each other, and the third power supply terminal 403 and the fourth power terminal 403
A current flows between the power supply terminal 404 and the power supply terminal 404 to eliminate the positive electrostatic surge.

On the other hand, when a negative electrostatic surge enters the third power supply terminal 403 of this circuit, the potential of the third power supply terminal 403 becomes relatively lower than the potential of the fourth power supply terminal 404. Then, the potential of the gate electrode of the fifth pinch-off resistor 415 rises higher than the potential of the 415 main electrode of the fifth pinch-off resistor 415. At this time, the conductivity type of the central portion of the P-type semiconductor of the fifth pinch-off resistor 415 changes to N-type. Therefore, both main electrodes of the fifth pinch-off resistor 415 are insulated from each other. Therefore, the third diode 42
No voltage is applied to 3 in the reverse direction.

As described above, in the semiconductor device according to the seventh embodiment of the present invention, when a positive electrostatic surge enters the third power supply terminal 403 of this circuit, this circuit operates as described above. , Eliminate the electrostatic surge. Further, when a negative electrostatic surge enters the third power supply terminal 403 of this circuit, the main electrodes of the fifth pinch-off resistor 415 are insulated from each other, so that the third diode 423 can be protected from the electrostatic surge. .

The semiconductor device of the seventh embodiment of the present invention is the same as the semiconductor device of the fifth embodiment of the present invention, except that the first power supply terminal 201 is connected to the third power supply terminal 403 and the second power supply is connected. The terminal 202 is used by connecting to the fourth power supply terminal 404. By assembling the circuit as described above, in the semiconductor device according to the fifth embodiment of the present invention, the first power supply terminal 2
When the potential of 01 becomes extremely higher than the potential of the second power supply terminal 202 (that is, when a positive electrostatic surge enters the third power supply terminal 403), the semiconductor device according to the fourth embodiment of the present invention Operates as described above, and the first power supply terminal 2
01 and the second power supply terminal 202 to flow a current to average the potential difference between both power supply terminals.

Further, in the semiconductor device of the seventh embodiment of the present invention, the fifth pinch-off resistor 415 is an element having the same structure as the second pinch-off resistor and is not shown in the sixth figure.
The same effect can be obtained by replacing the pinch-off resistor 416 with the gate electrode of the sixth pinch-off resistor 416 to the third power supply terminal 403.

Further, the third diode 423 is connected to the fifth diode
Even if it is connected to the fourth power supply terminal 404 via the main electrode of the pinch-off resistor 415, the same effect can be obtained.

On the other hand, when the connection direction of the third diode 423 is reversed and the gate electrode of the fifth pinch-off resistor 415 is connected to the third power supply terminal 403, this circuit becomes the third
When a positive electrostatic surge enters the power supply terminal 403, the fourth pinch-off resistor 414 causes the third power supply terminal 403 to operate.
And the fourth power supply terminal 404 are insulated to protect the third diode. Further, when a negative electrostatic surge enters the third power supply terminal 403, a current is passed between the third power supply terminal 403 and the fourth power supply terminal 404 to eliminate the negative electrostatic surge.

Furthermore, the circuit of the seventh embodiment of the present invention,
A circuit in which the gate electrode of the fifth pinch-off resistor 415 is connected to the third power supply terminal 403 by reversing the connection direction of the third diode 423 in the circuit of the seventh embodiment of the present invention described above. When the power supply terminal and the fourth power supply terminal are connected in parallel with each other, the third power supply terminal 403 can be used regardless of whether positive or negative surge enters the third power supply terminal 403.
It is possible to obtain a circuit that causes a current to flow between the fourth power supply terminal 404 and the fourth power supply terminal 404 to eliminate the surge.

(Eighth Embodiment) FIG. 21 is a circuit diagram for explaining a semiconductor device according to an eighth embodiment of the present invention. The semiconductor device according to the eighth embodiment of the present invention will be described below with reference to FIG.

This semiconductor device is the semiconductor device of the fourth embodiment of the present invention in which the first diode 121 is an element 521 in which a plurality of diodes are connected in series.

At this time, the total sum of the forward barrier voltages of the diodes is set higher than the voltage applied to both poles of the element 521 in which a plurality of diodes are connected in series in a normal operation, and the plurality of diodes are usually connected. A current should be prevented from flowing through the element 521 connected in series.

The semiconductor device of the eighth embodiment of the present invention has the same effect as that of the fourth embodiment. Furthermore, since the forward barrier voltage per diode is low, even if the forward barrier voltage per diode cannot be made higher than the voltage applied to both electrodes of the diode in normal operation, in normal operation It is possible to obtain a circuit in which no current flows between the output terminal 599 and the first power supply terminal 501.

When forming this circuit on a semiconductor substrate, an element 521 in which a plurality of diodes are connected in series is used.
May form electrodes adjacent to each other having different conductivity types on the semiconductor substrate. With this structure, it is possible to reduce the waste of the space on the semiconductor substrate for forming the circuit.

Further, the second and third diodes can also be replaced with an element similar to the element 512 in which the plurality of diodes used in this embodiment are connected in series.

(Ninth Embodiment) FIG. 22 is a circuit diagram for explaining a semiconductor device according to a ninth embodiment of the present invention. The semiconductor device according to the ninth embodiment of the present invention will be described below with reference to FIG.

This semiconductor device is the same as the semiconductor device according to the fourth embodiment of the present invention, except that the first pinch-off resistor 61 is used.
In this circuit, the first gate electrode is connected via a resistor 630.

When a high potential difference occurs between the output terminal 699 and the first power supply terminal 601 in this circuit, the voltage applied to the gate insulating film of the first pinch-off resistor 611 also rises. Here, the potential difference between the output terminal 699 and the first power supply terminal 601 is V ₀ , the time after the potential difference occurs is t, the resistance value of the resistor 630 is R, the gate insulating film capacitance is C,
If the base of the natural logarithm is e, the first pinch-off resistance 61
The voltage V applied to the gate insulating film of No. 1 is represented by the formula V = V ₀ (1−e ^{−t / CR} ).

When the gate electrode of the first pinch-off resistor 611 is connected via the resistor 630 having a resistance value R, the voltage applied to the gate insulating film of the first pinch-off resistor 611 does not rise immediately to V ₀ . When the value of R is further increased, it takes longer for the value of V to rise to the value of V ₀ . Here, before the voltage applied to the gate insulating film of the first pinch-off resistor 611 reaches a value that destroys the gate insulating film of the first pinch-off resistor 611, the diode 621 is
When a current is passed through the gate terminal to reduce the potential difference applied between the output terminal 699 and the first power supply terminal 601, the gate insulating film of the first pinch-off resistor 611 is destroyed by the gate insulating film of the first pinch-off resistor 611. It doesn't take so much voltage. Therefore, the gate insulating film of the first pinch-off resistor 611 can be protected from destruction due to high voltage.

The semiconductor device of the ninth embodiment of the present invention has the same effect as that of the fourth embodiment. Further, even if a high potential difference occurs between the output terminal 699 and the first power supply terminal 601 in this circuit, the first pinch-off resistance 6
Since a large voltage is not applied to the gate insulating film of No. 11, it is possible to prevent the gate insulating film of the first pinch-off resistor 611 from being destroyed by the high voltage.

The gate electrodes of the second, third, fourth, fifth and sixth pinch-off resistors can also be connected via resistors as in this embodiment. Further, a diode connected in series with the pinch-off resistor may be used as the resistor. For example, as shown in FIG. 23, the gate electrode of the third pinch-off resistor 713 may be connected to the output terminal 799 via the second transistor 722.

[0120]

According to the present invention, the output transistor can be effectively protected from the electrostatic surge which is apt to be destroyed.

Furthermore, according to the present invention, the electrostatic surge current that has entered the output terminal is shunted between the protective transistor side and the output transistor side, and the protective transistor side is also connected in series with the same protective means as the output transistor side. Therefore, it is possible to prevent the protection transistor side from being destroyed first.

Furthermore, according to the present invention, it is possible to obtain good resistance to electrostatic surges against both positive electrode electrostatic surges and negative electrode electrostatic surges.

Furthermore, according to the present invention, since the protection element, the output transistor, or the protection transistor are integrally formed in the same impurity diffusion region, the metal wiring connecting them is unnecessary, and the pattern area can be reduced.

Furthermore, according to the present invention, since the power supply terminal and the output terminal are connected via the diode, when an electrostatic surge enters the output terminal, a current flows between the output terminal and the power supply terminal through the diode. The static electricity surge that has flowed in and disappeared. Therefore, the output transistor can be more effectively protected from the electrostatic surge.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a semiconductor device according to a first embodiment.

FIG. 2 is a plan view of the semiconductor device of FIG.

3 is a cross-sectional view of the semiconductor device of FIG.

FIG. 4 is a cross-sectional view of protective element A when a negative electrode electrostatic surge is applied.

FIG. 5 is a cross-sectional view of protective element A when a positive electrode electrostatic surge is applied.

FIG. 6 is an explanatory diagram showing a semiconductor device according to a second embodiment.

FIG. 7 is a plan view of the semiconductor device of FIG.

FIG. 8 is an explanatory diagram showing a semiconductor device according to a third embodiment.

9 is a plan view of the semiconductor device of FIG.

10 is a cross-sectional view of the semiconductor device of FIG.

FIG. 11 is a protection element C when a negative electrode electrostatic surge is applied.
FIG.

FIG. 12 is a protection element C when a positive electrode electrostatic surge is applied.
FIG.

FIG. 13 is a plan view of another configuration example of the semiconductor device according to the third embodiment.

FIG. 14 is an explanatory diagram showing a conventional semiconductor device.

FIG. 15 is a cross-sectional view of an NMOS transistor in a CMOS process.

FIG. 16: NMOS in SOI-CMOS process
It is sectional drawing of a transistor.

FIG. 17 is an explanatory diagram showing a semiconductor device according to a fourth embodiment.

FIG. 18 is an explanatory diagram showing a semiconductor device according to a fifth embodiment.

FIG. 19 is an explanatory diagram showing a semiconductor device according to a sixth embodiment.

FIG. 20 is an explanatory diagram showing a semiconductor device according to a seventh embodiment.

FIG. 21 is an explanatory diagram showing a semiconductor device according to an eighth embodiment.

FIG. 22 is an explanatory diagram showing a semiconductor device according to a ninth embodiment.

FIG. 23 is an explanatory diagram showing a semiconductor device according to a ninth embodiment when the gate electrode of the pinch-off resistance is connected via a diode in the circuit.

[Explanation of symbols]

1 connection line 3 connection lines 4 High concentration impurity diffusion region 5 Low concentration impurity diffusion region 5g gate electrode 6 High concentration impurity diffusion region 7 NMOS output transistor 7s source 7g gate 7d drain 8 Output drive signal line 100 Output terminal for external connection 200 Power supply terminal for external connection 300 Ground terminal for external connection 1000, 2000, 3000 Semiconductor device

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21/822 H01L 21/8234 H01L 27/04 H01L 27/088

Claims (33)

(57) [Claims] 1. A semiconductor device manufactured by an SOI-CMOS process; a first power supply terminal for supplying a first power supply potential; a first conductivity type output transistor for outputting the first power supply potential; A first conductivity type low concentration impurity diffusion region in which a first conductivity type high concentration impurity diffusion region is formed, and a gate electrode formed above the low concentration impurity diffusion region via a gate oxide film. A protective element of 1; an output terminal; and a source terminal of the first conductivity type output transistor is connected to the first power supply terminal, and a drain terminal of the first conductivity type output transistor is
The high-concentration impurity diffusion region of the first protection element is connected to one end thereof, and the other end of the high-concentration impurity diffusion region of the first protection element is
A semiconductor device, wherein the semiconductor device is connected to the output terminal, and the gate electrode of the first protection element is connected to the first power supply terminal. 2. One end of the high-concentration impurity diffusion region of the first protection element and the high-concentration impurity diffusion region forming the drain terminal of the first conductivity type output transistor are the same.
The semiconductor device according to claim 1, wherein the semiconductor device is an impurity diffusion region . 3. A protection transistor of a first conductivity type, the gate of which is connected to the first power supply terminal and which is always in an off state; and a first conductivity type high concentration impurity diffusion region formed at both ends. A second protection element comprising a conductivity type low concentration impurity diffusion region and a gate electrode formed above the low concentration impurity diffusion region via a gate oxide film; A source terminal and a gate terminal are connected to the first power supply terminal, and a drain terminal of the first conductivity type protection transistor is
The second protection element is connected to one end of the high-concentration impurity diffusion region, and the other end of the high-concentration impurity diffusion region of the second protection element is
The semiconductor device according to claim 1, wherein the semiconductor device is connected to the output terminal, and the gate electrode of the second protection element is connected to the first power supply terminal. 4. A high-concentration impurity diffusion region (referred to as B) which forms one end (referred to as A) of the high-concentration impurity diffusion region of the first protection element and a drain terminal of the first conductivity type output transistor. And one end ( denoted as C) of the high-concentration impurity diffusion region of the second protection element and the high-concentration impurity diffusion region (denoted as D) forming the drain terminal of the first conductivity type protection transistor, At least 2 of the above A to D
The two high-concentration impurity diffusion regions are the same impurity diffusion region.
Characterized in that that, the semiconductor device according to claim 3. 5. A second power supply terminal for supplying a second power supply potential; a second conductivity type second protection transistor whose gate is connected to the third power supply terminal and which is always in an off state; A low-concentration impurity diffusion region of the second conductivity type in which a high-concentration impurity diffusion region of the second conductivity type is formed, and a gate electrode formed above the low-concentration impurity diffusion region via a gate oxide film. And a source terminal of the second conductivity type protection transistor is connected to the first power supply terminal, and a drain terminal of the second conductivity type protection transistor is
The high-concentration impurity diffusion region of the third protection element is connected to one end of the high-concentration impurity diffusion region, the gate terminal of the second-conductivity-type protection transistor is connected to the second power supply terminal, The other end of the diffusion area is
The semiconductor device according to claim 1, wherein the semiconductor device is connected to the output terminal, and the gate electrode of the third protection element is connected to the second power supply terminal. . 6. A high-concentration impurity diffusion region (referred to as B) which forms one end (referred to as A) of the high-concentration impurity diffusion region of the first protection element and a drain terminal of the first conductivity type output transistor. An end (denoted by C) of a high-concentration impurity diffusion region of the second protection element, a high-concentration impurity diffusion region (denoted by D) forming a drain terminal of the first conductivity type protection transistor, and One of the high-concentration impurity diffusion region of the third protection element (denoted by E) and the high-concentration impurity diffusion region ( denoted by F) of which the drain terminal of the second conductivity type protection transistor is formed, At least two high-concentration impurity diffusion regions having the same F are the same impurity diffusion region.
And characterized in that, the semiconductor device according to claim 5. 7. A semiconductor device manufactured by an SOI-CMOS process, comprising: a first power supply terminal for supplying a first power supply potential ; an output terminal; a transistor; 1 has a semiconductor containing a high concentration of conductivity type impurities, has a gate electrode formed to be in contact with the central portion of the semiconductor through a gate oxide film, the end portion facing each other It has a first pinch-off resistance used as a main electrode, a first terminal made of a semiconductor containing a first conductivity type impurity, and a first pinch-off resistance made of a semiconductor containing a second conductivity type impurity.
A first diode having two terminals, wherein the first terminal of the first diode is connected to the first power supply terminal, and the second terminal of the first diode is connected to the output terminal. Connected, the source terminal of the transistor is connected to the first power supply terminal, the drain terminal of the transistor is connected to one of the main electrodes of the first pinch-off resistance, the other of the first pinch-off resistance The main electrode of is connected to the output terminal, and the gate electrode of the first pinch-off resistor is connected to the first power supply terminal. 8. A gate oxide film having a semiconductor in which an end portion opposed to a second power supply terminal for supplying a second power supply potential contains a second conductivity type impurity at a higher concentration than a central portion. A semiconductor including a second pinch-off resistance having a gate electrode formed to be in contact with the central portion of the semiconductor through a pair of electrodes, the end portions facing each other being main electrodes, and an impurity of a first conductivity type. Having a first terminal made of, and further made of a semiconductor containing an impurity of the second conductivity type.
A second diode having two terminals, wherein the first terminal of the second diode is connected to the output terminal, and the second terminal of the second diode is connected to the first power supply terminal. Connected, the other main electrode of the first pinch-off resistor and the second terminal of the first diode are connected to the output terminal via the main electrode of the second pinch-off resistor, 8. The gate electrode of the second pinch-off resistance is connected to the second power supply terminal.
The semiconductor device according to. 9. A semiconductor device, in which end portions facing each other have a higher concentration of impurities of the second conductivity type than the central portion,
A third pinch-off resistor having a gate electrode formed in contact with the central portion of the semiconductor via a gate oxide film, the end portions facing each other serving as main electrodes, and the second diode; The first terminal is connected to the output terminal via the main electrode of the third pinch-off resistor, and the gate electrode of the third pinch-off resistor is connected to the output terminal. The semiconductor device according to claim 8. 10. An end portion of a semiconductor having a high concentration of impurities of the second conductivity type as compared with a central portion, the end portions facing each other being in contact with the central portion of the semiconductor through a gate oxide film. A third pinch-off resistor having a formed gate electrode, the end portions facing each other as main electrodes, and the second terminal of the second diode is the main pin of the third pinch-off resistor. 9. The semiconductor device according to claim 8, wherein the semiconductor device is connected to the first power supply terminal via an electrode, and the gate electrode of the third pinch-off resistor is connected to the output terminal. 11. The semiconductor device includes semiconductors whose opposite ends include a higher concentration of impurities of the first conductivity type than the central portion, and are in contact with the central portion of the semiconductor through a gate oxide film. A fourth pinch-off resistor having a formed gate electrode and having the opposite end portions as main electrodes, respectively , wherein the first terminal of the second diode is the main pin of the fourth pinch-off resistor. Is connected to the output terminal via an electrode, and the gate electrode of the fourth pinch-off resistance is the first electrode.
The semiconductor device according to claim 8, wherein the semiconductor device is connected to a power supply terminal. 12. The semiconductor device, wherein the end portions facing each other include a semiconductor containing a high concentration of impurities of the first conductivity type as compared with the central portion, and are in contact with the central portion of the semiconductor via a gate oxide film. A fourth pinch-off resistor having a formed gate electrode and having the opposite end portions as main electrodes, respectively, and the second terminal of the second diode is the main pin of the fourth pinch-off resistor. Is connected to the first power supply terminal via an electrode, and the gate electrode of the fourth pinch-off resistor is the first electrode.
The semiconductor device according to claim 8, wherein the semiconductor device is connected to a power supply terminal. 13. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of impurities of the first conductivity type than the central portion. Pinch-off having a semiconductor included in the semiconductor device, a gate electrode formed to be in contact with the central portion of the semiconductor through a gate oxide film, and the opposite end portions serving as main electrodes, respectively. A resistor and a first terminal made of a semiconductor containing an impurity of the first conductivity type; and a first terminal made of a semiconductor containing an impurity of the second conductivity type.
A third diode having a second terminal, wherein the first electrode of the third diode is the fifth pin.
A second main electrode of the third diode, the second electrode of the third diode is connected to the second power supply terminal, and the second main electrode of the fifth pinch-off resistor is connected to the first main electrode of the third diode.
A gate terminal of the fifth pinch-off resistor connected to the second terminal.
A semiconductor device, which is connected to a power supply terminal. 14. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of impurities of the first conductivity type than the central portion. Pinch-off having a semiconductor included in the semiconductor device, a gate electrode formed to be in contact with the central portion of the semiconductor through a gate oxide film, and the opposite end portions serving as main electrodes, respectively. A resistor and a first terminal made of a semiconductor containing an impurity of the first conductivity type; and a first terminal made of a semiconductor containing an impurity of the second conductivity type.
A third diode having two terminals, wherein the first electrode of the third diode is the first power supply.
Connected to a terminal , the second electrode of the third diode is connected to one main electrode of the fifth pinch-off resistor, and the other main electrode of the fifth pinch-off resistor is connected to the second electrode.
A gate terminal of the fifth pinch-off resistor connected to the second terminal.
A semiconductor device, which is connected to a power supply terminal. 15. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein end portions facing each other are impurities of the first conductivity type as compared with a central portion.
It has a semiconductor containing a high concentration of
Is formed so as to be in contact with the central portion of the semiconductor via
Gate electrodes, and each of the end portions facing each other is
It has a fifth pinch-off resistance as a main electrode and a first terminal made of a semiconductor containing impurities of the first conductivity type.
And a second semiconductor made of a semiconductor containing impurities of the second conductivity type.
A third diode having two terminals, wherein the first electrode of the third diode is connected to the second power supply terminal, and the second electrode of the third diode is the fifth electrode. Pi
Is connected to one main electrode of Nchiofu resistance, said fifth other main electrode of the pinch-off resistance of the first conductive
A gate terminal of the fifth pinch-off resistor connected to the first terminal.
A semiconductor device, which is connected to a power supply terminal. 16. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of impurities of the first conductivity type than the central portion. Pinch-off having a semiconductor included in the semiconductor device, a gate electrode formed to be in contact with the central portion of the semiconductor through a gate oxide film, and the opposite end portions serving as main electrodes, respectively. A resistor and a first terminal made of a semiconductor containing an impurity of the first conductivity type; and a first terminal made of a semiconductor containing an impurity of the second conductivity type.
A third diode having a second terminal, wherein the first electrode of the third diode is the fifth pin.
A second main electrode of the third diode is connected to the first power supply terminal, and the second main electrode of the fifth pinch-off resistor is connected to the second main electrode of the third diode.
A gate terminal of the fifth pinch-off resistor connected to the first terminal.
A semiconductor device, which is connected to a power supply terminal. 17. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of the second conductivity type impurity than the central portion. A pinch-off having a semiconductor included in the above, a gate electrode formed so as to be in contact with the central portion of the semiconductor through a gate oxide film, and the end portions facing each other being main electrodes, respectively. It has a resistor and a first terminal made of a semiconductor containing impurities of the first conductivity type.
And a second semiconductor made of a semiconductor containing impurities of the second conductivity type.
A third diode having a second terminal, wherein the first electrode of the third diode is the sixth pin.
A second main electrode of the third diode, the second electrode of the third diode is connected to the second power supply terminal, and the second main electrode of the sixth pinch-off resistor is connected to the first electrode.
A gate terminal of the sixth pinch-off resistor connected to the first terminal.
A semiconductor device, which is connected to a power supply terminal. 18. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of the second conductivity type impurity than the central portion. A pinch-off having a semiconductor included in the above, a gate electrode formed so as to be in contact with the central portion of the semiconductor through a gate oxide film, and the end portions facing each other being main electrodes, respectively. It has a resistor and a first terminal made of a semiconductor containing impurities of the first conductivity type.
And a second semiconductor made of a semiconductor containing impurities of the second conductivity type.
A third diode having a second terminal, the first electrode of the third diode is connected to the first power supply terminal, and the second electrode of the third diode is the sixth electrode. It is connected to one main electrode of the pinch-off resistor, and the other main electrode of the sixth pinch-off resistor is connected to the second electrode.
A gate terminal of the sixth pinch-off resistor connected to the first terminal.
A semiconductor device, which is connected to a power supply terminal. 19. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of the second conductivity type impurity than the central portion. A pinch-off having a semiconductor included in the above, a gate electrode formed so as to be in contact with the central portion of the semiconductor through a gate oxide film, and the end portions facing each other being main electrodes, respectively. It has a resistor and a first terminal made of a semiconductor containing impurities of the first conductivity type.
And a second semiconductor made of a semiconductor containing impurities of the second conductivity type.
A third diode having two terminals, wherein the first electrode of the third diode is connected to the second power supply terminal, and the second electrode of the third diode is the sixth electrode. Pi
One of the main electrodes of the turn-off resistance (the third power supply terminal)
And the other main electrode of the sixth pinch-off resistor is connected to the first electrode.
A gate terminal of the sixth pinch-off resistor connected to the second terminal.
A semiconductor device, which is connected to a power supply terminal. 20. A semiconductor device formed on the same substrate as the semiconductor device according to claim 5 , wherein the end portions facing each other have a higher concentration of the second conductivity type impurity than the central portion. A pinch-off having a semiconductor included in the above, a gate electrode formed so as to be in contact with the central portion of the semiconductor through a gate oxide film, and the end portions facing each other being main electrodes, respectively. It has a resistor and a first terminal made of a semiconductor containing impurities of the first conductivity type.
And a second semiconductor made of a semiconductor containing impurities of the second conductivity type.
A third diode having two terminals, the third diode
Said first electrode of said diode is said sixth pinch-off
Connected to one main electrode of the resistor, the second electrode of the third diode is connected to the first power supply terminal, and the other main electrode of the sixth pinch-off resistor is connected to the second electrode.
A gate terminal of the sixth pinch-off resistor connected to the second terminal.
A semiconductor device, which is connected to a power supply terminal. 21. The semiconductor device according to claim 7 , wherein the first diode is an element in which a plurality of diodes are connected in series. 22. The semiconductor device according to claim 8, wherein the second diode is an element in which a plurality of diodes are connected in series. 23. The semiconductor device according to claim 13, wherein the third diode is an element in which a plurality of diodes are connected in series. 24. The element in which the plurality of diodes are connected in series is such that diodes adjacent to each other are formed adjacent to each other on a semiconductor substrate. The semiconductor device according to. 25. The semiconductor device according to claim 7 , wherein the gate electrode of the first pinch-off resistor is connected to the first power supply terminal via a resistor. 26. The semiconductor device according to claim 8 , wherein the gate electrode of the second pinch-off resistor is connected to the second power supply terminal via a resistor. 27. The semiconductor device according to claim 9 , wherein the gate electrode of the third pinch-off resistor is connected to the output terminal via a resistor. 28. The semiconductor device according to claim 11 , wherein the gate electrode of the fourth pinch-off resistor is connected to the first power supply terminal via a resistor. 29. The semiconductor device according to claim 13 , wherein the gate electrode of the fifth pinch-off resistor is connected to the second power supply terminal via a resistor. 30. The semiconductor device according to claim 15 , wherein the gate electrode of the fifth pinch-off resistor is connected to the first power supply terminal via a resistor. 31. The semiconductor device according to claim 17, wherein the gate electrode of the sixth pinch-off resistor is connected to the first power supply terminal via a resistor. 32. The semiconductor device according to claim 19 , wherein the gate electrode of the sixth pinch-off resistor is connected to the second power supply terminal via a resistor. 33. The semiconductor device according to claim 25, wherein the resistor is a diode.