JP3439424B2 - Digital signal receiving circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a device for receiving digital radio signals. INDUSTRIAL APPLICABILITY The present invention is suitable for use in wireless communication in which the radio wave propagation state changes due to interference from other radio wave devices during communication. The present invention is suitable for use in mobile communication. INDUSTRIAL APPLICABILITY The present invention is applied to a receiving device that corrects an error in a received digital signal and switches the line used when the error correction frequency is high. INDUSTRIAL APPLICABILITY The present invention is used in a system in which bit interleaving is also used to improve the possibility of error correction for errors that occur in bursts. According to the present invention, even if an error occurring in a burst is effectively corrected by a receiving circuit by bit interleaving, the line switching is performed unnecessarily because the frequency of error correction is high. Technology related to prevention.

[0002]

2. Description of the Related Art FIG. 5 is a circuit block diagram of a main part of a conventional digital signal receiving apparatus. Input terminal I of this circuit
A modulated signal modulated by a digital signal is input to N. A reception antenna system, a frequency conversion system, an intermediate frequency amplification system, and the like are provided in front of the input terminal IN, but these are not directly related to the description of the present invention, and therefore their description is omitted in this figure. The digital signal arriving at this input terminal IN is a bit-interleaved digital signal in the device on the transmission side.

Bit interleaving means that the bit signal arrangement order of a digital information signal sequence is changed over a number of frames and transmitted according to a preset logic, and is transmitted in bursts on the radio wave propagation path, that is, for a certain period of time. Even if a propagation failure occurs, on the receiving side, after interleaved decoding by the inverse logic of the set logic, the error occurrence positions due to the bursty propagation failure are dispersed, and the errors are concentrated in one frame. By not doing so, the correct bit information can be decoded by the error correction circuit in the subsequent stage.

That is, in the conventional circuit of FIG. 5, a demodulation circuit 1 having a bit interleaved digital signal as an input, a bit interleave decoding circuit 2 having an output signal of the demodulation circuit 1 as an input, and the bit interleave decoding circuit. An error correction circuit 3 that receives the output signal of 2;
The error correction circuit 3 is provided with a line deterioration detection circuit 4 which receives an error pulse generated at each error correction as an input, detects the frequency per time, and outputs a line deterioration alarm output when the frequency exceeds a set threshold value. It is a digital signal receiving circuit. The output of the error correction circuit 3 is a data output. When the output is sent to the line deterioration detection circuit 4, it is assumed that the line currently in use cannot secure sufficient communication quality, and a switch for selecting another line by a device (not shown) in cooperation with the transmission side device. The action is triggered.

[0005]

In a receiving circuit that decodes a signal interleaved in this way and executes error correction, burst-like interference occurs in the radio wave propagation path, and bit error of the received signal is generated. Even if they occur intensively, after the bit interleaved decoding is executed, the error is dispersed, and there is a high possibility that the error correction executed for each frame will succeed. For example, when error correction logic that can correct even a 2-bit error in one frame is used, if bit errors occur intensively, error correction becomes impossible in that frame. However, when bit interleaving is performed, the concentrated error bits are distributed over a large number of frames, and when a large number of frames with errors of 2 bits or less are generated in one frame, these frames are Error correction will be effectively performed.

However, also in this case, the error correction by the error correction circuit 3 is frequently executed, so that the number of error corrections detected by the line deterioration detection circuit 4 becomes large, and when the frequency per time exceeds the threshold value. Even though the error correction is effectively performed, the line deterioration detection circuit 4 outputs a line deterioration alarm output. As a result, the switching control for selecting another line is executed by the device (not shown). This is a wasteful control operation, and hinders the effect of improving the line quality due to the bit interleaving.

[0007] Further, this is not desirable for effective use of radio wave resources because the line that can substantially maintain communication is abandoned and another line is selected. Further, when the line is switched, a new instantaneous interruption occurs in the communication, which further deteriorates the communication quality.

The present invention has been made against such a background, and even if a burst error occurs in the radio wave propagation path,
Bit-interleaved decoding spreads the error,
An object of the present invention is to provide a receiving device that controls so as to prevent unnecessary switching of a line to be used even if it is detected that error correction is frequently performed when the error correction is effectively performed. To do. That is, the present invention aims to effectively use radio resources. An object of the present invention is to provide a receiving apparatus capable of improving communication quality by reducing interruptions due to line switching during communication.
An object of the present invention is to provide a receiving device that can effectively use the effect of bit interleaving.

[0009]

According to the present invention, in error correction performed after decoding of bit interleaving, position information of a bit subjected to error correction is acquired from an error correction circuit, and the bit position subjected to the error correction is When the error correction is performed on a plurality of adjacent bits in the propagation path according to the interleaving logic, it is assumed that the bit interleaving works effectively and the error correction is properly executed. Even if the frequency becomes high, the basic feature is to temporarily prevent the output of the output for warning the line deterioration.

That is, according to the present invention, a demodulation circuit (1) having a signal including a bit-interleaved digital signal as an input, a bit interleave decoding circuit (2) having an output signal of the demodulation circuit as an input, and the bit interleave. An error correction circuit (3) that receives the output signal of the decoding circuit and an error pulse that is generated by this error correction circuit at each error correction are input and the frequency per time is detected and this frequency exceeds the set threshold value. In a digital signal receiving circuit equipped with a line deterioration detecting circuit (4) for sending an alarm output at this time, the position information in the frame of the error corrected by the error correcting circuit (3) is input, and this error is propagated through the propagation path. The burst error detection circuit (5) that determines that the burst error occurred and the determination output of this burst error detection circuit Characterized by comprising a means for disabling the operation of the line deterioration detecting circuit (4) Te.

The numbers in the above parentheses are reference numbers of the embodiment drawings described later. This is given for easy understanding of the constitution of the invention, and is not for understanding the constitution of the invention limited to the embodiments. (same as below)

With this configuration, even if the frequency of error correction increases, the error correction effectively corrects the error generated in a burst in the propagation path due to the effect of the bit interleaving coding and decoding. As a result, it is possible to prevent unnecessary line switching and the like by determining the line deterioration.

The means for invalidating the operation of the line deterioration detection circuit (4) is a judgment output of the burst error detection circuit (5) for an error pulse given from the error correction circuit (3) to the line deterioration detection circuit (4). Can be configured to include a masking circuit (6) that shuts off for the period during which is transmitted. With this configuration, since the error pulse does not reach the line deterioration detection circuit (4) while the mask circuit (6) is performing the mask operation, the line deterioration detection circuit (4) has a high frequency of error correction. It will no longer be determined that

The means for invalidating the operation of the line deterioration detecting circuit (4) outputs the detection output of the line deterioration detecting circuit (4) for a period during which the judgment output of the burst error detecting circuit (5) is sent. It is possible to adopt a configuration including means for fixing the output logical value when the line deterioration is not detected. According to this configuration, it is invalidated on the output side of the line deterioration detection circuit (4), and its detection output is meaningless.

When the error correction circuit (3) performs the error correction, the burst error detection circuit (5) propagates according to the bit interleave logic by using the in-frame position information of the bit for which the error correction is performed. From the time when it is detected whether or not further error correction is performed on the bit transmitted subsequently to the bit on the path, and the error correction is performed on more than n adjacent bits on the propagation path. It can be configured to send the judgment output. With this configuration, the operation of the line deterioration detection circuit (4) can be disabled only while the effect of bit interleaving is substantially effective. This reference value n
2 to 10 is appropriate, but the number of bits in this frame should be set individually based on the number of bits in a frame, the number of frames for bit interleaving, the error correction logic used, and other factors. Kimono.

The burst error detection circuit (5) is constructed so as to continuously output the output signal after it exceeds n, until it no longer detects that the error correction has been performed on the adjacent bit in the propagation path. Is desirable.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a block diagram of the essential parts of a first embodiment of the present invention. A bit interleaved digital signal is input to the input terminal IN. An antenna system, a frequency conversion system, an intermediate frequency amplification system, and the like as a receiver are connected to the input terminal IN before the input terminal IN, but these are omitted from this drawing because they are not directly related to the description of the present invention.

The demodulation output signal of the demodulation circuit 1 is a digital baseband signal. This digital signal sequence is a signal that has been bit-interleaved on the transmission side, is decoded by a bit interleave decoding circuit 2 having the same inverse logic as the bit interleave on the transmission side, and is error-corrected by the error correction circuit 3 and further on the transmission side. Error correction is executed according to the error correction logic applied to the signal sequence. The error-corrected digital signal train becomes a data output signal. Further, the error correction circuit 3 takes out an error pulse generated each time error correction is executed, and supplies this to the line deterioration detection circuit 4 via a mask circuit 6. The line deterioration detection circuit 4 detects the frequency (that is, frequency) of the error pulse per unit time, and outputs a line deterioration alarm output when the frequency exceeds a set threshold value.

In the present invention, the position information indicating where the error position in each frame in which the error corrected by the error correction circuit 3 has occurred is extracted, and this position information is given to the burst error detection circuit 5, It is determined whether or not the error position has occurred in a burst on the propagation path. Then, the mask circuit 6 interrupts the error pulse input to the line deterioration detection circuit 4 for the period in which the judgment output of the burst error detection circuit 5 is transmitted.

FIG. 2 is a block diagram of the burst error detection circuit 5 of this embodiment. The position information input from the error correction circuit 3 is input to the register 11 and held until the next error occurs. The output of the register 11 is output from the register 12, the match detection circuit 13, the mismatch detection circuit 14, and the register 1 at the next clock timing.
Enter in 5. The register 11 and the register 12 are updated at the same time. That is, the register 11 and the register 12 hold the position information of two errors that have occurred successively.

The outputs of the register 11 and the register 12 are compared by the coincidence detection circuit 13, and the comparison result is counted by the coincidence counting circuit 16. The coincidence counting circuit 16 is a register 1
Every time 1 and the register 12 are updated, the number of consecutive matches is counted. The count value of the coincidence counting circuit 16 is given to the input of the burst judgment circuit 17, and when the count value reaches the set reference value n, the burst judgment circuit 17 sends a judgment output. The reference value n is 3 in this embodiment.

The output of the burst judgment circuit 17 is branched and supplied to the register 15 as a set signal. At this time, the register 15 takes in and latches the output of the register 11. At the same time, the output of the burst judgment circuit 17 is the output circuit 1
8 is also given to the output circuit 18, so that the output circuit 18 starts transmitting the mask signal.

The output of the register 15 is the mismatch detection circuit 14
, Where it is compared with the contents of register 11.
When they do not match, the mismatch detection circuit 14 sends a signal to the output circuit 18 and the mismatch counting circuit 19. In the output circuit 18, the output of the determination output is stopped by the output of the mismatch detection circuit 14 for one clock cycle. Further, the mismatch counting circuit 19 counts the number of outputs of the mismatch detecting circuit 14 every time the register 11 is updated. This discrepancy counting circuit 19
Is output to the burst determination circuit 17, and when the number of consecutive disagreements reaches the set reference value m, the burst determination circuit 17 determines that the burst has ended and stops the output of the mask signal from the output circuit 18. The reference value m is 3 in this embodiment. This reference value m should also be set individually for each system based on the number of bits in a frame, the scale of the number of frames for bit interleaving, the adopted error correction logic, and the like.

Next, how to detect the occurrence of a burst-like error after decoding the bit interleave will be described in more detail using one logical example of the bit interleave. Now, as an example, a block code with a frame length M that can correct one error in one frame is used, and N is used as the recombination logic of bit interleaving.
Assume that the order of bit data for each frame is rearranged as follows. That is, assuming that the j-th bit of the i frame is Dij, D11, D12, ..., D1M,
Signals in the order of D21, D22, ..., D2M, ... DNM are D11, D21, ..., DN1, D12, D22 ,.
Rearrange in the order of N2, ... DNM. This rearrangement can be performed by one matrix memory provided in the transmitter, and can be decoded (reassembled) by the same one matrix memory provided in the receiver.

FIG. 3 is a block diagram of a matrix memory for performing this rearrangement. That is, the frame length M is taken in the horizontal axis direction and the depth N is taken in the vertical axis direction. Here, one unit of recombination is N M-bit frames, and the number of bits is M × N. In the transmitter, the bit string before rearrangement is written from the upper left side in horizontal rows one M bits per frame, so that the next row is written each time the frame is changed. Then, read this from the upper left, this time by advancing N bits vertically in one column and sequentially advancing one column to the right,
The read output bit string is transmitted to the propagation path.

In the bit interleave decoding circuit 2 of the receiving device, the received signal sequence received from this propagation path is written in N columns in the vertical direction from the upper left of the same matrix memory. Then, by reading this while sequentially advancing one row at a time in the horizontal direction from the upper left to the bottom, the bit string before the rearrangement of the transmitting device can be decoded.

It is assumed that a burst-like error has occurred in the propagation path due to radar radio wave interference or the like.
Then, in the matrix memory provided in the bit interleave decoding circuit 2 of the receiving device, a large number of errors occur in adjacent frames in bits near the same number in each frame, that is, in the vertical direction of the figure. . Bits indicated by hatching in FIG. 3 are bits in which an error has occurred. In the error correction circuit 3 of this receiver, error correction logic can correct up to one frame, that is, one error in one row in FIG. Most errors can be corrected when the transmission time is less than or equal to. The error position information transmitted by the error correction circuit 3 may be the bit number of each frame in this example. If the bit numbers of the adjacent frames match, the result of FIG.
When the coincidence detection circuit 13 described in 1 above detects a coincidence and the discrepancy occurs, the discrepancy detection circuit 14 also detects a discrepancy. A decision output is then generated as described above, which is sent or stopped.

The mask circuit 6 does not input the error pulse to the line deterioration detection circuit 4 for the period in which the judgment output is transmitted from the burst error detection circuit 5. As a result, the line deterioration detection circuit 4 does not generate an alarm output because the frequency of error pulses is high.

In the above embodiment, the bit interleaving recombination logic, as described with reference to FIG. 3, is such that a burst error appears at the same bit number in adjacent frames. , K for adjacent frames, not for the same number of adjacent frames
The same operation can be performed even if the bits appear in a shifted manner. Even if k is not a constant value, if it can be defined by a function, it can be dealt with similarly. Further, as shown in FIG. 2, the burst error detection circuit 5 has been described as being configured by a register or a coincidence detection circuit.
This detection logic can be implemented in software and implemented similarly.

(Second Embodiment) This embodiment uses an error correction logic capable of correcting an error on a frame-by-frame basis even when there is a 2-bit error in one frame. The configuration of the main part of the receiving circuit of FIG. 1 described in the first embodiment is the same. The bit interleave rearrangement logic is also the same as in the first embodiment. The second embodiment differs in the configuration of the burst error detection circuit 5. This is shown in FIG.

In FIG. 4, the in-frame position information of the bits for which error correction has been executed is input to the sequential register 21.
And held in register 22. The next time erroneous frames occur, they are copied to registers 23 and 24, register 21 and register 22.
The position information of the error bit of the frame including the next error is sequentially written in. These four registers 21, 22, 2
The held values of 3 and 24 are compared by the coincidence detection circuit 25. The coincidence detection circuit 25 has the same structure as the register 21.
3, the registers 21 and 24, the registers 22 and 23, and the registers 22 and 24 are compared, and the results are latched in the detection result holding circuit 26. The match determination circuit 27 makes the next determination from the output of the match detection circuit 25 and the output of the detection result holding circuit 26.

1) If the register 23 matches the register 21 or register 22 in the match detection circuit 25 and the register 21 matches the register 23 or register 24 in the detection result holding circuit 26, match 2) register in the match detection circuit 25 If 24 and the register 21 or the register 22 match, and the register 22 and the register 23 or the register 24 match in the detection result holding circuit 26, all match except 3) above 1) and 2).

That is, when the same error position information continues, a match is output. At the same time, the coincidence determination circuit 27 controls the selector 28, and in the case of the above 1), the register 2
3 output is selected, and in the case of 2) above, the output of the register 24 is selected. As a result, the continuous matching position information is input to the register 29. The output of the coincidence determination circuit 27 is input to the coincidence counting circuit 30, and when the count value reaches the set value n, burst occurrence is detected from the burst determination circuit 31. As a result, the determination output is sent from the output circuit 32. Both outputs of the register 21 and the register 22 are input to the mismatch detection circuit 33, and the output circuit 32 is input to a burst whose input does not match the register 29.
Stop sending the signal. Further, the mismatch detection circuit 33 outputs a mismatch for a burst in which the outputs of both the register 21 and the register 22 do not match the output of the register 29.

With this configuration, the present invention can be carried out even when the error correction logic which can correct even when there are two error bits in one frame is adopted.

[0035]

As described above, according to the present invention, when error bits generated in a burst are dispersed by bit interleaving and the error is effectively corrected by an error correction circuit, error correction is performed. It is possible to prevent the alarming of the line failure because the frequency of execution is high. As a result, useless line switching can be avoided, radio resources can be effectively used, and communication quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a receiving circuit according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a burst error detection circuit according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a matrix memory of the bit interleave decoding circuit according to the embodiment of the present invention.

FIG. 4 is a block configuration diagram of a burst error detection circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a main part of a conventional receiving circuit.

[Explanation of symbols]

1 Demodulation circuit 2-bit interleave decoding circuit 3 Error correction circuit 4 Line deterioration detection circuit 5 Burst error detection circuit 6 Mask circuit 11, 12, 15 registers 13, 25 Match detection circuit 14, 33 Mismatch detection circuit 16, 30 Match counting circuit 17, 31 Burst judgment circuit 18, 32 output circuit 19, 34 Mismatch counting circuit 21, 22, 23, 24, 29 registers 26 Detection result holding circuit 27 Matching judgment circuit 28 selector

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Riki Mitsui 2-11-1, Nagata-cho, Chiyoda-ku, Tokyo NTT Mobile Communications Network Co., Ltd. (56) References: JP-A-6-252892 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 1/00 G06F 11/10 330 H03M 13/27 H04B 17/00

Claims (5)

(57) [Claims] 1. A demodulation circuit that demodulates and outputs a bit interleaved digital signal, and a bit interleave decoding circuit that receives the output signal of this demodulation circuit as an input.
An error correction circuit that receives the output signal of this decoding circuit,
The line deterioration detecting circuit for sending to alarm output detected that the frequency detecting the time per frequency as an input an error pulses generated in each error correction exceeds the set threshold value in the error correction circuit in the digital signal receiving circuit including an error of this <br/> plurality of error position information based on input and storing position information in the frame of the corrected through the error correction circuit error burst channel Receiving a digital signal, characterized by including a burst error detection circuit for determining that the line error detection circuit has been generated, and means for controlling the operation of the line deterioration detection circuit according to the determination output of the burst error detection circuit. circuit. 2. The means for controlling the operation of the line deterioration detection circuit cuts off an error pulse given from the error correction circuit to the line deterioration detection circuit for a period during which a judgment output of the burst error detection circuit is sent. The digital signal receiving circuit according to claim 1, further comprising a mask circuit. 3. When the means for controlling the operation of the line deterioration detecting circuit does not detect the line deterioration during the period in which the detection output of the line deterioration detecting circuit is transmitted as the judgment output of the burst error detecting circuit. 2. The digital signal receiving circuit according to claim 1, further comprising means for fixing the output logical value of. 4. The burst error detection circuit, when error correction is executed by the error correction circuit, uses the in-frame position information of the bit for which the error correction has been executed, according to the logic of bit interleaving, in the propagation path. It is sequentially detected whether or not the error correction is further executed for the bit transmitted subsequent to the bit, and the judgment output is started when it is detected that the error correction is executed for more than n adjacent bits in the propagation path. Claim 1 including means for delivering
The described digital signal receiving circuit. 5. The digital signal according to claim 4, wherein said burst error detection circuit includes means for continuously outputting an output signal until it no longer detects that error correction has been performed on an adjacent bit in its propagation path. Receiver circuit.