JP3435744B2 - Multiplication circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit suitable for mounting on a so-called DSP (digital signal processor) or the like, which is developed for high-speed execution of operations required for voice processing and graphic processing. .

[0002]

2. Description of the Related Art Conventionally, a shift and add method has been known as a binary multiplication method. As a method for executing this shift and add method, a method using a parallel multiplier, 2-bit booth (2bit-Bo
oth) method is known.

In the method using the parallel multiplier, when the multiplicand X and the multiplier Y are multiplied, the number 1 is, for example, 8 bits ×
As shown in the example of performing multiplication of 8 bits → 16 bits, a partial product obtained by multiplying the multiplicand X by 1 bit of the multiplier Y is added, and these partial products are added,
The multiplication results Z14 to Z0 are obtained. In addition,
In Expression 1, S-SS represents sign extension.

[0004]

[Equation 1]

The 2-bit booth method is represented by
For example, as shown in the case of multiplication of 8 bits × 8 bits → 16 bits, the least significant bit Y of the multiplier Y is
Multiply from 0 by 2 bits, set 0 as the least significant evaluation bit, and perform partial product operation with the evaluation bits y _{2j + 2} , y _{2j + 1} , y _2j as shown in Table 1. Thus, the multiplication results Z14 to Z0 are obtained.

In this 2-bit booth method,
All numerical values are represented in 2's complement, and signs are sign-extended.

[0007]

[Equation 2]

[0008]

[Table 1]

The 2-bit Booth method has the advantage that the number of partial products generated can be reduced and the addition process can be shortened, as compared with the multiplication method using a parallel multiplier.

[0010]

However, even with this 2-bit Booth method, when this is used as a logic circuit, the number of stages of addition increases as the number of digits increases, and as a result, a large number of operations are required. There is a problem that it takes time and the amount of logic increases.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide a multiplication circuit capable of reducing the number of stages of addition, shortening the operation time, and reducing the amount of logic to be processed.

[0012]

FIG. 1 is a diagram showing the principle of a multiplication circuit according to the present invention. The multiplication circuit of the present invention has 2n bits × 2n bits → 2n bits (the lower 2n bits of the result are rounded down). It is assumed that multiplication is performed.

In the figure, X is a multiplicand of 2n bits (where n is
= Integer greater than or equal to 2), x ₁ is the upper n bits of the multiplicand X, x ₀
Is the lower n bits of the multiplicand X, Y is the multiplier of 2n bits, y
₁ indicates the upper n bits of the multiplier Y, and y ₀ indicates the lower n bits of the multiplier Y.

Further, 10 is a multiplication unit, and x₁To be
Number, y₀Multiplication with x as the multiplier₁Xy₀, X ₀Is the multiplicand, y₀
Multiplication with x as the multiplier₀Xy₀, X₁Is the multiplicand, y₁And the multiplier
Multiplication x₁Xy₁, X₀Is the multiplicand, y₁Multiplication with a multiplier
x₀Xy₁Is to do.

However, the multiplying unit 10 performs multiplication x₁Xy₀To
For y₀The evaluation bit of y₀._{2 J + 2}, Y₀._{2J + 1},
y₀._2J(However, when J = 0, 1 ... n / 2)
To y₀._{2 J + 2}= 1, y₀._{2J + 1}= 0, y₀._2JWhen = 0
X for partial product operations₁Inversion number (1's complement)
Shift 1 bit to the left and add 2 bits to the right
And y₀._{2J + 2}= 1, y₀._{2J + 1}= 0, y₀._2J= 1
And y₀._{2J + 2}= 1, y₀. _{2J + 1}= 1, y₀._2J= 0
In some cases, for partial product operations, x₁Add the inversion number of
The first 2 bits modified to shift right by 2 bits.
The multiplication is performed based on the method of T. Booth.

Further, the multiplication section 10 performs multiplication for the multiplication x ₀ × y ₀ based on the second 2-bit Booth method in which the code is modified so as to extend 0.

[0017] The multiplication unit 10, for multiplying x ₁ × y ₁ is, y ₁ evaluation bit _{y 1. 2 J + 2,} y 1. 2J + 1,
y _1. when referred to _2J, the value of the least significant evaluation bit value M of the most significant bit of _{y 0, y 1. 2J +} 2 = 1, y 1. 2J + 1 = 0,
y _1. In the case of _2J = 0, for the operation of the partial product, by adding a value obtained by 1-bit shift to left reversal number of x ₁ is shifted to the right by 2 _{bits, y 1. 2J + 2 =} 1, y _{1. 2J + 1 = 0,} y 1. 2J = 1
Cases, _{and, y 1. 2J + 2 =} 1, y 1. 2J + 1 = 1, y 1. 2J =
In the case of 0, the operation of the partial product is based on the third 2-bit Booth method modified by adding the value obtained by shifting the inverted number of x ₁ by 1 bit to the left and shifting it to the right by 2 bits. The addition is performed.

Further, for the multiplication x ₀ × y ₁ , the multiplication unit 10 sets the value of the least significant evaluation bit to the value M of the most significant bit of y ₀ , and the code is modified to extend 0. Four
Multiplication is performed based on the 2-bit Booth's method.

Numeral 11 is an adder, and this adder 1
1 is multiplication x₁Xy₀, X₀Xy₀, X ₁Xy₁, X₀Xy₁of
Multiplication result z₁, Z₂, Z₃, Z_FourFor x₁Xy₀, X₀
Xy₁Multiplication result of z₁, Z_FourFor, make the digits the same,
Multiplication x₀Xy₀Multiplication result of z₂For x₁Xy₀, X₀
Xy₁Multiplication result of z₁, Z_FourTo n right shift
And multiply x₁Xy₁Multiplication result of z₃For, multiply x₁
Xy₀, X₀Xy₁Multiplication result of z₁, Z_FourAgainst n bit
In the state of shifting to the left, the addition is performed.

[0020]

In the present invention, the upper n bits x of the multiplicand X are
₁ , the lower n bits x _{0 of} the multiplicand X, the upper n bits y _{1 of} the multiplier Y, and the lower n bits y ₀ of the multiplier Y are transferred to the multiplication unit 10.

[0021] Here, the multiplying unit 10, the multiplicand a x _1, and multiplying x ₁ × y ₀ to multiplier of y _0, the multiplicand a x _0,
a multiplying x ₀ × y ₀ to the y ₀ and the multiplier, the multiplicand a x _1, and multiplying x ₁ × y ₁ to the multiplier of y _1, the multiplicand a x _0, multiplying x ₀ × y ₁ to the multiplier of y ₁ Is done.

In this case, for the multiplication x ₁ × y ₀ , y ₀ ..
_{2J + 2 = 1, y 0} . 2J + 1 = 0, y 0. In the case of _2J = 0, for the operation of the partial product, 2-bit inversion number by adding 1-bit shift value to the left of x ₁ It shifted to the _{right, y 0. 2J + 2 =} 1,
_{y 0. 2J + 1 = 0} , y 0. For _2J = 1, and, y _{0. 2J +} 2 =
If 1, y _{0 .2J + 1} = 1 and y _{0 .2J} = 0, then for the operation of the partial product, the first modified by adding the inversion number of x ₁ to shift right by 2 bits. The multiplication is performed based on the 2-bit Booth method. That is, the multiplication by the operation of the partial product based on Table 2 is performed.

[0023]

[Table 2]

The sign of the multiplication x ₀ × y ₀ is 0.
The multiplication is performed based on the second 2-bit Booth method modified to extend That is, the multiplication is performed by the operation of the partial product based on Table 3. The two's complement is the least significant bit of the inversion number (the one's complement) plus one.

[0025]

[Table 3]

For multiplication x ₁ × y ₁ , the value of the least significant evaluation bit is set to the value M of the most significant bit of y ₀ , and y ₁ ..
_{2J + 2 = 1, y 1} . 2J + 1 = 0, y 1. In the case of _2J = 0, for the operation of the partial product, 2-bit inversion number by adding 1-bit shift value to the left of x ₁ It shifted to the right, also, y _{1. 2J + 2
= 1, y 1. 2J +} 1 = 0, y 1. For _2J = 1, and, y _{1. 2J
+2} = _1, y 1. In the case of _{2J + 1 = 1, y 1} . 2J = 0 , for the operation of the partial product, which is modified to shift by adding an inverted number of x ₁ to 2 bits to the right The multiplication is performed based on the third 2-bit Booth method. That is, the multiplication is performed by the operation of the partial product based on Table 4.

[0027]

[Table 4]

For the multiplication x ₀ × y ₁ , the value of the least significant evaluation bit is set to the value M of the most significant bit of y ₀ , and the code is modified to extend 0 to a fourth 2-bit Booth. The multiplication is performed based on the method of. That is, the multiplication is performed by the operation of the partial product based on Table 5.

[0029]

[Table 5]

Then, in the adder 11, multiplication x ₁ ×
multiplication results z ₁ , z of y ₀ , x ₀ × y ₀ , x ₁ × y ₁ , x ₀ × y _{1.
For 2} , z ₃ and z ₄ , the digits of the multiplication results z ₁ and z ₄ of x ₁ × y ₀ and x ₀ × y ₁ are the same, and the multiplication result z ₂ of multiplication x ₀ × y ₀ is The multiplication results z ₁ and z _{4 of} x ₁ × y ₀ and x ₀ × y ₁ are shifted to the right by n bits, and multiplication x ₁ ×
Regarding the multiplication result z ₃ of y ₁ , multiplication x ₁ × y ₀ , x ₀ × y ₁
The multiplication results z ₁ and z ₄ are added in the state of being shifted to the left by n bits, where the multiplicand is X and the multiplier is Y.
2n bits × 2n bits → 2n bits (the lower 2 bits of the result are rounded down) are completed.

The multiplication circuit according to the present invention is applied here to 0111, 0101, 1111, 1011 and 101.
0,1111,1000,0111 ₂ (1979428
743 _{1 0)} as the multiplicand X, 1010,0001,01
01, 0110, 1011, 1110, 0011, 11
The content of the calculation in the case of performing multiplication with 10 ₂ (−1588150722 ₁₀ ) as the multiplier Y is as follows.

In this case, x ₁ = 0111,0101,1,
111, 1011, x ₀ = 1010, 1111, 100
0,0111, y ₁ = 1010,000,0101,
0110, y ₀ = 1011, 1110, 0011, 11
It becomes 10.

Therefore, the multiplication x₁Xy₀Is calculated in Equation 3
Done as shown, multiplication x₀Xy₀The calculation of is shown in Equation 4.
And multiply x₁Xy₁Is calculated as shown in Equation 5.
I multiply x₀Xy₁Is calculated as shown in Equation 6,
Multiplication x₁Xy₀, X₀Xy₀, X ₁Xy₁, X₀Xy₁Multiplication of
Fruit z₁, Z₂, Z₃, Z_FourIs added as shown in Equation 7.
It

[0034]

[Equation 3]

[0035]

[Equation 4]

[0036]

[Equation 5]

[0037]

[Equation 6]

[0038]

[Equation 7]

As described above, according to the present invention, when the 2n-bit multiplicand X and the 2n-bit multiplier Y are multiplied, the multiplicand X is set to the upper n bits x ₁ and the lower n bits x ₀ . , And multiply the multiplier Y by y _{1 of the} upper n bits,
It is divided into y _{0 of the} lower n bits.

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the present invention, the number of addition stages can be reduced, the multiplication time can be shortened, and the logical amount to be processed can be reduced.

The multiplications x ₁ × y ₀ , x ₀ × y ₀ , x ₁ ×
Performing y ₁ , x ₀ × y ₁ by the modified first, second, third, and fourth 2-bit Booth method is an example, and needless to say, it can be performed by a method other than these methods. is there.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, referring to FIGS. 2 to 7, examples of use of the first to fifth and fourth embodiments of the multiplication circuit according to the present invention will be described.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention, in which 20 is a 2n-bit register for storing a multiplicand X and 21 is a 2n-bit register for storing a multiplier Y. A register, 22 is a 2n-bit register for storing the calculation result, and 23 is a register 20-
22 is a control unit for controlling 22.

Further, 24 is a multiplier for multiplying n bits × n bits → 2n bits based on Table 2 or Table 4, 25
Is a multiplier that performs multiplication of n bits × n bits → 2n bits based on Table 3 or Table 5.

Reference numeral 26 denotes the multiplication result output from the multipliers 24 and 25, and the value stored in the register 22.
It is an adder that adds n bits and 3n bits.

In this first embodiment, 2n bits ×
When multiplication of 2n bits → 2n bits is performed, the 2n-bit multiplicand X is stored in the register 20, and the register 2
The 2n-bit multiplier Y is stored in 1 and the register 22 is cleared.

Next, of the multiplicand X stored in the register 20, the upper n bits x ₁ are transferred to the multiplier 24 as the multiplicand, the lower bits x ₀ are transferred to the multiplier 25, and the register 21 stores them. Of the multiplier Y, the lower bit y ₀ is transferred to the multipliers 24 and 25 as a multiplier.

Here, in the multiplier 24, multiplication of x ₁ × y ₀ is performed based on Table 2, and the multiplication result z ₁
Is transferred to the adder 26, and in the multiplier 25,
Based on the above, the multiplication x ₀ × y ₀ is performed, and the multiplication result z ₂ is transferred to the adder 26.

[0050] In the adder 26, for the multiplication result z ₁ of the multiplication x ₁ × y _0, the multiplication result z ₂ of the multiplication x ₀ × y _0,
For the multiplication result z ₁ , the least significant bit is the least significant bit at the time of addition, and for the multiplication result z ₂ , the n + 1th bit is the least significant bit at the time of addition, 3n bits + 3n bits are added, and the upper 2n bits of the addition result are in register 2
Stored in 2.

Next, of the multiplier Y stored in the register 21, the upper n bits y ₁ are transferred as multipliers to the multipliers 24 and 25, and the least significant bit y ₀ of the multiplier Y is used as the least significant evaluation bit. The high-order bit M is transferred to the multipliers 24 and 25.

Here, in the multiplier 24, the multiplication x ₁ × y ₁ is performed based on Table 4, and the multiplication result z ₃
Is transferred to the adder 26, and in the multiplier 25,
Based on the above, the multiplication x ₀ × y ₁ is performed, and the multiplication result z ₄ is transferred to the adder 26.

[0053] In the adder 26, the multiplication result z ₃ of the multiplication x ₁ × y _1, the multiplication result z ₄ of the multiplication x ₀ × y _1, the value stored in the register 22, the multiplication result z _3, the The most significant bit is the most significant bit during the addition, the least significant bit of the multiplication result z ₄ is the least significant bit during the addition, and the stored value of the register 22 is the least significant bit. 3n bits + 3n bits are added in a state where the upper bits are the most significant bits at the time of addition, and the upper 2n bits of the addition result are stored in the register 22.

Here, regarding the 2n-bit multiplicand X and the 2n-bit multiplier Y, 2n bits × 2n bits → 2n
The result of the bit multiplication is obtained in the register 22, and the multiplication is completed.

As described above, in the first embodiment,
When multiplying the 2n-bit multiplicand X and the 2n-bit multiplier Y, the multiplicand X is divided into upper n bits x ₁ and lower n bits x ₀ , and the multiplier Y is divided into upper n bits y ₁ and lower n.
It is divided into bits y ₀ .

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the first embodiment, the number of addition stages can be reduced, the multiplication time can be shortened, and the logical amount can be reduced.

Second Embodiment FIG. 3 FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
Reference numeral 30 is an n-bit register that stores the upper n bits x ₁ of the 2n-bit multiplicand X, and 31 is an n-bit register that stores the lower n bits x ₀ of the 2n-bit multiplicand X.

Further, 32 is the upper n of the 2n-bit multiplier Y.
N-bit register in which bit y ₁ is stored, 33 is 2
It is an n-bit register that stores the lower n bits y _{0 of the} n-bit multiplier Y.

Further, 34 is n bits × n based on Table 2.
Reference numeral 35 is a multiplier for performing bit-> 2n-bit multiplication, and 35 is a multiplier for performing n-bit * n-bit-> 2n-bit multiplication based on Table 3.

36 is n bits × n based on Table 4.
A multiplier that performs multiplication of bits → 2n bits, and a multiplier 37 that performs multiplication of n bits × n bits → 2n bits based on Table 5.

Further, 38 is a multiplier 34, 35, 36, 3
Regarding the multiplication result output from 7, 3n bits + 3n
An adder for adding bits, 39 is a 2n-bit register for storing the upper 2n bits of the addition result output from the adder 38.

In this second embodiment, 2n bits ×
When multiplication of 2n bits → 2n bits is performed, the upper n bits x ₁ of the multiplicand X are stored in the register 30, the lower n bits x ₀ of the multiplicand X are stored in the register 31, and the upper n bits of the multiplier Y are stored in the register 32. The bit y ₁ is stored, and the lower n bits y ₀ of the 2n-bit multiplier Y are stored in the register 33.

The upper n bits x ₁ of the multiplicand X stored in the register 30 are used as the multiplicands in the multipliers 34 and 36.
And the lower n bits x ₀ of the multiplicand X stored in the register 31 are transferred to the multipliers 35 and 37 as the multiplicand.

The upper n bits y ₁ of the multiplier Y stored in the register 32 are transferred to the multipliers 36 and 37 as multipliers, and the lower n bits y ₀ of the multiplier Y stored in the register 33 are multipliers. 34, 35.

As the least significant evaluation bit in the multipliers 36 and 37, the most significant bit M of the least significant n bits y ₀ of the multiplier Y stored in the register 33 is transferred to the multipliers 36 and 37. In the multipliers 34 and 35, 0 is set as the least significant evaluation bit.

Here, in the multiplier 34, based on Table 2, multiplication with x ₁ as a multiplicand and y ₀ as a multiplier is performed,
The multiplication result z ₁ is transferred to the adder 38, and the multiplier 35
In the above, based on Table 3, multiplication with x ₀ as a multiplicand and y ₀ as a multiplier is performed, and the multiplication result z ₂ is transferred to the adder 38.

Further, in the multiplier 36, based on Table 4, multiplication is carried out with x ₁ as the multiplicand and y ₁ as the multiplier, and the multiplication result z ₃ is transferred to the adder 38, and in the multiplier 37. On the basis of Table 5, multiplication is performed using x ₀ as a multiplicand and y ₁ as a multiplier, and the multiplication result z ₄ is transferred to the adder 38.

In the adder 38, multiplication x ₁ × y ₀ , x
₀ x y ₀ , x ₁ x y ₁ , x ₀ x y ₁ multiplication results z ₁ , z ₂ ,
For z ₃ and z ₄ , the least significant bit of the multiplication result z ₁ is the least significant bit at the time of addition, and the n + 1th bit of the multiplication result z ₂ is the least significant bit at the time of addition. And the multiplication result z ₃ is
The most significant bit is set as the most significant bit at the time of addition, and the multiplication result z ₄ is added with the least significant bit at the least significant bit at the time of addition. Of the addition result, the upper 2n bits are stored in the register 39.

Here, for the 2n-bit multiplicand X and the 2n-bit multiplier Y, 2n bits × 2n bits → 2n
The result of the bit multiplication is obtained in the register 39, and the multiplication is completed.

Thus, also in this second embodiment,
When multiplying the 2n-bit multiplicand X and the 2n-bit multiplier Y, the multiplicand X is divided into upper n bits x ₁ and lower n bits x ₀ , and the multiplier Y is divided into upper n bits y ₁ and lower n.
It is divided into bits y ₀ .

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the second embodiment as well,
It is possible to reduce the number of addition stages and shorten the multiplication time.

Third Embodiment FIG. 4 FIG. 4 is a circuit diagram showing a third embodiment of the present invention, in which 40 is a 2n-bit register for storing a multiplicand X, 41 is a 2n-bit register for storing a multiplier Y. The register 42 is a 2n-bit register for storing the operation result.

43 is a multiplier for multiplying n bits × n bits → 2n bits based on Table 2, Table 3, Table 4 or Table 5, and 44 is a control for controlling the registers 40 to 42 and the multiplier 43. Reference numeral 45 denotes an adder / subtractor that adds the multiplication result output from the multiplier 43 and the value stored in the register 42.

When the multiplier 43 receives the mode signal MD0 from the control unit 44, it performs multiplication based on Table 2 or Table 4, and when it receives the mode signal MD1 from the control unit 44, it outputs Table 3 Alternatively, the multiplication based on Table 5 is performed.

In the third embodiment, 2n bits ×
When the multiplication of 2n bits → 2n bits is performed, the 2n-bit multiplicand X is stored in the register 40 and the register 4
The 2n-bit multiplier Y is stored in 1 and the register 42 is cleared.

Next, among the multiplicands X stored in the register 40, the upper n bits x ₁ are used as the multiplicand and the multiplier 4
3 of the multipliers Y stored in the register 41 as well as being transferred to the multiplier 4, the lower n bits y ₀ are used as the multipliers.
3 is transferred.

Further, in this case, the control section 44 causes the multiplier 4 to
3 is applied with the mode signal MD0, and in the multiplier 43, multiplication of x ₁ × y ₀ is performed based on Table 2, and the multiplication result z ₁ is transferred to the adder / subtractor 45.

[0080] In the adder-subtracter 45, the multiplication result z ₁ of the multiplication x ₁ × y _0, for a storage value of the register 42, the multiplication result z ₁ includes a least significant bit when the least significant bit of the addition With respect to the value stored in the register 42, addition is performed with the most significant bit being the most significant bit at the time of addition, and the upper 2n bits of this addition result are stored in the register 42. It

Next, among the multiplicands X stored in the register 40, the lower n bits x ₀ are used as the multiplicand and the multiplier 4
3, the lower n bits y _{0 of the} multiplier Y stored in the register 41 are transferred to the multiplier 43 as a multiplier.

Also, in this case, the control unit 44 causes the multiplier 4 to
3 is supplied with the mode signal MD1, and in the multiplier 43, multiplication of x ₀ × y ₀ is performed based on Table 3, and the multiplication result z ₂ is transferred to the adder / subtractor 45.

[0083] In the adder-subtracter 45, the multiplication result z ₂ of the multiplication x ₀ × y _0, for a storage value of the register 42, the multiplication result z ₂ includes a least significant bit of the time of the n + 1-th bit adder With respect to the value stored in the register 42, addition is performed with the most significant bit being the most significant bit at the time of addition, and the upper 2n bits of this addition result are stored in the register 42. It

Next, of the multiplicands X stored in the register 40, the upper n bits x ₁ are used as the multiplicands by the multiplier 4
3 of the multipliers Y stored in the register 41, the upper n bits y ₁ are transferred to the multiplier 43 as a multiplier.

Further, the most significant bit M of the least significant n bits y ₀ of the multiplier Y stored in the register 41 is transferred to the multiplier 43 as the least significant evaluation bit.

Further, in this case, the control section 44 causes the multiplier 4 to
3 is applied with the mode signal MD0, and in the multiplier 43, multiplication of x ₁ × y ₁ is performed based on Table 4, and the multiplication result z ₃ is transferred to the adder / subtractor 45.

[0087] In the adder-subtracter 45, the multiplication result z ₃ of the multiplication x ₁ × y _1, for the value stored in the register 42, the multiplication result z ₃ includes a most significant bit of the time of the most significant bit is added With respect to the value stored in the register 42, addition is performed with the most significant bit being the most significant bit at the time of addition, and the upper 2n bits of this addition result are stored in the register 42. It

Next, among the multiplicands X stored in the register 40, the lower n bits x ₀ are used as the multiplicand and the multiplier 4
3 of the multipliers Y stored in the register 41, the upper n bits y ₁ are transferred to the multiplier 43 as a multiplier.

As the least significant evaluation bit, the most significant bit M of the least significant n bits y ₀ of the multiplier Y stored in the register 41 is transferred to the multiplier 43.

Further, in this case, the control section 44 causes the multiplier 4 to
3 is applied with the mode signal MD1, and in the multiplier 43, multiplication of x ₀ × y ₁ is performed based on Table 5, and the multiplication result z ₄ is transferred to the adder / subtractor 45.

[0091] In the adder-subtracter 45, the multiplication result z ₄ of the multiplication x ₀ × y _1, for the value stored in the register 42, the multiplication result z ₄ are the least significant bits of this time the least significant bit of the addition With respect to the value stored in the register 42, addition is performed with the most significant bit being the most significant bit at the time of addition, and the upper 2n bits of this addition result are stored in the register 42. It

Here, for the 2n-bit multiplicand X and the 2n-bit multiplier Y, 2n bits × 2n bits → 2n
The result of the bit multiplication is obtained in the register 42, and the multiplication is completed.

Thus, also in this third embodiment,
When multiplying the 2n-bit multiplicand X and the 2n-bit multiplier Y, the multiplicand X is divided into upper n bits x ₁ and lower n bits x ₀ , and the multiplier Y is divided into upper n bits y ₁ and lower n.
It is divided into bits y ₀ .

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the third embodiment as well,
It is possible to reduce the number of addition stages, shorten the multiplication time, and reduce the logical amount.

According to the third embodiment, in addition to multiplication of 2n bits × 2n bits → 2n bits, 2n bits × 2n bits × 2n bits × 2n bits → 2n bits as a 2n bit × 2n bit system product sum operation. A product-sum operation can be performed.

As a 2n-bit × n-bit product sum operation, a product-sum operation of 2n bits × n bits → 2n bits, 2n bits ± 2n bits × n bits → 2n bits can be performed.

Also, as a double n-bit × n-bit product sum operation, n-bit × n-bit ± n-bit × n-bit →
A product-sum operation of 2n bits, 2n bits ± (n bits × n bits ± n bits × n bits) → 2n bits can be performed.

Fourth Embodiment FIG. 5 FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention, in which 50 is a 2n-bit register for storing a multiplicand X and 51 is a 2n-bit register for storing a multiplier Y. The register 52 is a 2n-bit register for storing the operation result.

Further, 53 is a multiplier for multiplying n bits × n bits → 2n bits based on Table 2 or Table 3, 54
Is a multiplier that performs multiplication of n bits × n bits → 2n bits based on Table 4 or Table 5.

Further, 55 is a control unit for controlling the registers 50, 51 and 52 and the multipliers 53 and 54, and 56 is the multiplier 5
An adder / subtractor that adds the multiplication results output from the registers 3 and 54 to the value stored in the register 52.

When the multiplier 53 receives the mode signal MD0 from the control unit 55, it performs multiplication based on Table 2 or Table 4, and when it receives the mode signal MD1 from the control unit 55, it outputs the table 3 Alternatively, the multiplication based on Table 5 is performed.

When receiving the mode signal MD0 from the control unit 55, the multiplier 54 performs multiplication based on Table 2 or Table 4, and when receiving the mode signal MD1 from the control unit 55, the multiplier 54 Alternatively, the multiplication based on Table 5 is performed.

In the fourth embodiment, 2n bits ×
When multiplication of 2n bits → 2n bits is performed, the 2n-bit multiplicand X is stored in the register 50 and the register 5
The 2n-bit multiplier Y is stored in 1 and the register 52 is cleared.

Next, the multiplicand X stored in the register 50
Of these, the upper n bits x ₁ are multipliers 53,
Of the multipliers Y transferred to the register 54 and stored in the register 51, the lower n bits y ₀ are used as multipliers in the multiplier 53.
And the upper n bits y ₁ are transferred to the multiplier 54 as a multiplier.
Transferred to.

As the least significant evaluation bit in the multiplier 54, the most significant bit M of the least significant n bits y ₀ of the multiplier Y stored in the register 51 is transferred to the multiplier 54. In the multiplier 53, 0 is set as the least significant evaluation bit.

Further, in this case, the control unit 55 causes the multiplier 5 to
The mode signal MD0 is given to the reference numerals 3 and 54, the multiplication by x ₁ × y ₀ is performed in the multiplier 53 based on Table 2, and the multiplication result z ₁ is transferred to the adder / subtractor 56, and the multiplier 54 In, the multiplication x ₁ × y ₁ is performed based on Table 4, and the multiplication result z ₃ is transferred to the adder / subtractor 56.

[0108] In the adder-subtracter 56, the multiplication result z ₁ of the multiplication x ₁ × y _0, the multiplication result z ₃ of the multiplication x ₁ × y _1,
Regarding the multiplication result z ₁ of the multiplication x ₁ × y ₀ , the least significant bit is set to be the least significant bit at the time of addition, and the multiplication x 1
The multiplication result z ₃ of ₁ × y ₁ is added with the most significant bit being the most significant bit at the time of addition, and the addition result is stored in the register 52.

Next, among the multiplicands X stored in the register 50, the lower n bits x ₀ are used as the multiplicands and the multipliers 53 and 5 are provided.
4 and the multiplier Y stored in the register 51
Among them, the lower n bits y ₀ are transferred to the multiplier 53 as a multiplier, and the upper n bits y ₁ are transferred to the multiplier 54 as a multiplier.

As the least significant evaluation bit in the multiplier 54, the most significant bit M of the least significant n bits y ₀ of the multiplier Y stored in the register 51 is transferred to the multiplier 54. In the multiplier 53, 0 is set as the least significant evaluation bit.

Further, in this case, the control unit 55 causes the multiplier 5 to
The mode signal MD1 is applied to the reference numerals 3 and 54, and the multiplier 53 performs multiplication x ₀ × y ₀ based on Table 3, and the multiplication result z ₂ is transferred to the adder / subtractor 56, and the multiplier 54 In, the multiplication x ₀ × y ₁ is performed based on Table 5, and the multiplication result z ₄ is transferred to the adder / subtractor 56.

[0112] In the adder-subtracter 56, the multiplication result z ₂ of the multiplication x ₀ × y _0, the multiplication result z ₄ of the multiplication x ₀ × y _1, for the value stored in the register 52, the multiplication x ₀ × y ₀ Multiplication result z
_{For 2} , the n + 1th bit should be the least significant bit at the time of addition, and for the multiplication result z ₄ of multiplication x ₀ × y ₁ , the least significant bit should be the least significant bit at the time of addition. Regarding the value stored in the register 52, addition is performed with the most significant bit set to the most significant bit at the time of addition, and the addition result is stored in the register 5
Stored in 2.

Here, for the 2n-bit multiplicand X and the 2n-bit multiplier Y, 2n bits × 2n bits → 2n.
The result of the bit multiplication is obtained in the register 52, and the multiplication is completed.

Thus, also in the fourth embodiment,
When multiplying the 2n-bit multiplicand X and the 2n-bit multiplier Y, the multiplicand X is divided into upper n bits x ₁ and lower n bits x ₀ , and the multiplier Y is divided into upper n bits y ₁ and lower n.
It is divided into bits y ₀ .

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the fourth embodiment as well,
It is possible to reduce the number of addition stages, shorten the multiplication time, and reduce the logical amount.

According to the fourth embodiment, in addition to the multiplication of 2n bits × 2n bits → 2n bits, 2n bits × 2n bits × 2n bits × 2n bits → 2n bits as a 2n bit × 2n bit system multiply-add operation. A product-sum operation can be performed.

As a 2n-bit × n-bit product sum operation, a product-sum operation of 2n bits × n bits → 2n bits, 2n bits ± 2n bits × n bits → 2n bits can be performed.

As a double n-bit × n-bit product sum operation, n-bit × n-bit ± n-bit × n-bit →
A product-sum operation of 2n bits, 2n bits ± (n bits × n bits ± n bits × n bits) → 2n bits can be performed.

Fifth Embodiment FIG. 6 FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention. 60 is a 2n-bit register for storing the multiplicand X, and 61 is a 2n-bit register for storing the multiplier Y. The register 62 is a 2n-bit register for storing the calculation result.

Further, 63 is a multiplier for multiplying n bits × n bits → 2n bits based on Table 2, Table 3, Table 4 or Table 5, and 64 is shown in Table 2, Table 3, Table 4 or Table 5. Based on n
It is a multiplier that performs multiplication of bits × n bits → 2n bits.

Further, 65 is a multiplier for multiplying n bits × n bits → 2n bits based on Table 2, Table 3, Table 4 or Table 5, and 66 is shown in Table 2, Table 3, Table 4 or Table 5. Based on n
It is a multiplier that performs multiplication of bits × n bits → 2n bits.

67 is a control unit for controlling the registers 60, 61, 62 and the multipliers 63, 64, 65, 66, and 6
Reference numeral 8 denotes an adder / subtractor which adds 3n bits + 3n bits to the multiplication results output from the multipliers 63, 64, 65 and 66.

The multipliers 63, 64, 65, 66 are
When the mode signal MD0 is received from the control unit 67, Table 2
Alternatively, when the multiplication is performed based on Table 4 and the mode signal MD1 is received from the control unit 67, the multiplication based on Table 3 or Table 5 is performed.

In the fifth embodiment, 2n bits ×
When multiplication of 2n bits → 2n bits is performed, the multiplicand X is stored in the register 60 and the multiplier Y is stored in the register 61.

Then, the upper n bits x ₁ of the multiplicand X stored in the register 60 are used as the multiplicands in the multipliers 63 and 65.
And the lower n bits x ₀ are transferred to the multiplier 6 as the multiplicand.
4 and 66.

The upper n bits y ₁ of the multiplier Y stored in the register 61 are transferred to the multipliers 65 and 66 as multipliers, and the lower n bits y ₀ are multipliers to the multipliers 63 and 64.
Transferred to.

The multiplier Y stored in the register 61 is used as the least significant evaluation bit in the multipliers 65 and 66.
The most significant bit M of the lower n bits y ₀ of M is the multiplier 65, 6
6 is transferred. In the multipliers 63 and 64,
0 is set as the least significant evaluation bit.

In this case, the control unit 67 causes the multiplier 6 to
3 is given a mode signal MD0, and in the multiplier 63, multiplication is performed based on Table 2 with x ₁ being the multiplicand and y ₀ being the multiplier, and the multiplication result z ₁ is transferred to the adder / subtractor 68. .

Further, in this case, the control unit 67 causes the multiplier 6 to
4 is supplied with the mode signal MD1, and in the multiplier 64, based on Table 3, multiplication with x ₀ as a multiplicand and y ₀ as a multiplier is performed, and the multiplication result z ₂ is transferred to the adder / subtractor 68. .

Further, in this case, the control unit 67 causes the multiplier 6 to
5 is given the mode signal MD0, and in the multiplier 65, multiplication is carried out based on Table 4 with x ₁ being the multiplicand and y ₁ being the multiplier, and the multiplication result z ₃ is transferred to the adder / subtractor 68. .

Further, in this case, the control unit 67 causes the multiplier 6 to
5, the mode signal MD1 is supplied to the multiplier 5, and in the multiplier 66, based on Table 5, multiplication with x ₀ as the multiplicand and y ₁ as the multiplier is performed, and the multiplication result z ₄ is transferred to the adder / subtractor 68. .

In the adder / subtractor 68, multiplication x ₁ × y ₀ ,
x ₀ × y ₀ , x ₁ × y ₁ , x ₀ × y ₁ multiplication result z ₁ , z ₂ , z
_{For 3} and z ₄ , the least significant bit of the multiplication result z ₁ is the least significant bit at the time of addition, and the n + 1 bit of the multiplication result z ₂ is the least significant bit at the time of addition. For the multiplication result z ₃ , the most significant bit is the most significant bit for addition, and for the multiplication result z ₄ , the least significant bit is the least significant bit for the addition. In this state, addition is performed, and the upper 2n bits of this addition result are stored in the register 62.

Here, for the 2n-bit multiplicand X and the 2n-bit multiplier Y, 2n bits × 2n bits → 2n
The result of the bit multiplication is obtained in the register 62, and the multiplication is completed.

Thus, also in this fifth embodiment,
When multiplying the 2n-bit multiplicand X and the 2n-bit multiplier Y, the multiplicand X is divided into upper n bits x ₁ and lower n bits x ₀ , and the multiplier Y is divided into upper n bits y ₁ and lower n.
It is divided into bits y ₀ .

And x₁Is the multiplicand, y₀Power with
Arithmetic x₁Xy₀And x₀Is the multiplicand, y₀Multiplication with x as the multiplier₀
Xy₀And x₁Is the multiplicand, y₁Multiplication with x as the multiplier₁Xy₁
And x ₀Is the multiplicand, y₁Multiplication with x as the multiplier₀Xy₁And
The modified numbers shown in Table 2, Table 3, Table 4, and Table 5, respectively.
1st, 2nd, 3rd, 4th 2-bit booth method
Yes, these multiplication x₁Xy₀, X₀Xy₀, X₁Xy₁, X₀×
y₁Multiplication result of z₁, Z₂, Z ₃, Z_FourIs added as shown in Figure 1.
Add under the given rules shown in the block showing part 11
I'm supposed to.

Therefore, according to the fifth embodiment as well,
It is possible to reduce the number of addition stages and shorten the multiplication time.

According to the fifth embodiment, the control unit 6
By the control by 7, in addition to multiplication of 2n bits × 2n bits → 2n bits, 2n bits ± 2n bits × 2n bits → 2n as a 2n bit × 2n bit system product sum
It is possible to perform a multiply-accumulate operation consisting of bits.

As a 2n-bit × n-bit product sum operation, a product-sum operation of 2n bits × n bits → 2n bits, 2n bits ± 2n bits × n bits → 2n bits can be performed.

As a 2n bit × 2n bit system product-sum operation, a product-sum operation of 2n bit × 2n bit → 2n bit, 2n bit ± 2n bit × 2n bit → 2n bit can be performed.

As a double n-bit × n-bit product sum operation, n-bit × n-bit ± n-bit × n-bit →
A product-sum operation of 2n bits, 2n bits ± (n bits × n bits ± n bits × n bits) → 2n bits can be performed.

Example of Use ... FIG. 7 FIG. 7 is a block diagram showing a DSP equipped with the fourth embodiment (where n = 16) shown in FIG.

In the figure, 70 is an arithmetic unit, 71 and 72 are arithmetic registers used for various arithmetic operations, logical operations and transfer instructions, and 73 and 74 are 16 bits × 16 bits → 32.
Multiplier (MUL) for multiplying bits, 75 adder / subtractor (ADD / SUB), 76 arithmetic logic unit (AL
U) and 77 are operation result latches (LTR).

However, it is the arithmetic register 71 that can be used to store the multiplicand X and the multiplier Y in the multiplication instruction, and the arithmetic register 72 can be used for the arithmetic instruction.

The arithmetic register 71 corresponds to the registers 50 and 51 shown in FIG. 5, and the multipliers 73 and 74 correspond to the registers shown in FIG.
5 corresponds to the multipliers 53 and 54 shown in FIG.
Corresponds to the adder / subtractor 56.

Reference numeral 80 is a sequencer section,
Reference numeral 83 is an instruction register, a so-called instruction register (IR1, IR1A, IR2), 84 is a loop register (LPR) used during execution of loop processing, 8
Reference numeral 5 is a decoder, and the arithmetic unit 70 is controlled by the sequencer unit 80. That is, the sequencer unit 80 is shown in FIG.
Corresponds to the control unit 55 shown in.

Further, 90 is a CPU interface section, 91 is a CPU access control section, 92 is a system data latch (SDLT), 93 is a status register (STR) indicating the state of this DSP, and 94 is a system
Address latch (SALT).

CSX is a chip select signal and RW.
X is a read / write signal, DTACKX is a data acknowledge signal, D15-0 are data signals, and A15-0 are address signals.

Reference numeral 100 denotes an address calculation unit, which is 1
01 and 102 are arithmetic logic units (XALU, YAL
U) and 103 are offset registers used as offsets at the time of index addressing and circular addressing, and 104 is a control register (CTR) that controls the execution and operation mode of the program.

Reference numeral 105 denotes a PUSH / POP instruction,
A stack pointer (SP) 106, which indicates a save / restore address of data when a subroutine call instruction is executed, is an internal address control unit.

Further, 107 is an index register for designating an operand address at the time of transfer, and 108 is a program counter (PC) showing a memory address in which an instruction code is stored.

Further, 110 is an instruction RAM unit, and 11
1 is an instruction RA having a scale of 256 words × 16 bits
M (random access memory), 112 is an instruction RAM 11
1 is an instruction RAM interface unit for connecting to 1.

Further, 120 is an external ROM having a scale of 64K words × 16 bits for program / data sharing.
This is a memory interface unit that is intended for connection with (read only memory).

Reference numeral 121 denotes a memory access control unit,
122 is a memory address (MADDR) control unit, and 123 is
Is a memory data latch (MDLT), MM is a memory mode signal, MCEX is a memory chip enable signal, and MA.
15 to 0 are memory addresses, and MDs 15 to 0 are memory data.

Reference numeral 130 denotes a data RAM section, which is 1
31 and 132 are data RAMs having a scale of 256 words × 16 bits, and 133 are data RAMs 131 and 132.
This is a data RAM interface section for connection with the.

Further, 140 is a control unit, 141 is a clock control unit, 142 is a test circuit, RSTX is a reset signal, CLK1 is an internal clock signal, CLK0 is an external synchronization clock signal, and TEST2 to 0 are test signals. Is.

In this DSP, 16 bits × 16
Two multipliers 73, 7 for performing bit-> 32-bit multiplication
Since 4 is installed, 16-bit x 16-bit system multiply-accumulate operation, 16-bit x 16-bit → 32-bit,
32 bits ± 16 bits × 16 bits → 32 bits product-sum operation can be performed.

As the 32-bit × 16-bit product sum operation, a 32-bit × 16-bit → 32-bit, 32-bit ± 32-bit × 16-bit → 32-bit product-sum operation can be performed.

As a 32-bit × 32-bit product sum operation, a product-sum operation of 32 bits × 32 bits → 32 bits, 32 bits ± 32 bits × 32 bits → 32 bits can be performed.

As a double 16-bit × 16-bit product sum operation, 16 bits × 16 bits ± 16 bits ×
16 bits → 32 bits, 32 bits ± (16 bits ×
16 bits ± 16 bits × 16 bits) → 32 bits product-sum operation can be performed.

As described above, in this DSP, for example, when a 32-bit multiplicand X and a 32-bit multiplier Y are multiplied, the multiplicand X is divided into x ₁ of upper 16 bits and x _{0 of} lower 16 bits. And the multiplier Y is the top 16
As divided into a y ₁ and the lower 16 bits of y ₀ bits, the multiplicand of x _1, and multiplying x ₁ × y ₀ to multiplier of y _0, x
₀ multiplicand, and a multiplier x ₀ × y ₀ to multiplier of y _0, the multiplicand a x _1, and multiplying x ₁ × y ₁ to the multiplier of y _1, the multiplicand a x _0,
The multiplication x ₀ × y ₁ with y ₁ as a multiplier is shown in Table 2,
The modified first, second, third, shown in Table 3, Table 4, and Table 5,
4th 2-bit Booth method and multiply these x ₁
× y ₀ , x ₀ × y ₀ , x ₁ × y ₁ , x ₀ × y ₁ multiplication result z ₁ ,
It is possible to add z ₂ , z ₃ and z ₄ under the predetermined rule shown in the block showing the adder 11 shown in FIG.

Therefore, according to this DSP, when the calculation necessary for performing the graphic processing is performed, the number of addition stages can be reduced, the calculation time can be shortened, and the logic amount can be reduced.

[0163]

As described above, according to the present invention, when a multiplicand X of 2n bits and a multiplier Y of 2n bits are multiplied, the multiplicand X is x _{1 of} upper n bits and x of lower n bits. _{In addition to 0} , the multiplier Y is divided into y ₁ of the upper n bits and y _{0 of the} lower n bits, x ₁ is a multiplicand, y ₀ is a multiplier x ₁ × y ₀ , and x ₀ is a multiplicand, a multiplying x ₀ × y ₀ to the y ₀ and the multiplier, the multiplicand a x _1, multiplying x ₁ to the multiplier of y ₁
× and y _1, the multiplicand a x _0, multiplication and multiplier to y ₁ x ₀ × y ₁
And the modified first, second, third, and fourth 2-bit Booth methods shown in Tables 2, 3, 4, and 5, respectively, and multiply these by x ₁ × y ₀ , x ₀ x y ₀ , x
_{Since the result of 1} x y ₁ and x ₀ x y ₁ is added under a predetermined rule, the number of addition stages can be reduced, the multiplication time can be shortened, and the logical amount to be processed can be reduced. Can be achieved.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of use of a fourth embodiment of the present invention.

[Explanation of symbols]

X multiplicand Y multiplier 10 Multiplier 11 adder

Front Page Continuation (72) Inventor Shunji Katsuki 2-6-1, Marunouchi, Chiyoda-ku, Tokyo Fujitsu Device Limited (56) Reference JP-A-3-94328 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 7/52 310

Claims (6)

(57) [Claims] 1. A high-order n bit (x ₁ ) of a multiplicand (X) of 2n bits (where n is an integer of 2 or more), a multiplicand of a low-order n bit (y ₀ ) of a multiplier of 2n bits (Y). A first multiplication (x ₁ × y ₀ ) and a lower n bits (x ₀ ) of the multiplicand (X) as a multiplicand, and a lower n bits (y ₀ ) of the multiplier (Y) as a multiplier.
(X ₀ × y ₀ ) of the multiplicand (X), the upper n bits (x ₁ ) of the multiplicand (X) being the multiplicand, and the upper n bits (y ₁ ) of the multiplier (Y) being the multiplier
(X ₁ × y ₁ ), the lower n bits (x ₀ ) of the multiplicand (X) are the multiplicands, and the upper n bits (y ₁ ) of the multiplier (Y) are the multipliers.
Multiplication and (x ₀ × y _1), wherein the first multiplier _{(x 1 × y 0),} y 0 the evaluation bit lower n bits (y ₀₎ of the multiplier (Y). _{2J + 2 , y 0. 2J + 1,} y 0. 2J ( where, J = 0,1 ···
When the n / 2) and _{referred, y 0. 2J + 2 =} 1, y 0. 2J + 1 = 0,
y _0. In the case of _2J = 0, for the operation of the partial product, shifted by adding 1-bit shift value to the left by two bits right reversal number of the upper n bits (x ₁₎ of the multiplicand (X) , Y ₀ .
_{2J + 2 = 1, y 0} . 2J + 1 = 0, y 0. For _2J = 1, and, y
_{0. 2J + 2 = 1,} y 0. In the case of _{2J + 1 = 1, y 0} . 2J = 0 , for the operation of the partial product, inverting the number of the upper n bits (x ₁₎ of the multiplicand (X) Is added according to the method of the first 2-bit Booth modified to shift to the right by 2 bits, and for the second multiplication (x ₀ × y ₀ ) the sign is such that 0 is extended. Based on the method of the second 2-bit Booth modified as described above, for the third multiplication (x ₁ × y ₁ ), the evaluation bit of the high-order bit (y ₁ ) of the multiplier (Y) is y. _{1. 2J +} 2,
y _1. when referred to _{2J + 1, y 1. 2J} , the lower n bits (y ₀₎ of the most significant bit value of the multiplier the value of the least significant evaluation bit (Y) (M), y 1. _{2J + 2 = 1, y 1} . 2J + 1 = 0, y 1.
_{When 2J} = 0, in the operation of the partial product, a value obtained by shifting the inverted number of the upper n bits (x ₁ ) of the multiplicand (X) to the left by 1 bit is added to shift to the right by 2 bits, and y _{1 .2J + 2
= 1, y 1. 2J +} 1 = 0, y 1. For _2J = 1, and, y _{1.
2J + 2 = 1, y 1} . 2J + 1 = 1, y 1. In the case of _2J = 0, for the operation of the partial product, the number of inversions of the upper n bits (x ₁₎ of the multiplicand (X) was added And the value of the least significant evaluation bit is multiplied by the multiplier for the fourth multiplication (x ₀ × y ₁ ). The value of the most significant bit (M) of the lower n bits (y ₀ ) of (Y) is used, and the code is modified based on the fourth 2-bit Booth method modified to extend 0 (10). ) And the first, second, third and fourth multiplications (x ₁ × y ₀ , x ₀
× y ₀ , x ₁ × y ₁ , x ₀ × y ₁ ) multiplication result (z ₁ , z ₂ ,
z ₃ , z ₄ ) for the first and fourth multiplications (x ₁ ×
Regarding the multiplication result (z ₁ , z ₄ ) of y ₀ , x ₀ × y ₁ ),
With the same digit, the multiplication result (z ₂ ) of the second operation (x ₀ × y ₀ ) is the first and fourth multiplication (x ₁ × y
The multiplication result (z ₁ , z ₄ ) of ₀ , x ₀ × y ₁ ) is shifted to the right by n bits, and the multiplication result (z ₃ ) of the third multiplication (x ₁ × y ₁ ) is , The first and fourth multiplications (x ₁
Xy ₀ , x ₀ × y ₁ ) multiplication result (z ₁ , z ₄ )
An adder (1 that performs addition in a state of shifting left by n bits
1) is provided, and the multiplicand (X) and the multiplier (Y) are multiplied by each other. 2. The multiplication unit (10) performs the first multiplication (x ₁ × y ₀ ) based on the modified first 2-bit Booth method, and the third multiplication (10). x ₁ × y ₁ ) based on the modified third 2-bit Booth method and a second multiplier (x ₀ × y ₀ ) based on the modified second And a second multiplier for performing the fourth multiplication (x ₀ × y ₁ ) based on the modified fourth 2-bit Booth method. The multiplication circuit according to claim 1, wherein the multiplication circuit is configured as follows. 3. A first multiplier (10) for performing the first multiplication (x ₁ × y ₀ ) based on the modified first 2-bit Booth method; A second multiplier for performing the second multiplication (x ₀ × y ₀ ) based on the modified second 2-bit Booth method; and the third multiplication (x ₁ × y ₁ ). And a fourth multiplier (x ₀ × y ₁ ) for performing the fourth multiplication (x ₀ × y ₁ ) based on the modified method of the third 2-bit Booth. 4. The multiplication circuit according to claim 1, wherein the multiplication circuit is provided with a fourth multiplier that performs the above method. 4. The multiplication unit (10) performs the first multiplication (x ₁ × y ₀ ) based on the modified first 2-bit Booth method, and the second multiplication (10). x ₀ × y ₀ ) based on the modified second 2-bit Booth method and the third multiplication (x ₁ × y ₁ ) of the modified third 2-bit Booth. And a multiplier for performing the fourth multiplication (x ₀ × y ₁ ) based on the modified fourth 2-bit Booth method. The multiplication circuit according to claim 1. 5. The multiplication unit (10) performs the first multiplication (x ₁ × y ₀ ) based on the modified first 2-bit Booth method, and the second multiplication (10). x ₀ × y ₀ ) based on the modified second 2-bit Booth method and a third multiplier (x ₁ × y ₁ ) based on the modified third And a second multiplier for performing the fourth multiplication (x ₀ × y ₁ ) based on the modified fourth 2-bit Booth method. The multiplication circuit according to claim 1, wherein the multiplication circuit is configured as follows. 6. The multiplying unit (10) performs the modified first 2-bit Booth method on the first multiplication (x ₁ × y ₀ ) and the modified second 2-bit method. A first multiplier based on the Booth method, the modified third 2-bit Booth method or the modified fourth 2-bit Booth method, and the second multiplication (x ₀ Xy ₀ ) the modified first 2-bit Booth method, the modified second 2-bit Booth method, the modified third 2-bit Booth method or the modified A second multiplier based on a fourth 2-bit Booth method, and the modified first 2-bit Booth method, the modified third multiplication (x ₁ × y ₁ ). The second 2
A third multiplier, which is based on the Bit Booth method, the modified third 2-bit Booth method or the modified fourth 2-bit Booth method, and the fourth multiplication ( x ₀ × y ₁ ) the modified first 2-bit Booth method, the modified second 2-bit Booth method, the modified third 2-bit Booth method or the 4. The multiplier circuit according to claim 1, further comprising: a fourth multiplier that operates based on the modified fourth 2-bit Booth method.