JP3434787B2 - HDLC frame conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an HDLC frame conversion circuit, and more particularly to a high level data link control procedure (hereinafter referred to as HDLC) for packet data having a plurality of bits.
Enter. ) It relates to an HDLC frame conversion circuit for converting a frame or converting an HDLC frame into packet data having a plurality of bits.

[0002]

2. Description of the Related Art Conventionally, HDLC frame conversion is performed by an HDLC controller that converts transmission data into an HDLC frame and transmits it to a line or receives an HDLC frame from the line and extracts data transmitted from the HDLC frame. In the HDLC controller that is an NEC μPD72103A, for example, a processor and a program in the HDLC controller convert packet data, which is transmission data, into an HDLC frame and transmit it, or deframe the transmitted HDLC frame, which is reception data, into a packet. I am converting it to data. At this time, the NEC μPD72103A exchanges commands / statuses with an external processor or an external memory externally, receives packet data which is transmission data from the outside, and deframes the received HDLC frame. It passes the packet data to the outside.

[0003]

[Problems to be Solved by the Invention] The above-mentioned conventional HDL
HDLC frame conversion by C controller
At the C controller, a processor and a program convert packet data, which is transmission data, into an HDLC frame and transmit it, or de-frame the received HDLC frame, which is reception data, and convert it into packet data. , Exchanges commands / status with an external processor or external memory, and receives packet data that is transmission data from the outside, or passes de-framed packet data of the received HDLC frame to the outside. Therefore, there is a problem in that the processing speed of inputting the transmission data from the outside and outputting it to the line or passing the reception data from the line into packet data to the outside becomes slow. Further, since the external processor controls the HDLC controller by exchanging commands / statuses with the HDLC controller, there is a problem that the performance of the external processor deteriorates.

The object of the present invention is to eliminate the above-mentioned conventional drawbacks by preventing the command / status from being exchanged with an external processor or external memory so that the transmission data is input from the outside. An object of the present invention is to provide an HDLC frame conversion circuit in which the processing speed of outputting to a line or packet data of received data from a line and passing to the outside does not slow down, and the performance of an external processor does not deteriorate.

[0005]

Means for Solving the Problems The first HDLC of the present invention
The frame conversion circuit inputs packet data having a plurality of bits, processes the input packet data by a plurality of blocks each having a predetermined function, and processes the high-level data link control procedure (hereinafter referred to as HDLC). ) In the HDLC frame conversion circuit for converting into a frame, an input interface block for inputting the packet data serially and outputting this packet data serially, and a packet data for serially inputting the packet data from the input interface block FC for adding FCS indicating that a check sequence (hereinafter referred to as FCS) is added and serially outputting this packet data with FCS
S additional block and F from the FCS additional block
Packet data with CS is input serially and this FCS
When a predetermined number of "1" bits continue in the attached packet data, "0" insertion indicating that a "0" bit is inserted after this predetermined number of "1" bits is performed. 0 "An insertion block for serially outputting the inserted packet data with FCS, and the"
The flag data indicating that the start flag indicating the start of this data and the end flag indicating the end of this data are added to this input data is added to this input data serially. The above-mentioned F with the addition of "0"
A flag addition block for serially outputting the packet data with CS, and the FCS packet data with the flag added and the "0" inserted from the flag addition block are serially input and the input data is serially output. An output interface block,
A priority processing circuit that controls the operation of each block of the input interface block, the FCS addition block, the insertion block, the flag addition block, and the output interface block so that the blocks in the later stages have priority. And are provided.

In the priority processing circuit of the first HDLC frame conversion circuit of the present invention, when the output interface block is outputting the data serially and the output destination cannot receive the data, the output interface block outputs the data from the output interface block. The operation of each block of the input interface block, the FCS addition block, the insertion block, and the flag addition block in the preceding stage is stopped, and each of these blocks is placed in a holding state in which the state immediately before the stopping is held. I am trying to do it.

Further, in the priority processing circuit of the first HDLC frame conversion circuit of the present invention, when the flag addition block is performing the flag addition, the input interface block in a stage preceding the flag addition block, The operation of each of the FCS addition block and the insertion block is stopped, and each of these blocks is brought into a holding state for holding the state immediately before the stop.

Further, in the priority processing circuit of the first HDLC frame conversion circuit of the present invention, when the insertion block is performing the "0" insertion, the input in a stage preceding the insertion block is input. The operations of the interface block and the FCS-added block are stopped, and the blocks are brought into the holding state for holding the state immediately before the stopping.

Further, the priority processing circuit of the first HDLC frame conversion circuit of the present invention is arranged such that, when the FCS addition block is performing the FCS addition, the input interface block in the preceding stage of the FCS addition block is The operation is stopped, and the input interface block is brought into a holding state for holding the state immediately before the stop.

Further, in the priority processing circuit of the first HDLC frame conversion circuit of the present invention, when the output interface block is not outputting the FCS-added packet data to which the flag is added and the "0" is inserted, When the output interface block is outputting the data, when the output destination can receive the data, when the flag addition block is not performing the flag addition, the insertion block is
When 0 ”insertion is not performed and the FCS
When the additional block does not perform the FCS addition,
When the packet data is interrupted while the input interface block is inputting the packet data, each of the FCS addition block, the insertion block, the flag addition block, and the output interface block in the subsequent stage of the input interface block The operation of the blocks is stopped, and each of the blocks is brought into a holding state for holding the state immediately before the stop.

A second HDLC frame conversion circuit according to the present invention comprises a plurality of blocks each having a predetermined function by inputting a high level data link control procedure (hereinafter referred to as HDLC) frame having a plurality of bits. In an HDLC frame conversion circuit that processes the input HDLC frame and converts it into packet data having a plurality of bits, an input interface block that serially inputs the HDLC frame and serially outputs the HDLC frame; The HDLC frame is serially input from a block, and the HDLC included in the input HDLC frame is input.
The HDLC in which a start flag indicating the start of a frame and an end flag indicating the end of this HDLC frame are deleted and the flag is deleted
A flag deletion block that outputs frames serially,
When the HDLC frame from which the flag has been deleted is serially input from the flag deletion block and the HDLC frame from which the flag has been deleted is followed by a predetermined number of "1" bits, the predetermined number of consecutive "1" A deletion block that outputs “0” deletion indicating that the “0” bit after the “bit” is deleted, serially outputs the “0” deletion, and deletes the flag, and the deletion block The HDLC frame with the “0” deleted and the flag removed is serially input from the block, and a frame check sequence (hereinafter referred to as FC
Write S. ) Is deleted, the FCS is deleted, the FCS is deleted, the “0” is deleted, and the HDLC frame in which the flag is deleted is serially output, and the FCS is deleted from the FCS deletion block. The output interface block that inputs “0” deletion and serially outputs the HDLC frame from which the flag has been deleted, and outputs the input data, and the deletion block
A holding state for stopping the operation of the FCS deletion block and the output interface block, which are in the subsequent stage of the deletion block when performing the 0 "deletion, and for holding these blocks in the state immediately before the stop. And when the output interface block is outputting the data serially while the output destination is not receiving the data when the deletion block is not performing the "0" deletion, The operation of each of the FCS deletion block, the deletion block, the flag deletion block, and the input interface block, which precedes the output interface block, is stopped, and the state immediately before the stop of these blocks is retained. To hold it to It is configured to include a, a priority processing circuit for controlling to be.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of an HDLC frame conversion circuit of the present invention.

In the present embodiment shown in FIG. 1, the packet data 13 having a plurality of bits is input, and the packet data 13 input by a plurality of blocks each having a predetermined function are processed to perform a high level data link control procedure. (Hereinafter, referred to as HDLC.) H converted into a frame
In the DLC frame conversion circuit, the packet data 13
Is input serially from, for example, a FIFO, and the packet data 13 is serially output as DOUT1, and the packet data 13 is input serially from the input interface block 1 to the packet data 13 (for example, cyclic redundancy check ( Hereinafter, it will be referred to as CRC.) FCS addition indicating that a frame check sequence (hereinafter, referred to as FCS) that is a calculation result will be added will be performed.
The FCS addition block 2 for serially outputting the packet data 13 with CS (DOUT2), and the packet data 13 with FCS from the FCS addition block 2 are serially input, and a predetermined number of "1" bits are input to the packet data 13 with FCS. "0" insertion indicating that a "0" bit is to be inserted after this predetermined number of "1" bits that has been continued for a predetermined number of times, and this "0" inserted packet data with FCS 13 (DOUT3) Insertion block 3 that serially outputs F and the F that was inserted from insertion block 3 by "0"
The packet data 13 with CS is serially input, and a flag indicating that a start flag indicating the start of this data and an end flag indicating the end of this data are added to this input data is added and this flag is added to "0". Inserted packet data with FCS 13 (DO
Flag addition block 4 for serially outputting UT4)
Then, the FCS-added packet data 13 to which a flag is added and "0" is inserted is serially input from the flag addition block 4 and the input data is serially output to DOUT.
5, an output interface block 5 for outputting to a FIFO, and an input interface block 1, FCS
The additional block 2, the insertion block 3, the flag addition block 4, and the output interface block 5 are configured by a priority processing circuit 6 that controls the operation of each block so that a block in a later stage has priority. There is.

When the packet data 13 is output, the input interface block 1 outputs a signal (VALID-OUT1) indicating the effective range of the output data, and the FCS addition block 2 outputs the packet data 13 with FCS. When outputting, the signal (VALID-OUT2) indicating the effective range of the output data is output, and the insertion block 3 outputs this when outputting the packet data 13 with FCS inserted with "0". Signal indicating the effective range of data (VA
LID-OUT3) is output, and the flag addition block 4 outputs a signal (VALID-OU) indicating the valid range of the data to be output when outputting the FCS-added packet data 13 with the flag added and "0" inserted.
T4) is output.

The priority processing circuit 6 outputs the data when the output interface block 5 is serially outputting the data, and when the output destination, for example, the FIFO, cannot receive the data in a full flag state (a state in which it overflows when data is written any more). 5 receives this full flag state from the FIFO and outputs EN0 which is output as "0", and each of the input interface block 1, the FCS addition block 2, the insertion block 3 and the flag addition block 4 in the preceding stage of the output interface block 5 The operation of each block is stopped, and each block is set to the holding state for holding the state immediately before the stop.

Further, the priority processing circuit 6 receives the EN4 output as "0" from the flag addition block 4 while the flag addition block 4 is adding the flag, and receives the input interface in the stage prior to the flag addition block 4. The operation of each block of the block 1, the FCS addition block 2 and the insertion block 3 is stopped, and each of the blocks is brought into a holding state for holding the state immediately before the block is stopped.

Further, the priority processing circuit 6 receives the EN3 output as "0" from the insertion block 3 while the insertion block 3 is performing "0" insertion, and then the priority processing circuit 6 precedes the insertion block 3. The operation of a certain input interface block 1 and the FCS addition block 2 is stopped, and the states immediately before the blocks are stopped are held.

Further, the priority processing circuit 6 receives the EN2 output as "0" from the FCS addition block 2 while the FCS addition block 2 is performing the FCS addition, and receives the FC
The operation of the input interface block 1 in the preceding stage of the S addition block 2 is stopped so that the state immediately before the input interface block 1 is stopped is held.

In the priority processing circuit 6, the output interface block 5 adds a flag and inserts "0" into the packet data 13 with FCS (that is, HDLC).
When the frame 14) is not being output, the output interface block 5 outputs the data (that is, the HDLC frame 1).
When the output destination can receive this data in the case of outputting 4), when the flag addition block 4 does not perform flag addition, when the insertion block 3 does not perform "0" insertion, and when the FCS addition block is performed. 2 does not add FCS, that is, EN2
When EN3, EN4, and EN5 are all "1", the packet data 13 is in the empty state (a state in which data cannot be read from the FIFO) while the input interface block 1 is inputting the packet data 13 from the FIFO, for example. If the input interface block 1 is interrupted and detects this empty state from the FIFO and outputs EN1 as "0", this output E
In response to N1, the operation of each of the FCS addition block 2, the insertion block 3, the flag addition block 4 and the output interface block 5 in the subsequent stage of the input interface block 1 is stopped, and immediately before stopping these blocks. The holding state is maintained.

In FIG. 1, a FIFO for receiving the packet data 13 to be transmitted and serially transmitting the packet data 13 to the input interface block 1 and an output interface block 5 for outputting the HDLC frame 14 to the receiving line are output serially. 2 and a gate circuit (combination of AND circuit and OR circuit) as an example of the priority processing circuit 6 are also shown.

Next, the operation of the HDLC frame conversion circuit of this embodiment will be described in detail with reference to FIG.

FIG. 2 is a diagram showing the relationship between the output signals of the blocks shown in FIG.

In FIG. 1, the input interface block 1 stores packet data 13 (for example, data of an information portion desired to be transmitted, and an address portion and a control portion may be added to this data), for example, a FIFO. When the packet data 13 is serially input, the packet data 13 is serially output as DOUT1, and when the packet data 13 is output, a signal (VAL) indicating the effective range of the data to be output.
ID-OUT1) is output. Then, the input interface block 1 sends the packet data 13 to the FIFO, for example.
This FIFO is in the empty state (FIFO
When this packet data 13 is interrupted in a state where the data cannot be read out more), the empty state is set to FIFO.
The received EN1 is output as "0" from O. When not in the empty state, EN1 is output as "1". F
The CS addition block 2 is the input interface block 1
Then, the packet data 13 is serially input, and the packet data 13 is, for example, a cyclic redundancy check (hereinafter referred to as CRC) calculation result FC.
This FCS is performed by adding FCS indicating that S (for example, 2 bytes) is added to the end of the input packet data 13.
The attached packet data 13 (DOUT2) is serially output, and when output, a signal (VALID-OUT2) indicating the effective range of the output data is output. Then, when the FCS addition block 2 is performing FCS addition, EN2 is output as "0". When FCS addition is not performed, EN2 is output as "1". Insertion block 3 is F from FCS addition block 2.
The packet data 13 with CS is input serially and this F
A predetermined number of packet data 13 with CS (for example, 5
When the "1" bit continues, the "0" insertion indicating the insertion of the "0" bit after the predetermined number of "1" bits is performed and the "0" inserted FCS is performed. Attached packet data 13 (DOUT3)
Is serially output, and when output, a signal (VALID-OUT3) indicating the effective range of the output data is output. If a large number of "0" insertions occur, VALID-OUT3 is extended correspondingly. And
When the insertion block 3 is performing "0" insertion, EN3 is output as "0". "0"
EN3 is set to "1" when insertion is not performed.
Output as. A flag addition block 4 serially inputs the FCS-added packet data 13 inserted by "0" from the insertion block 3 and adds a flag indicating that a start flag and an end flag are added to the input data, and this flag is added. Packet data with FCS added with "0" inserted (DO
UT4) is output serially, and when output, a signal (VALID-OUT) indicating the effective range of the output data is output.
4) is output. Then, when the flag addition block 4 is performing flag addition, EN4 is output as "0". If no flag is added, set EN4 to "1".
Output as. The output interface block 5 adds the flag from the flag addition block 4 and inserts "0" into the packet data 13 with FCS (that is,
The HDLC frame 14) is serially input, and the input data is serially used as DOUT5, for example, a FIFO.
Output to. When a full flag state is received from the output destination, for example, the FIFO, while outputting this DOUT5, EN5
Is output as "0". When the full flag state is not received from the FIFO, EN5 is output as "1". The priority processing circuit 6 includes EN1 and EN of each functional block.
When 2, EN3, EN4, and EN5 simultaneously become “0”, the priority order is EN1 <EN2 <EN3 <EN4 <
The priority is set to EN5, and EN1 has the lowest priority and EN5 has the highest priority. For example, "0"
If the generation of an insertion and the addition of a flag are performed at the same time, the priority order is EN3 <EN4, and since the addition of the flag EN4 has a higher priority, the '0' insertion process is performed immediately after the flag addition process. Is done. Simultaneous processing in other functional blocks is similarly performed according to the priority order. Then, the priority processing circuit 6 outputs “0” from the output interface block 5 when the output interface block 5 is outputting data serially and the output destination, for example, the FIFO is in the full flag state.
In response to N5, "0" is output to each block of the input interface block 1, the FCS addition block 2, the insertion block 3 and the flag addition block 4 in the preceding stage of the output interface block 5, and the operation of each block is performed. It is made to stop and these blocks are made into the holding state which holds the state just before stopping. Then, when the full flag state of the FIFO is released, the output interface block 5 receives EN5 output as "1", and the output interface block 5 receives
Input interface block 1, FCS in the previous stage
"1" is output to each of the additional block 2, the insertion block 3 and the flag additional block 4, and each block operates from the state immediately before the holding state is released and the block is stopped. Further, the priority processing circuit 6 receives the EN4 output as "0" from the flag addition block 4 while the flag addition block 4 is performing the flag addition, and receives the input interface blocks 1 and 1 in the preceding stage from the flag addition block 4. By outputting "0" to each of the FCS addition block 2 and the insertion block 3, the operation of each block is stopped, and each block is brought into a holding state in which the state immediately before the block is stopped is held. There is. Then, when the flag addition is completed, the EN4 output as "1" from the flag addition block 4 is received, and the input interface block 1, the FCS addition block 2 and the insertion block 3 in the preceding stage to the flag addition block 4 are respectively received. Outputs "1", and each block operates from the state immediately before the retention state is released and the block is stopped. Further, the priority processing circuit 6 receives the EN3 output as "0" from the insertion block 3 while the insertion block 3 is performing "0" insertion, and receives the input interface in the stage preceding the insertion block 3. Stop the operation of block 1 and FCS addition block 2,
Each of these blocks is set to a holding state in which it holds the state immediately before being stopped. When the "0" insertion is completed, the insertion block 3 receives the EN3 output as "1", and the input interface block 1 and the FCS addition block 2 in the block preceding the insertion block 3 receive "1". Is output, and these blocks operate from the state immediately before the retention state is released and the block is stopped. Further, the priority processing circuit 6 is
F when the CS addition block 2 is performing FCS addition
Upon receiving EN2 output as "0" from the CS addition block 2, the operation of the input interface block 1 in the preceding stage of the FCS addition block 2 is stopped, and the state immediately before the input interface block 1 is stopped is held. I am trying to do it. When the FCS addition is completed, the FCS addition block 2 outputs "1" as E.
Upon receiving N3, "1" is output to the input interface block 1 in the preceding stage of the FCS addition block 2, and this input interface block 1 operates from the state immediately before the holding state is released and the operation is stopped. Further, the priority processing circuit 6 is
Output interface block 5 adds a flag to "0"
When the inserted FCS-attached packet data 13 (that is, the HDLC frame 14) is not being output, the output interface block 5 outputs data (that is, HDL).
In the case of outputting the C frame 14), when the output destination can receive this data, when the flag addition block 4 does not add the flag, the insertion block 3
0 "insertion is not performed and FCS addition block 2 is not performing FCS addition, that is, EN2, EN3, EN4 and EN5 are all" 1 ".
At this time, while the input interface block 1 is inputting the packet data 13 from the FIFO, for example, the FIFO is empty (the data cannot be read from the FIFO), the packet data 13 is interrupted, and the input interface block 1 is in the empty state. FIF
When EN1 is output as "0" by detecting from O, the output EN1 is received and the FCS addition block 2, the insertion block 3, the flag addition block 4, and the output interface block 5 in the subsequent stage of the input interface block 1 are received. The operation of each of the blocks is stopped, and each of the blocks is brought into a holding state for holding the state immediately before the stop. And FI
When the empty state of the FO is released, it receives EN1 output as "1" from the input interface block 1,
"1" is output to each block of the FCS addition block 2, the insertion block 3, the flag addition block 4 and the output interface block 5, which are in the subsequent stage of the input interface block 1, and each block is released from the holding state and stopped. Operates from the previous state.

FIG. 3 is a block diagram showing a second embodiment of the HDLC frame conversion circuit of the present invention.

The present embodiment shown in FIG. 3 is a high-level data link control procedure (hereinafter referred to as HD) having a plurality of bits.
It describes as LC. ) HDLC input by inputting a frame and inputting by a plurality of blocks each having a predetermined function
In an HDLC frame conversion circuit that processes a frame 14 and converts it into packet data 13 having a plurality of bits (data of an information part to be received, and an address part and a control part may be added to this data), HDLC
An input interface block 7 for serially inputting the frame 14 and serially outputting the HDLC frame 14 as DOUT1, and an input interface block 7
Further, the HDLC frame 14 is serially input, and the start flag indicating the start of the HDLC frame 14 and the end flag indicating the end of the HDLC frame 14 included in the input HDLC frame 14 are deleted and the flag is deleted. A flag deletion block 8 that serially outputs the flag-deleted HDLC frame 14 as DOUT2 and a flag deletion block 8 that serially inputs the flag-deleted HDLC frame 14 and a predetermined number of the flag-deleted HDLC frame 14 When the "1" bit of "0" is continued, "0" deletion indicating that the "0" bit after the predetermined number of "1" bits is deleted is performed, and the "0" deletion flag is set. DOUT the deleted HDLC frame 14
Deletion block 9 that outputs serially as 3
Then, the HDLC frame 14 with the "0" deleted and the flag deleted is serially input from the deletion block 9 and is included in the input data (for example, a cyclic redundancy check (hereinafter, referred to as CRC)) operation result. F) indicating that a frame check sequence (hereinafter, referred to as FCS) is deleted.
An FCS deletion block 10 for serially outputting the HDLC frame 14 in which CS deletion is performed, FCS is deleted, “0” is deleted, and a flag is deleted as DOUT4;
In the deletion block 9, the output interface block 11 for serially inputting the HDLC frame 14 in which the FCS is deleted from the CS deletion block 10 and the "0" deletion is performed and the flag is deleted is serially output as DOUT5. FC located after the deletion block 9 when performing 0 ”deletion
S deletion block 10 and output interface block 11
The operation is stopped and these blocks are controlled so as to be in a holding state in which the state immediately before being stopped is held. When the deletion block 9 does not perform "0" deletion, the output interface block 11 When the output destination cannot receive this data while outputting the data serially, the FCS deletion block 10, the deletion block 9, the flag deletion block 8 and the input interface block 7 in the preceding stage of the output interface block 11 are It is configured by a priority processing circuit that stops the operation and controls each of the blocks to be in a holding state that holds the state immediately before the block is stopped.

The flag deletion block 8 outputs a signal (VALID-OUT2) indicating the valid range of the data to be output when outputting the HDLC frame 14 from which the flag is deleted.
And the deletion block 9 outputs
When outputting the HDLC frame 14 with the deletion of 0 "and the flag deleted, a signal (VALID-OUT3) indicating the valid range of the output data is output, and the FCS deletion block 10 deletes the FCS to" 0 ". A signal (VALID-OUT4) indicating the valid range of the output data is output when outputting the HDLC frame 14 that has been deleted and the flag is deleted, and the output interface block 11 deletes the FCS and deletes "0". When outputting the HDLC frame 14 with the flag deleted, a signal (VALID-OUT5) indicating the effective range of the output data is output.

In FIG. 3, for example, a FIFO for receiving the HDLC frame 14 to be received from the line and serially receiving the HDLC frame 14 to the input interface block 7, and a packet data 13 from the output interface block 11 are serially received. Output FIFO
And a gate circuit (AND
Circuit and OR circuit combination).

Next, the operation of the HDLC frame conversion circuit of this embodiment will be described in detail with reference to FIG.

FIG. 4 is a diagram showing the relationship between the output signals of the blocks shown in FIG.

In FIG. 3, the input interface block 7 serially inputs the HDLC frame 14 from, for example, a FIFO, and inputs the HDLC frame 14 to DOUT1.
As serial output. The flag deletion block 8 is
HDLC frame 1 from input interface block 7
4 is serially input and this input HDLC frame 1
The flag indicating deletion of the start flag and the end flag included in No. 4 is deleted, and this flag is deleted.
The DLC frame 14 is serially output as DOUT2, and when the DOUT2 is output, a signal (VALID-OUT2) indicating the effective range of the output data is output. The deletion block 9 serially inputs the flag-deleted HDLC frame 14 from the flag deletion block 8 and deletes the flag from the HDLC frame 1
When a predetermined number (for example, 5) of "1" bits is continued to 4, "0" deletion indicating that the "0" bit following the predetermined number of "1" bits is deleted And delete this flag by deleting this "0" H
The DLC frame 14 is serially output as DOUT3, and when this DOUT3 is output, a signal (VALID-OUT3) indicating the effective range of the output data is output. Then, when the deletion block 9 is performing "0" deletion, EN3 is output as "0". EN when not performing "0" deletion
3 is output as "1". FCS deletion block 10
Deletes "0" from the deletion block 9 and serially inputs the HDLC frame 14 from which the flag has been deleted, and performs FCS deletion indicating that the FCS included in the input data is deleted. The HDLC frame 14 (that is, the packet data 13) from which the deletion is performed and the flag is deleted is serially output as DOUT4, and when the DOUT4 is output, a signal (VALID-OU) indicating the valid range of the output data is output.
T4) is output. Output interface block 11
Is serially input to the HDLC frame 14 in which the FCS has been deleted from the FCS deletion block 10 and the flag has been deleted, and the flag has been deleted. Is output, a signal (VALID-OUT) indicating the effective range of the output data is output.
5) is output. When a full flag state (a state of overflowing when writing more than this) is received from the output destination, for example, FIFO, while outputting this DOUT5, EN5
Is output as "0". When the full flag state is not received from the FIFO, EN5 is output as "1". In the priority processing circuit 12, EN3 and EN5 are simultaneously set to '
When it becomes 0 ', the priority is set to EN3> EN5, and EN3 has a higher priority. For example, if the generation of the '0' deletion and the detection of the full flag state from the FIFO operate at the same time,
The priority order is EN3> EN5, and since the “0” deletion has a higher priority, the “0” deletion process is immediately performed. The priority processing circuit 12 receives the EN3 output as “0” from the deletion block 9 while the deletion block 9 is performing “0” deletion, and receives the FCS deletion block 10 located after the deletion block 9. And output interface block 11
By outputting "0", the operation of these blocks is stopped, and each block is set to the holding state that holds the state immediately before the stop. And when the "0" deletion is completed, the deletion block is completed. From 9 "
In response to EN3 output as "1", "1" is output to each block of the FCS deletion block 10 and the output interface block 11 that are subsequent to the deletion block 9, and the respective blocks are released from the holding state and stopped. It operates from the state immediately before, and the priority processing circuit 12
When the deletion block 9 is not performing "0" deletion (when EN3 is "1"), the output interface block 11 is outputting data serially and the output destination FIFO cannot receive this data. When (F
When the IFO is in the full flag state), the output interface block 11 receives EN5 output as "0",
FCS in front of output interface block 11
"0" is output to each block of the deletion block 10, the deletion block 9, the flag deletion block 8 and the input interface block 7 to stop the operation of each block, and the state immediately before stopping these blocks is retained. Each is set to the holding state. Then, when the full flag state of the FIFO is released, the output interface block 11 outputs EN5 as "1", receives the output EN5, and receives the output EN5.
In each block of the deletion block 9, the flag deletion block 8 and the input interface block 7,
1 "is output, and each block operates from the state immediately before the retention state is released and the block is stopped.

[0032]

As described above, the HDLC of the present invention
According to the frame conversion circuit, the packet data is HDLC
When converting to a frame, the input interface block inputs the packet data, the FCS addition block receives the packet data from the input interface block and adds FCS, and the insertion block inputs the FCS addition packet data from the FCS addition block. "0" insertion is performed, the flag addition block inputs the packet data with FCS inserted by "0" from the insertion block, the start flag and the end flag are added to make an HDLC frame, and the output interface block makes an HDLC frame. Is output. Then, the priority processing circuit controls the operation of each block of the input interface block, the FCS addition block, the insertion block, the flag addition block, and the output interface block so that the blocks in the later stages are preferentially performed. When converting an HDLC frame into packet data, the input interface block inputs the HDLC frame, the flag deletion block inputs the HDLC frame from the input interface block, deletes the start flag and the end flag, and deletes the deletion block. Therefore, the HDLC frame from which the flag has been deleted is input from the flag deletion block, and "0" deletion is performed.
The FCS deletion block inputs the HDLC frame that has been deleted by "0" from the deletion block and deletes the flag to delete the FCS, and the output interface block outputs the packet data. When the 0 "deletion is being performed, the F that follows the deletion block
When the deletion block does not perform "0" deletion by controlling the operations of the CS deletion block and the output interface block so that they are held in the states immediately before they are stopped. When the output interface block is outputting data serially and the output destination cannot receive this data,
The operation of each of the FCS deletion block, the deletion block, the flag deletion block, and the input interface block, which precedes the output interface block, is stopped, and each of the blocks is brought into a holding state in which it retains the state immediately before being stopped. To control. For this reason, if the data to be converted is input to this conversion circuit, the conversion result can be obtained without interaction between this conversion circuit and the outside of this conversion circuit. Therefore, packet data to be transmitted as an HDLC frame is input from the outside. Output to the line or received data from the line (HDLC frame)
The processing speed until the packet data is passed to the outside is not slowed down, and the performance of the processor outside the conversion circuit is not deteriorated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an HDLC frame conversion circuit of the present invention.

FIG. 2 is a diagram showing a relationship of output signals of respective blocks in FIG.

FIG. 3 is a block diagram showing a second embodiment of the HDLC frame conversion circuit of the present invention.

FIG. 4 is a diagram showing a relationship of output signals of each block in FIG.

[Explanation of symbols]

1 Input interface block 2 FCS additional block 3 Insertion block 4 Flag addition block 5 Output interface block 6 Priority processing circuit 7 Input interface block 8 flag deletion block 9 deletion block 10 FCS deletion block 11 Output interface block 12 Priority processing circuit 13 packet data 14 HDLC frame

Claims (9)

(57) [Claims] 1. A high level data link control procedure (hereinafter referred to as HDLC) by inputting packet data having a plurality of bits and processing the inputted packet data by a plurality of blocks each having a predetermined function. ) In an HDLC frame conversion circuit for converting into a frame, an input interface block for serially inputting the packet data and outputting this packet data serially, and inputting the packet data serially from the input interface block to a frame for the packet data An FCS addition block that performs FCS addition indicating that a check sequence (hereinafter referred to as FCS) is added and serially outputs this FCS-added packet data, and the FCS-added packet data from the FCS addition block. "0" indicating that a "0" bit is inserted after this predetermined number of "1" bits when a predetermined number of "1" bits continue in the packet data with FCS. "Insert and do this" 0 "
An insertion block for serially outputting the inserted packet data with FCS, and serially inputting the "0" inserted packet data with FCS from the insertion block and starting the data with this input data. A flag addition block for adding a start flag shown and an end flag showing the end of this data, and adding this flag and outputting the "0" inserted packet data with FCS serially; The flag is added from the flag addition block
An output interface block for serially inputting the 0 ”insertion packet data with FCS and serially outputting the input data, and the input interface block, the FCS addition block, the insertion block, the flag addition block, and the An HDLC frame conversion circuit, comprising: a priority processing circuit that controls the operation of each block of the output interface block so that the block in the subsequent stage has priority. 2. When the packet data is output, the input interface block that outputs a signal indicating the effective range of the data to be output, and the effective range of the data to be output when the packet data with FCS are output are set. The FC that outputs a signal indicating
S addition block, the insertion block that outputs a signal indicating the valid range of the output data when outputting the packet data with FCS inserted by the "0", and the flag by adding "0" The HDLC frame conversion circuit according to claim 1, further comprising: the flag addition block that outputs a signal indicating a valid range of the output data when the inserted packet data with FCS is output. 3. The priority processing circuit, wherein when the output interface block is outputting the data serially and the output destination cannot receive the data, the input interface block in a stage preceding the output interface block, The operation of each of the FCS-added block, the insertion block, and the flag-added block is stopped, and each of these blocks is placed in a holding state for holding the state immediately before the stopping. The HDLC frame conversion circuit according to claim 1. 4. The priority processing circuit, when the flag addition block is performing the flag addition, each of the input interface block, the FCS addition block, and the insertion block in a stage preceding the flag addition block. Stop the operation of the block
The HDLC frame conversion circuit according to claim 1, 2 or 3, wherein each of the blocks is set to a holding state for holding the state immediately before the stop. 5. The priority processing circuit, when the insertion block is performing the "0" insertion, performs the operation of the input interface block and the FCS addition block in the preceding stage of the insertion block. The HDLC frame conversion circuit according to claim 1, 2, 3 or 4, wherein the blocks are stopped and each of the blocks is set to a holding state for holding the state immediately before the stopping. 6. The priority processing circuit, when the FCS addition block is performing the FCS addition,
The operation of the input interface block in the preceding stage of the S addition block is stopped, and the input interface block is brought into a holding state for holding the state immediately before the stop. 4. The HDLC frame conversion circuit described in 4 or 5. 7. The priority processing circuit is configured such that when the output interface block is not outputting the packet data with FCS added with the flag and the "0" insertion, the output interface block is outputting the data. In this case, when the output destination can receive this data, when the flag addition block does not perform the flag addition, when the insertion block does not perform the "0" insertion, and when the F
If the packet data is interrupted while the input interface block is inputting the packet data when the CS addition block is not performing the FCS addition, the FCS at the subsequent stage of the input interface block
The operation of each block of the additional block, the insertion block, the flag addition block, and the output interface block is stopped, and each of these blocks is brought into a holding state for holding the state immediately before the stopping. The HDLC frame conversion circuit according to claim 6. 8. A high-level data link control procedure (hereinafter referred to as HDLC) frame having a plurality of bits is input, and the input HDLC frame is processed by a plurality of blocks each having a predetermined function. HD for converting to packet data with multiple bits
In the LC frame conversion circuit, the HDLC frame is serially input and
An input interface block that outputs a frame serially, a start flag that serially inputs the HDLC frame from the input interface block and that indicates the start of an HDLC frame included in the input HDLC frame, and an end that indicates the end of this HDLC frame. And a flag deletion block that deletes the flag indicating that the flag has been deleted and serially outputs the HDLC frame from which the flag has been deleted, and the HDLC frame from which the flag has been deleted from the flag deletion block that is serially input to this flag "0" deletion indicating that when a predetermined number of "1" bits continues in the deleted HDLC frame, a "0" bit following the predetermined number of "1" bits is deleted Do this "0" Delhi And a deletion block for serially outputting the HDLC frame with the flag deleted, and the HDLC frame with the "0" deletion and the flag deleted, serially input from the deletion block to the input data. The FCS deletion indicating that the included frame check sequence (hereinafter referred to as FCS) is deleted is performed, and the FCS is deleted.
The HDLC with 0 "deletion and the flag removed
The FCS deletion block that outputs a frame serially, and the FCS deletion block that deletes the FCS from the FCS deletion block
The HDLC with 0 "deletion and the flag removed
An output interface block that serially inputs a frame and serially outputs the input data; and an FCS deletion block that is located after the deletion block when the "0" deletion is performed in the deletion block. And the output interface block are stopped, and these blocks are controlled so as to be in a holding state for holding the state immediately before the stop, and the deletion block performs the "0" deletion. If the output interface block is not outputting the data while the output interface block is outputting the data serially when there is no such data, the FCS in the preceding stage to the output interface block
The operation of each block of the deletion block, the deletion block, the flag deletion block, and the input interface block is stopped, and these blocks are controlled to be in a holding state that holds the state immediately before the stop. An HDLC frame conversion circuit, comprising: a priority processing circuit. 9. The flag deletion block that outputs a signal indicating the effective range of the output data when outputting the HDLC frame in which the flag is deleted; and the deletion of the flag by performing the “0” deletion. H
When outputting the DLC frame, when outputting the deletion block that outputs a signal indicating the effective range of the data to be output, and when outputting the HDLC frame in which the FCS is deleted, the "0" is deleted, and the flag is deleted. The F that outputs a signal indicating the effective range of the data to be output
A CS deletion block; and an output interface block that outputs a signal indicating a valid range of the output data when the HDLC frame in which the FCS is deleted, the "0" is deleted, and the flag is deleted is output. The HDLC frame conversion circuit according to claim 8, wherein