JP3421988B2 - Display device and method for preventing influence of interference between clocks used therein - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of preventing the influence of inter-clock interference used in the display device, and more particularly to a method of preventing the influence of inter-clock interference in a liquid crystal monitor.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal monitor device, as shown in FIG.
As shown in, the video input terminal 1, the synchronization input terminal 2,
A / D (analog / digital) converter 3, clock generators 4, 13 and 14, a signal processor 5, a timing generator 7, a display device (liquid crystal monitor) 8, a memory 9, a CPU ( Central processing unit) 10.

The A / D converter 3 performs A / D conversion on the video signal input from the video input terminal 1, and the signal processing unit 5 performs A / D conversion.
For the signal A / D converted by the converter 3, "conversion from input resolution to display resolution", "gamma correction", "D / A"
“Conversion” and “signal amplification” are performed and output to the display device 8.

The A / D converter 3 receives a sync signal input from the sync input terminal 2 from the sync signal in the PLL (Ph
A / D conversion is performed using a clock signal generated by using an as Locked Loop circuit (not shown).

After the signal processing unit 5 receives the data from the A / D converter 3 in synchronization with the clock signal from the clock generation unit 4 and performs resolution processing in synchronization with the clock signal generated by the clock generation unit 13. Of the data is output to the display device 8.

The clock generator 14 supplies a clock signal for operating the CPU 10, and the CPU 10 and CP
The interfaces of the memory 9 and the signal processing unit 5 connected to the U bus are driven.

In the conventional circuit described above, when the signal processing unit 5 mixes the clock signal components of the clock generating units 13 and 14 with the video signal before A / D conversion, when the clock generating unit 4 performs sampling. Therefore, interference fringes due to mutual interference will be superimposed on the image. Even if the clock signal frequency is as high as several tens of megahertz, this interference fringe can be confirmed as the interference fringe.

[0008]

In the above-mentioned conventional display device, when two or more clock signals are provided, decoupling is performed by a substrate, a spatial shield plate or the like in order to prevent the interference of the clock signals.

In the above display device, "beat noise (interference fringe)" is caused by using the plurality of clock signals.
May appear on the screen, and this is the biggest cause of failure when developing a device such as a liquid crystal projector, a plasma display, or a liquid crystal monitor that handles input signals and output signals with different clocks.

Therefore, an object of the present invention is to solve the above problems and to prevent the influence of the interference between clocks used in a display device capable of fundamentally avoiding the interference even if clock interference occurs. It is to provide a prevention method.

[0011]

A display device according to the present invention uses a sampling clock signal for sampling an input signal and a plurality of clock signals generated separately from the sampling clock signal to perform signal processing and device control processing. And a means for applying frequency modulation to each of the plurality of clock signals , wherein the means for applying frequency modulation is a pseudo- laser.
Random noise is generated and the noise causes
Of the clock signals are modulated.

A method of preventing an influence of inter-clock interference of a display device according to the present invention uses a sampling clock signal for sampling an input signal and a plurality of clock signals generated separately from the sampling clock signal, thereby performing a signal processing and device. Is a method of preventing the influence of inter-clock interference of a display device that constitutes a system for performing the control processing of the above , wherein frequency modulation is applied to each of the plurality of clock signals, and the frequency modulation is a pseudo random noise.
Noise, and the noise causes the multiple clock signals to
This is done by modulating the frequency of each signal .

That is, the display device of the present invention includes a clock signal generated according to an input video signal (RGB signal or television signal from a computer),
Having one or more clock signals with different frequencies prepared separately, the effect on the video signal appearing in the form of interference fringes due to these interferences can be appropriately modulated with the separately prepared clock signals with different frequencies. When applied, the interference fringes are diffused so that they cannot be recognized as images.

Conventionally, in a display device having two or more clock signals, decoupling is performed by a substrate, a spatial shield plate, or the like in order to prevent the influence of the interference of the clock signals. It is possible to reduce the size, and it is possible to contribute to downsizing and cost reduction of the device. Therefore, even if the influence of clock interference occurs due to some circumstances (for example, a mistake in wiring work in manufacturing), it is possible to fundamentally diffuse and avoid it.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a display device according to an embodiment of the present invention. 1, a display device according to an embodiment of the present invention is provided with a modulation signal generator 12, and clock generators 6 and 11 are provided instead of the clock generators 13 and 14, respectively, and the conventional display device shown in FIG. The configuration is the same as the above, and the same components are denoted by the same reference numerals. The operation of the same constituent element is similar to that of the conventional example.

The A / D converter 3 performs A / D conversion on the video signal input from the video input terminal 1, and the signal processing unit 5 performs A / D conversion.
For the signal A / D converted by the converter 3, "conversion from input resolution to display resolution", "gamma correction", "D / A"
“Conversion” and “signal amplification” are performed and output to the display device (liquid crystal monitor) 8.

The A / D converter 3 receives a synchronization signal input from the synchronization input terminal 2 from a PLL (Ph
A / D conversion is performed using a clock signal generated by using an as Locked Loop circuit (not shown).

After the signal processing unit 5 receives the data from the A / D converter 3 in synchronization with the clock signal from the clock generation unit 4 and performs resolution processing in synchronization with the clock signal generated by the clock generation unit 6. Of the data is output to the display device 8.

The clock generator 11 supplies a clock signal for operating the CPU 10, and the CPU 10 and CP
The interfaces of the memory 9 and the signal processing unit 5 connected to the U bus are driven.

The modulation signal generator 12 includes a clock generator 6,
A modulation signal for modulating the frequency of the clock signal generated at 11 is generated. The clock generators 6 and 11 have a VCO (Vol) whose frequency varies depending on the voltage of the input signal.
target Controlled Oscilato
r: voltage controlled oscillator) circuit (not shown) is prepared.

The modulation signal generator 12 generates pseudo random noise, and the generated noise modulates the frequency of the clock signal generated from the clock generators 6 and 11.

As a result, even if the clock signal components of the clock generators 6 and 11 are mixed in the video signal before A / D conversion in the signal processing unit 5, the components are diffused by pseudo random noise. As a result, interference fringes cannot be confirmed at certain places.

Therefore, in one embodiment of the present invention, conventionally, in addition to the clock signal for sampling the input signal,
In a display device having one or a plurality of clock signals, the influence of the interference of the clock signals can be avoided from the display screen, and the device can be configured without adding various parts. Therefore, the number of parts of the device can be reduced, and the cost can be reduced.

[0024]

As described above, according to the present invention, a system for performing signal processing and device control processing using a sampling clock signal for sampling an input signal and a clock signal generated separately from the sampling clock signal. In the display device configured as described above, by performing frequency modulation on the clock signal, even if clock interference occurs, it is possible to fundamentally diffuse and avoid the interference.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a display device according to a conventional example.

[Explanation of symbols]

1 Video input terminal 2 Sync input terminal 3 A / D converter 4, 6, 11 Clock generator 5 Signal processor 7 Timing generator 8 display devices 9 memory 10 CPU 12 Modulation signal generator

Continuation of the front page (56) Reference JP-A-11-133906 (JP, A) JP-A-11-284579 (JP, A) JP-A-8-137437 (JP, A) JP-A-2000-338932 (JP, A) JP-A-63-310058 (JP, A) JP-A-9-101835 (JP, A) JP-A-6-241851 (JP, A) JP-A-6-250755 (JP, A) JP-A-4 −310699 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3/00-5/42 G06F 1/04

Claims (4)

(57) [Claims] 1. A display device that constitutes a system for performing signal processing and device control processing using a sampling clock signal for sampling an input signal and a plurality of clock signals generated separately from the sampling clock signal. , have a means for applying a frequency modulation to said plurality of clock signals respectively, subjecting said frequency modulation means
Generates pseudo-random noise and
To modulate the frequency of each of the plurality of clock signals.
A display device characterized by being configured . 2. A circuit for generating said plurality of clock signals, a display device according to claim 1, characterized in that it comprises a voltage controlled oscillator whose frequency is varied by the voltage of the input signal. 3. A clock of a display device constituting a system for performing signal processing and device control processing using a sampling clock signal for sampling an input signal and a plurality of clock signals generated separately from the sampling clock signal. A method of preventing the influence of interference , wherein frequency modulation is applied to each of the plurality of clock signals, and the frequency modulation generates pseudo random noise.
Generated by the noise, each of the plurality of clock signals
A method for preventing the influence of inter-clock interference, which is performed by modulating the frequency . 4. The effect of inter-clock interference according to claim 3, wherein the plurality of clock signals are generated from a circuit including a voltage controlled oscillator whose frequency varies depending on the voltage of the input signal. Method.