JP3420700B2 - Code synchronization acquisition circuit for spread spectrum signal - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code synchronization acquisition circuit for a direct sequence spread spectrum communication (DS-SS) receiver.

[0002]

2. Description of the Related Art There is a direct spread spectrum communication system as a communication system excellent in interference resistance and noise resistance. In this system, an information signal is spread by a spreading code having a wider band than this signal and communication is performed, but the receiving side must synchronize this spreading sequence.

As a conventional code synchronization acquisition technique, a correlation filter is used to obtain a correlation output, the correlation output is stored in a memory, and the maximum one is selected to obtain the code timing. There is. However, the above-described method has a drawback that a matched filter must be handled for each sample, which causes an increase in circuit scale and calculation amount.

On the other hand, as another conventional code synchronization acquisition technique, there is a method of obtaining a correlation output using a matched filter corresponding to a spread code and comparing the correlation output with a threshold value instantaneously to detect the code timing. .

However, according to this method, in the case of detecting a received signal in the case where there is a transmission line fluctuation such as fading,
There is a drawback that the synchronization acquisition characteristic becomes very bad.

[0006]

The receiving apparatus using the above-mentioned conventional code synchronization acquisition technique has the following problems.

In the conventional method of obtaining a code output by obtaining a correlation output by using a matched filter corresponding to a spread code, storing this output in a memory, and selecting the maximum of these outputs, the matched output for each sample is used. There is a problem that a filter must be dealt with, which causes an increase in circuit scale and calculation amount.

On the other hand, in the method of obtaining the correlation output using the matched filter corresponding to the spread code and instantaneously comparing the correlation output with the threshold value to detect the code timing,
In the case of detecting a received signal when there is a transmission line fluctuation such as fading, there is a problem that the synchronization acquisition characteristic becomes extremely poor.

The present invention has been made to solve the above problems, and an object thereof is to provide a code synchronization acquisition circuit for spread spectrum signals which can reduce the circuit scale and the amount of calculation.

Another object of the present invention is to provide a code synchronization acquisition circuit for a spread spectrum signal which can reduce the circuit scale and the amount of calculation without significantly degrading the synchronization acquisition characteristics.

Further, according to the present invention, for a received signal whose signal amplitude temporally fluctuates due to the influence of fading or the like,
An object of the present invention is to provide a code synchronization acquisition circuit for spread spectrum signals that can reduce the processing time for synchronization acquisition.

[0012]

In order to achieve the above object, a code synchronization acquisition circuit for a spread spectrum signal according to the invention of claim 1 is a code synchronization for performing synchronization acquisition of a spread code of a direct spread spectrum spread signal. In the capture circuit, an antenna for receiving a direct spread spectrum signal, an RF receiving section for frequency-converting the signal received by the antenna to obtain a baseband signal, and a baseband signal obtained by the RF receiving section An AD converter that obtains a discrete received signal by sampling the signal, a matched filter that despreads the discrete received signal obtained by the AD converter with a spreading code,
An integrator that integrates the squared value of the amplitude of the output signal of the matched filter for each period obtained by equally dividing the period of the spreading code sequence into a predetermined number, and holds the integration result for each divided period obtained by the integrator. And holding means and peak determining means for determining the code timing based on the content held by the holding means.

The code synchronization acquisition circuit for spread spectrum signals of the present invention integrates the output power value of the matched filter for one cycle of the spread code sequence for each period in which the cycle of the spread code sequence is equally divided into a predetermined number of 2 or more. However, by determining the code timing based on the integrated value for each divided period, both the amount of memory used and the amount of calculation can be reduced, and the circuit configuration can be simplified.

Further, according to the present invention, as described in claim 2, the code timing is judged based on the result of cumulative addition of the integration result for each divided period obtained by the integrator over a plurality of cycles of the spread code sequence. By doing so, it is possible to improve the deterioration of the synchronization acquisition characteristic due to the fading fluctuation and reduce the time required for the synchronization acquisition.

Further, according to the present invention, as described in claim 3, the code timing is obtained from the result of synthesizing the integrated values obtained for each divided period with respect to the output power values of the matched filters of the plurality of antenna branches. As described above, the deterioration of the synchronization acquisition characteristic due to the fading fluctuation can be improved, and the time required for the synchronization acquisition can be reduced.

Further, according to the present invention, as described in claim 4, the discrete received signal is inversed by using a plurality of matched filters each having a code coefficient of a different part divided from the spread code code as a tap coefficient. By spreading, the correlation processing for one cycle can be performed in the time of 1 / n cycle of the spread code sequence, and the calculation time can be shortened.

Further, according to the present invention, as described in claim 5, the divided period in which the output power value of the matched filter exceeds the threshold value is determined, and the determination result is held for a predetermined number of spreading code sequence periods. However, by determining the code timing based on the held contents, it is possible to improve the deterioration of the synchronization acquisition characteristic due to the fading fluctuation, as in the above invention,
The time required for synchronization acquisition can be reduced.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a code synchronization acquisition circuit for spread spectrum signals according to a first embodiment of the present invention.

As shown in the figure, the code synchronization acquisition circuit includes an antenna 10 for receiving a DS-SS signal, an RF receiver 11 for frequency-converting the signal received by the antenna 10 into a baseband signal, and a base. AD for sampling a band signal to generate a discrete reception baseband signal
Matched filter (MF) for despreading the discrete reception signal output from the converter 12 and the AD converter 12 with a spreading code
13, a signal power integrator 14 that integrates the power value of the correlation output from the matched filter 13 for a certain period, a timing generator 15 that generates a timing signal in the integration period of the signal power integrator 14, and a signal power integrator 14 A memory 16 that holds the integration result of 1 in the integration cycle and a peak determination unit 17 that determines the timing of the correlation peak based on the content stored in the memory 16 and determines the code timing.

Next, the operation of the code synchronization acquisition circuit will be described.

The DS-SS signal received by the antenna 10 is frequency-converted by the RF receiving section 11 into a baseband signal, and this baseband signal is AD.
The converter 12 samples and outputs a discrete reception baseband signal.

The matched filter (MF) 13 has a spreading code for synchronization acquisition as a tap coefficient, despreads the received baseband signal output from the AD converter 12, and outputs the result at each sample timing. The signal power integrator 14 integrates the power value of the correlation output from the matched filter 13 at regular intervals and outputs the integration result.
The integration period is determined by the timing signal of the timing generator 15. The output of the signal power integrator 14 is held in the memory 16 at each timing. The peak determination unit 17 determines the timing of the correlation peak based on the content stored in the memory 16 and determines the code timing.

The operation of the signal power integrator 14 will be described in more detail with reference to FIG.

FIG. 2 shows the output of the matched filter 13 over the spread code repetition period (or the repetition period of symbols spread by a specific code) T. Since the matched filter 13 calculates the correlation value between the received signal and the spread code, when the received signal includes signals from a plurality of transmitters or signals due to multipath, for example, a plurality of correlations as shown in FIG. Get the despread result with peaks.

The signal power integrator 14 integrates the output power value of the matched filter 13 every fixed integration period w,
The integrated value is output as a representative value for that period (block). The timing of the integration period w is specified by the timing generator 15. The timing generator 15 sets the cycle T of the spread code sequence to K (where K is a predetermined number of 2 or more).
The timing to be given to the signal power integrator 14 is generated such that the period equally divided into individual pieces is set as the integration period w.

In the block (for example, block 2) corresponding to the timing when the output of the matched filter 13 reaches the correlation peak, the power integrated value also becomes high. Therefore, the power integrated value for each block from the signal power integrator 14 is stored in the memory 1
6, the code timing can be estimated by determining a block having a large power integral value from the stored contents of the memory 16.

By adopting such a configuration, the memory 16
Can be suppressed to a value corresponding to the number of divided periods for one cycle of the spread code sequence, and the configuration of the receiver can be simplified. At the same time, it is possible to reduce the number of comparison operations when selecting a memory having a large memory content, so that it is possible to reduce the size and power consumption of the receiving device.

In the process of FIG. 2, the code timing is estimated at the cycle T of the spreading code sequence. However, as shown in FIG. 3, the power integrated values of each period are synchronously added over a plurality of cycles of the spreading code sequence. Alternatively, the code timing may be estimated from the cumulative addition result. That is, this is to calculate the power integral value of each block over one period T of the spread code sequence, record the result in the memory 16, and to calculate the power integral value of each block for the next period T for the past of the same block. Add to the power integrated value on the memory 16,
In this method, the code timing is estimated based on the added value of N × period T. By this method, it is possible to reduce the influence of generation and attenuation of an instantaneous correlation peak due to noise, fading, etc., and it is possible to improve the synchronization acquisition characteristic.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a diagram showing the configuration of a code synchronization acquisition circuit for spread spectrum signals according to the second embodiment.

The code synchronization acquisition circuit of the present embodiment is a DS-
Multiple antennas 4 for receiving SS signals as multiple signals
0-1, 40-2 and R provided for each antenna branch
F receivers 41-1 and 41-2, AD converters 42-1 and 42-2,
The matched filters 43-1 and 43-2, the signal power integrators 44-1 and 44-2, the adder 48 that combines the outputs of the signal power integrators 44-1 and 44-2, and the timing generator 45.
And a memory 46 and a peak determination section 47.

In this code synchronization acquisition circuit, the DS-SS signals received by the antennas 40-1 and 40-2 are respectively RF receiving sections 41-1 and 41-2 for each antenna branch.
Are frequency-converted into baseband signals, sampled by the AD converters 42-1 and 42-2, and converted into discrete reception baseband signals, which are sent to the matched filters 43-1 and 43-2.

The matched filters 43-1 and 43-2 despread the received baseband signal for each antenna branch,
The result is signal power integrator 44 for each sample timing.
-1, 44-2 is output. Signal power integrators 44-1 and 44-2
Integrates the power value of the correlation output from the matched filters 43-1 and 43-2 at regular intervals. Note that the timing generator 45 operates during the integration period of these signal power integrators 44-1 and 44-2.
Of the timing signal. The timing generator 45 equalizes the period T of the spreading code sequence into K (where K is a predetermined number equal to or greater than 2) and sets the signal power integrators 44-1 and 44-2 as the integration period w. Generate timing to give to.

The power integrated values obtained by the signal power integrators 44-1 and 44-2 are combined by the adder 48, and the combined power integrated values are stored in the memory 46. The peak determination unit 47 determines the timing of the correlation peak based on the content held in the memory 46 and estimates the code timing.

With the above-mentioned structure, it is possible to reduce the influence of the occurrence and attenuation of the instantaneous correlation peak due to noise, fading, etc., and it is possible to improve the synchronization acquisition characteristic.

Next, a third embodiment of the present invention will be described.

FIG. 5 is a diagram showing the structure of the code synchronization acquisition circuit for the spread spectrum signal of this embodiment.

The code synchronization acquisition circuit of this embodiment has a DS-
Multiple antennas 5 for receiving SS signals as multiple signals
0-1, 50-2 and RF provided for each antenna branch
Receivers 51-1 and 51-2 and AD converters 42-1 and 42-2
A switch 58 for switching the outputs of the AD converters 42-1 and 42-2, a matched filter 53, a signal power integrator 54, a timing generator 55, a memory 56, and a peak determination section 57. Is configured.

In this code synchronization acquisition circuit, the DS-SS signals received by the antennas 50-1 and 50-2 are respectively RF receiving sections 51-1 and 51-2 for each antenna branch.
Is converted to a base band signal by the AD converters 52-1 and 52-2, and is converted into a discrete reception base band signal by the switch 5
8 is output.

The switch 58 switches the antenna branch connected to the matched filter 53 at intervals equal to or longer than the period T of the spread code sequence. Matched filter 53
Despreads the received baseband signal selected by the switch 58 and outputs the result to the signal power integrator 54 at each sample timing. The signal power integrator 54 integrates the power value of the correlation output from the matched filter 53 every fixed period w.

The power integrated value for each divided period obtained by the signal power integrator 54 is cumulatively added to the power integrated value already recorded in the memory 56. Peak determination unit 57
Evaluates the timing of the correlation peak based on the cumulative addition value of N × period T held in the memory 46 and estimates the code timing.

With the above-mentioned configuration, the influence of the instantaneous generation or attenuation of the correlation peak due to noise, fading, etc. can be achieved with a smaller number of matched filters as compared with the code synchronization acquisition circuit of the embodiment shown in FIG. A code synchronization acquisition circuit that can be reduced can be realized.

Next, a fourth embodiment of the present invention will be described.

FIG. 6 is a diagram showing the configuration of a code synchronization acquisition circuit for spread spectrum signals according to the fourth embodiment.

As shown in the figure, this code synchronization acquisition circuit includes an antenna 60 for receiving a DS-SS signal, an RF receiver 61, an AD converter 62, and different parts divided from a spread code sequence. A plurality of matched filters 63-1 to 63-4 each having the code sequence as a tap coefficient, and a plurality of signal power integrators 64-1 to 64-4 that integrate the output power values of the respective matched filters for a certain period, The timing generator 65, the memory 66, and the peak determination unit 67 are provided.

In this code synchronization acquisition circuit, the DS-SS signal received by the antenna 60 is fed to the RF receiver 6
Each of the matched filters 63-1 is frequency-converted into a baseband signal by 1 and further sampled by the AD converter 62 into a discrete reception baseband signal.
It is output in parallel to ~ 63-4.

Each of the matched filters 63-1 to 63-4 has a sequence (partial sequence) of different parts divided from the spread code sequence as a tap coefficient, and the sampled received baseband signal is its own partial sequence. , And outputs the despread result to the corresponding signal power integrators 64-1 to 64-4 at the sample timing.

Each of the signal power integrators 64-1 to 64-4 integrates the power value of the correlation output from the corresponding matched filter 63-1 to 63-4 for a certain period. The timing generator 6 operates during the integration period of each signal power integrator 64-1 to 64-4.
5 timing signals. The timing generator 65 sets the cycle T of the spreading code sequence to K (where K is 2
The timing is given to the signal power integrators 64-1 to 64-4 so that the period equally divided into the above predetermined number) is set as the integration period w.

The integration results of the signal power integrators 64-1 to 64-4 are held in the memory 66 for each integration cycle. The peak determination unit 67 determines the timing of the correlation peak based on the content held in the memory 66 and estimates the code timing.

Details of this operation will be described with reference to FIG.

Here, an example is shown in which the spreading code sequence is divided into four partial sequences, but the same effect can be obtained even if the number of partial sequences is other than four.

Each matched filter (MF1, MF2, M
Since F3, MF4) 63-1 to 63-4 have different partial sequences, when a received signal is input, the despreading results for a part of the spreading sequence are output in parallel at different timings. These matched filters 63-1 to
The output of 63-4 is power-integrated in parallel by the signal power integrators 64-1 to 64-4 and stored in the area of the memory 66 corresponding to the timing of each partial sequence. Therefore, in this example, as shown in FIG. 7B, the signal power integral values corresponding to the matched filters 63-1 to 63-4 are stored in four different memory areas.

By performing this process, the spread code sequence 1
Since it is possible to realize the same processing as performing the correlation processing for one cycle in the time of / 4 cycle, it is possible to reduce the time required for the calculation, particularly in the case of a spread signal having a long code repetition cycle. .

Next explained is the fifth embodiment of the invention.

FIG. 8 is a diagram showing the configuration of the code synchronization acquisition circuit of the fifth embodiment.

As shown in the figure, this code synchronization acquisition circuit has an antenna 70 for receiving a DS-SS signal, an RF receiver 71, an AD converter 72, and a matched filter 73.
And a squarer 74 that squares the output of the matched filter 73.
A threshold value determination unit 75 that compares the output of the squarer 74 with a threshold value, a memory 76 that holds the result of the threshold value determination, and the estimation of the code timing based on the content stored in the memory 76. A code timing detection period selection unit 77 that determines a period for performing the following, and a peak determination unit 78 that determines the timing of the correlation peak by narrowing down the period determined by the code timing detection period determination unit 77 and estimates the code timing. It is equipped with.

In this code synchronization acquisition circuit, the DS-SS signal received by the antenna 70 is frequency-converted by the RF receiving section 71 into a baseband signal, further sampled by the AD converter 72, and discretely received. It becomes a baseband signal and is output to the matched filter 73. The matched filter 73 despreads the received baseband signal output from the AD converter 72 and introduces the result into the squarer 74. The squarer 74 squares the output from the matched filter 73 and introduces it to the threshold value determination unit 75. The threshold determination unit 75 compares the signal power value obtained through the squarer 74 with a preset threshold, and updates the contents of the memory 76 as follows based on the comparison result.

In FIG. 9, T is the period of the spreading code sequence,
P indicates the start position of the spread code sequence, and w indicates each period in which T is divided into K. As shown in FIG. 10, a memory area corresponding to each of the K number of periods w is secured in the memory 76.

FIG. 11 shows the procedure of the updating process of the memory 76.
Shown in. First, in step 111, the threshold value determination unit 7
At 5, the signal power value obtained by the squarer 74 is compared with a preset threshold value, and if a signal power value exceeding the threshold value is detected within the period w, the signal power value 1 is added to the value already recorded in the corresponding memory area (step 112). This operation is repeated for a predetermined number (N) of cycles T of the spread code sequence (step 113). However, if there is a period w in which a signal power value exceeding the threshold value is not detected within this N * T period, the value of the memory area corresponding to the period w is cleared to 0 (step 11).
4).

After the memory update for the period T × N is completed,
The code timing detection period selection unit 77 checks the value of each memory area corresponding to each period, detects a memory area having a value of N from them (step 115), and details the period w corresponding to this memory area. It is selected as a period for estimating the code timing (step 116).

After that, the peak determining section 78 narrows down the period selected by the code timing detection period selecting section 77 to determine the timing of the correlation peak and estimates the code timing.

With the above-mentioned structure, it is possible to reduce the influence of the occurrence and attenuation of the instantaneous correlation peak due to noise, fading, etc., and it is possible to improve the synchronization acquisition characteristic.

The respective embodiments described above can be combined and realized. Further, the constituent elements of the receiving device of each of the above embodiments do not need to be physically separated, and can be realized by a single unit or a plurality of signal processors.

[0065]

As described above, according to the present invention, the output power value of the matched filter for one cycle of the spreading code sequence is integrated every period when the period of the spreading code sequence is equally divided into a predetermined number of 2 or more. However, by determining the code timing based on the integrated value for each divided period, both the amount of memory used and the amount of calculation can be reduced, and the circuit configuration can be simplified.

Further, according to the present invention, the code timing is determined based on the result of cumulative addition of the integration result for each divided period obtained by the integrator over a plurality of cycles of the spread code sequence. It is possible to improve the deterioration of acquisition characteristics and reduce the time required for synchronous acquisition.

Further, according to the present invention, the code timing is determined from the result of synthesizing the integrated values obtained for each divided period with respect to the output power values of the matched filters of a plurality of antenna branches, thereby determining the above-mentioned invention. In the same way as above, deterioration of synchronization acquisition characteristics due to fading fluctuation can be improved,
The time required for synchronization acquisition can be reduced.

Further, according to the present invention, by using a plurality of matched filters with the sequences of different parts divided from the spreading code sequence as tap coefficients, the discrete reception signals are despread, respectively, and Correlation processing for one cycle can be performed in a time of 1 / n cycle, and the calculation time can be shortened.

Further, according to the present invention, the divided period in which the output power value of the matched filter exceeds the threshold value is judged, the judgment result is held for a predetermined number of spreading code sequence periods, and the code is based on the held contents. By determining the timing, the deterioration of the synchronization acquisition characteristic due to the fading fluctuation can be improved and the time required for the synchronization acquisition can be reduced as in the above-described invention.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a code synchronization acquisition circuit for spread spectrum signals according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the signal power integrator in FIG.

FIG. 3 is a diagram showing a modified example of the code synchronization acquisition circuit of the first embodiment.

FIG. 4 is a diagram showing a configuration of a code synchronization acquisition circuit for spread spectrum signals according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a code synchronization acquisition circuit for spread spectrum signals according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a code synchronization acquisition circuit for spread spectrum signals according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the code synchronization acquisition circuit of the fourth embodiment.

FIG. 8 is a diagram showing a configuration of a code synchronization acquisition circuit for spread spectrum signals according to a fifth embodiment of the present invention.

FIG. 9 is a diagram for explaining the operation of the code synchronization acquisition circuit of the fifth embodiment.

FIG. 10 is a diagram showing a configuration of a memory that holds a threshold comparison result for each divided period in the code synchronization acquisition circuit of the fifth embodiment.

11 is a flowchart showing a procedure of a memory update process of FIG.

[Explanation of symbols]

10, 40, 50, 60, 70 ......... Antenna 11, 41, 51, 61, 71 ... RF receiver 12, 42, 52, 62, 72 ... AD converter 13, 43, 53, 63, 73 ......... Matched filter 14, 44, 54, 64, 74 ... Signal power integrator 15, 45, 55, 65, 75 ... Timing generator 16,46,56,66,76 ......... Memory 17, 47, 57, 67, 78 ......... Peak determination section 48 ... Adder 58 ……… Switch 74 ………… Square 75 ......... Threshold judgment section 77 ... Code timing detection period selection unit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-70489 (JP, A) JP-A-8-8780 (JP, A) JP-A-6-77931 (JP, A) JP-A-7- 297805 (JP, A) JP 8-298478 (JP, A) JP 8-331011 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 13/00-13 / 06 H04B 1/69-1/713 H04L 7/00-7/10

Claims (7)

(57) [Claims] 1. A code synchronization acquisition circuit for acquiring the synchronization of a spread code of a direct spread spectrum signal, comprising: an antenna for receiving the direct spread spectrum signal; and a base for frequency-converting the signal received by the antenna. An RF receiving unit that obtains a band signal, an AD converter that obtains a discrete received signal by sampling the baseband signal obtained by the RF receiving unit, and a discrete received signal obtained by the AD converter. A matched filter that despreads with a spreading code, an integrator that integrates the squared value of the amplitude of the output signal of the matched filter for each period in which the period of the spreading code sequence is evenly divided into a predetermined number, and is determined by the integrator. Holding means for holding the integration result for each of the divided periods, and peak judging means for judging the code timing based on the contents held by the holding means. Code synchronization acquisition circuit of a spread spectrum signal characterized by Rukoto. 2. A code synchronization acquisition circuit for synchronously acquiring a spread code of a direct spread spectrum spread signal, comprising: an antenna for receiving the direct spread spectrum spread signal; and a base for frequency-converting the signal received by the antenna. An RF receiving unit that obtains a band signal, an AD converter that obtains a discrete received signal by sampling the baseband signal obtained by the RF receiving unit, and a discrete received signal obtained by the AD converter. A matched filter that despreads with a spreading code, an integrator that integrates the squared value of the amplitude of the output signal of the matched filter for each period in which the period of the spreading code sequence is evenly divided into a predetermined number, and is determined by the integrator. Holding means for cumulatively adding and holding the integration result for each of the divided periods over a plurality of cycles of the spread code sequence, and a code based on the contents held by the holding means. Code synchronization acquisition circuit of a spread spectrum signal, characterized by comprising a peak determining means for determining timing. 3. A code synchronization acquisition circuit for performing synchronization acquisition of a spread code of a direct spread spectrum signal, a plurality of antennas receiving the direct spread spectrum signal as a plurality of signals, and a signal received by each antenna. A plurality of RF receivers that obtain respective baseband signals by frequency conversion of A, and a plurality of A that obtains discrete received signals by sampling the baseband signals obtained by the respective RF receivers.
A D converter, a plurality of matched filters that despread the discrete reception signals generated by the AD converters with spreading codes, and a squared value of the amplitude of the output signal of each of the matched filters,
A plurality of integrators that respectively integrate the period of the spread code sequence into a predetermined number of periods, an adder that combines the integration results of the divided periods obtained by the integrators, and an adder that obtains Code synchronization acquisition of a spread spectrum signal, comprising: holding means for holding a combined value of integration results for each of the divided periods; and peak determination means for judging code timing based on the content held by the holding means. circuit. 4. A code synchronization acquisition circuit for acquiring synchronization of a spread code of a direct spread spectrum spread signal, comprising: an antenna for receiving the direct spread spectrum spread signal; and a base for performing frequency conversion on the signal received by the antenna. An RF receiving unit that obtains a band signal, an AD converter that obtains a discrete received signal by sampling the baseband signal obtained by the RF receiving unit, and a discrete received signal obtained by the AD converter. , A plurality of matched filters that respectively despread using the code sequences of different parts divided from the spreading code sequence, and the squared value of the amplitude of the output signal of each of the matched filters,
A plurality of integrators that integrate each period of the spread code sequence evenly divided into a predetermined number, a holding unit that holds the integration result for each divided period obtained by each integrator, and the holding unit A code synchronization acquisition circuit for a spread spectrum signal, comprising: peak determining means for determining code timing based on contents. 5. A code synchronization acquisition circuit for acquiring synchronization of a spread code of a direct spread spectrum signal, comprising: an antenna for receiving the direct spread spectrum signal; and a base for frequency-converting the signal received by the antenna. An RF receiver that obtains a band signal, an AD converter that obtains a discrete received signal by sampling the baseband signal that is output from the RF receiver, and a discrete received signal that is obtained by the AD converter. A matched filter that despreads with a code, a squarer that squares the amplitude of the output signal of the matched filter, and a period that equally divides the period of the spreading code sequence into a predetermined number,
Determination means for comparing the output of the squarer with a threshold value to determine a divided period in which the output of the squarer exceeds the threshold value; and a determination result of the determination means for a predetermined number of spread code sequences of 2 or more. A code synchronization acquisition circuit for a spread spectrum signal, comprising: holding means for holding a cycle; and peak determining means for judging a code timing based on the contents held by the holding means. 6. The spread-spectrum signal code synchronization acquisition circuit according to claim 1, wherein the peak determination unit divides the integration result held by the holding unit to have the largest value of the integration result. A code synchronization acquisition circuit for spread spectrum signals, characterized by selecting code timing corresponding to a period. 7. The code synchronization acquisition circuit for a spread spectrum signal according to claim 1, wherein the peak determination means sets a value of an integration result held by the holding means for each divided period in advance. A code synchronization acquisition circuit for spread spectrum signals, characterized in that the code timing corresponding to the divided period exceeding the specified threshold is selected as a complement.