JP3413815B2 - Wireless device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless device that performs signal processing by software.

[0002]

2. Description of the Related Art In some radios, all or part of signal processing is performed by software. FIG. 9 shows the configuration of a conventional wireless device of this type. In FIG. 9, 101 is an A / D and D / A converter, 102 is a dedicated IC, and 103 is D
SP (Digital Signal Process)
or; digital signal processing device), 104 is a memory, 10
5 is a control IC, 106 is a CPU, 107 is a ROM, 1
08 is an I / O interface, 109 is RAM, 11
Reference numeral 0 is an A / D and D / A converter, and 111 is an analog I / O.

The operation of the conventional radio will be described below with reference to FIG.

In the case of reception, the A / D and D / A converter 101 receives an analog signal received by a radio unit (not shown), converts the analog signal into a digital signal, and converts it into a dedicated I / O signal.
The operation of delivering to C102 is performed. On the other hand, when sending,
The digital signal input from the dedicated IC 102 is received, the signal is converted into an analog signal, and the signal is delivered to a wireless unit (not shown) for transmission.

In the case of reception, the dedicated IC 102 and the DSP 103 demodulate the signal input from the A / D, D / A converter 101, shape the waveform with a root roll-off filter, etc., channel codec, voice codec, etc. Is decrypted. On the other hand, in the case of transmission, by digital signal processing, operations such as encoding (mapping) of the original signal, waveform shaping by a root roll-off filter, modulation, etc. are performed, and the signal is A / D, D / A converter 101. Perform the operation to pass to. Among these processing, the dedicated IC 102
Performs relatively high-speed processing, and the DSP 103 causes the memory 10
According to the program recorded in No. 4, relatively low speed signal processing is performed. These processes may differ depending on the performance of the wireless communication system used, the dedicated IC used, and the DSP.

The control IC 105 performs control such as signal input / output timing control, channel control, and modulation / demodulation switching among the A / D and D / A converter 101, the dedicated IC 102, and the DSP 103. Further, it also controls a radio unit (not shown).

The CPU 106 loads the program recorded in the ROM 107 into the RAM 109, and
Control IC1 according to the program loaded in M109
05 and the input / output of data with the keyboard and the display via the I / O 108.

Regarding the A / D, D / A converter 110 and the analog I / O 111, in the case of reception, the A / D,
The D / A converter 110 converts the digital signal decoded by the DSP 103 into an analog audio signal and transfers it to the analog I / O 111. The analog I / O 111 reproduces the received analog signal as voice through a speaker. On the other hand, in the case of transmission, the analog I / O 111 transfers the analog audio signal input from the microphone to the A / D and D / A converter 110. The A / D, D / A converter 110 converts the received analog signal into a digital signal,
Hand it over to 103.

Most of these conventional radios are made of dedicated hardware such as ASIC and gate array, and some of the radio functions are realized by software. This makes it possible to take measures for some of the functions performed by the DSP in response to changes in specifications after design and trial production and bugs.

However, the conventional wireless device has the following problems. In other words, in such an architecture of a radio device, in order to support a plurality of radio communication systems such as an analog mobile phone and a digital mobile phone with a single radio device, a small portion of software is included. Therefore, it is necessary to physically equip a plurality of hardware parts and switch them as needed, which causes a problem that the hardware scale becomes large. Further, one radio cannot be used in both of a plurality of radio communication systems such as PDC and PHS. In addition, if there are bugs in the radio, most of them are hardware bugs, so even if it is a small one, we will collect all products depending on the type of bug,
There was a need to replace parts, which resulted in a significant cost loss.

[0011]

In the conventional wireless device,
In order to support a plurality of wireless communication systems, it is necessary to equip a plurality of hardware and switch them as necessary, which causes a problem that the hardware scale becomes large. In addition, a wireless device manufactured to support one wireless communication system cannot be changed to support another wireless communication system.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a radio apparatus capable of easily supporting a plurality of radio communication systems.

[0013]

According to the present invention, there is provided an A / D and D / A converter, a first memory for temporarily storing data of the A / D and D / A converter, and a predetermined radio unit. Of the DSP and the software of the DSP and the FPGA that processes the predetermined operation of the wireless device by hardware based on the program described in the hardware description language. Rewritable first storage device, input / output control device, I / O interface, CPU that executes software that controls the entire device, second storage device that stores software of the CPU, and processing by the CPU Wireless device including a second memory for temporarily storing data to be stored, the A / D and D / A converter, the first memory, Serial DSP, the FPGA, the first
Of at least a part of the storage device, the input / output control device, the I / O interface, the CPU, the second storage device, and the second memory are connected by an FPGA. Wireless device.

[0014]

[0015]

[0016]

[0017]

[0018]

For example, by rewriting the DSP program and the FPGA wiring for connecting (wiring) elements, it is possible to support a plurality of wireless communication systems.

Preferably, a dedicated IC for processing the operation of the radio device by hardware may be further provided, and the connection between the dedicated IC and other elements may be performed by the FPGA.

[0021] Preferably, the input / output control device may control a wireless means composed of an analog circuit.

Preferably, a D / A converter connected to a speaker is connected to the output of the I / O interface,
An A / D converter having a microphone connected thereto may be connected to the input of the I / O interface to enable voice communication.

Preferably, a network I / O device may be connected to the I / O interface to enable data communication.

It should be noted that the present invention related to the apparatus also holds as the invention related to the method, and the present invention related to the method also holds as the invention related to the apparatus.

According to the present invention, in a radio device which performs radio signal processing by software, a minimum of hardware is provided and means for adaptively changing wiring is provided, so that one radio device can be used for various radio devices. It becomes possible to adapt to the communication system, and the system change for the processing used in each wireless communication system can be realized easily and quickly. In addition, when the hardware is changed to support various wireless communication systems, the wiring between the devices can be easily changed by rewriting the changeable wiring program.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

Hereinafter, a radio having a function of realizing at least a part of the radio function by software will be referred to as a "software radio".

FIG. 1 shows a configuration example of a radio signal processing apparatus applied to the software defined radio according to this embodiment.

As shown in FIG. 1, the present radio signal processing apparatus has A / D and D / A conversions for A / D conversion and D / A conversion.
From A converter 1, A / D, D / A converter 1 or A /
A memory 2 for temporarily storing data to the D / D / A converter 1, a rewritable storage device 3 for holding software such as DSP and FPGA, and an operation of a wireless device in a program described by software. DSP (Digital Signal Procedures)
sor (digital signal processing device) 4, an FPGA (Field Pr) that processes the operation of the wireless device by hardware based on a program described in a hardware description language.
An programmable gate array 5, a memory 6, a CPU 7, a ROM 8, an I / O interface 9, an input / output control unit 10, and a changeable wiring 11 are provided.

Software for operating the DSP 4 is recorded in the rewritable storage device 3. The DSP 4 performs a desired operation by loading and executing a necessary program from the rewritable storage device 3. The rewritable storage device 3 is an EEPROM (Electrically)
Erasable and Programmable
e Read Only Memory), RAM (R
A readable / writable memory such as an and / or Access Memory) may be used. Further, the rewritable storage device 3 may include the memory 2.

The "changeable wiring" (11) is a wiring optimal for each wireless communication system such as a data bus and a control line when various wireless communication systems (such as PDC or PHS) are used. It is a thing. In addition, when there is a portion that is not used in the wireless communication system that is being used, connection is not performed and unnecessary current is prevented from flowing, so that there is an effect of suppressing power consumption of the entire device. The changeable wiring 11 is composed of, for example, an FPGA.

FIG. 2 shows a configuration example of a software defined radio to which the present radio signal processing apparatus is applied.

As shown in FIG. 2, the software defined radio comprises a radio section 12 and a radio signal processing device 20. The radio unit 12 performs RF processing such as analog signal filtering processing and power amplification processing, and IF processing such as band limitation, mixing with local oscillation signals, and modulation / demodulation. In addition, the wireless unit 12 includes a wireless signal processing device 20.
A control line from the input / output control unit 10 is connected, and for example, switching control of the duplexer, control of the oscillation frequency of the synthesizer, and the like are performed.

Next, the operation of the software defined radio will be described.

First, when the power is turned on, the CPU 7 has a ROM
The program recorded in 8 performs initial operations such as checking the currently operable wireless communication system. During operation of the wireless function, DSP4, FPGA5 and I / O
The O interface 9 is controlled. Also, the memory 6
Stores a program and temporary data for the CPU 7 to operate. In this software defined radio, software for implementing the wireless function is recorded in the rewritable storage device 3.

The DSP 4 and the FPGA 5 load and execute a program recorded in the rewritable storage device 3 necessary for the operation according to a control signal from the CPU 7. The application program executed by the DSP 4 is a part or all of digital processing. For example, a modulation function, a demodulation function, a filtering function, a frequency conversion function, a signal generation (synthesizer) function, a channel codec (TDMA).
Control) function, voice codec function, spread of CDMA, etc.
A despreading function and the like can be mentioned. Moreover, in this, A / D,
Functions for controlling the D / A converter 1, such as A / D, D / A
Control of clock frequency of converter, and further input / output control unit 1
A function of controlling the wireless unit 12 via 0, for example, switching of gain may be included. When the DSP 4 includes a function whose processing speed cannot be met in time or a function which is more efficient to execute in the FPGA 5, the FPGA 5 executes this. Of course, the CPU 7 may perform these controls.

The communication I / O interface 9 is for communicating data transmitted and received by a wireless function with an external device. For example, the data is a voice signal,
When the signal is for data communication, it provides an interface with an external device according to the signal.

The rewritable storage device 3 has a DS
The wiring information of "modifiable wiring" (11) for connecting devices such as P4 and FPGA5 is included.
The FPGA 5, the CPU 7, and the like are connected according to a program in the rewritable storage device 3. Furthermore, the CPU 7,
Since it is not necessary to change the connection of the ROM 8, fixed wiring may be performed.

When the software defined radio communicates,
First, at the time of reception, the A / D, D / A converter 1 outputs an RF signal,
An analog signal such as an IF signal and a baseband signal is received from the wireless unit, and A / D conversion processing is performed under the control of the DSP 4, CPU 7, and the like. The A / D converted digital signal is transmitted to the DSP 4 or the FPGA 5. If the signal transmitted here exceeds the processing speed of the DSP 4 or FPGA 5, a method of temporarily storing it in the memory 2 can be considered. For the converted digital signal,
The DSP 4 or FPGA 5 performs demodulation processing, filtering processing, channel codec processing, voice codec processing, despreading processing in the case of CDMA, and the like.
The data is transmitted to the O interface 9 directly or after being subjected to processing such as packetization to a protocol transmitted by the CPU 7 in the case of data communication, for example.

At the time of transmission, data such as voice signals and packet data is directly sent from the I / O interface 9 or after the packet data is processed by the CPU 7, the DSP
4 or FPGA5. DSP4 or FP
The GA5 performs voice codec processing, channel codec processing, filtering processing, modulation processing, and spreading processing in the case of CDMA on the received signal. When the processing is completed, the data is transmitted to the A / D and D / A converter 1. Further, in the case where a process for communicating data between the DSP 4 and the FPGA 5 is included, the data is stored in the memory 2 and the data is stored in the DSP 4 and the FPGA 5.
From the memory 2, the processed data is transmitted from the memory 2 to the A / D, D / A converter 1.

By configuring the wireless device in this way, when it corresponds to various wireless communication systems, since the modulation / demodulation function differs depending on the wireless communication system, the storage device 3 capable of rewriting the program of the modulation / demodulation function, for example, EEPRO.
It is possible to adaptively support various modulation systems by storing the data in M, switching this program as needed, and executing it in the DSP 4 or FPGA 5.

In a wireless communication system that requires high-speed signal processing, the rewritable storage device 3 is rewritten, and a program necessary for this high-speed signal processing is added to the FPGA 5 for processing. At this time, the changeable wiring 11 is rewritten so that only the necessary portions are connected.

In the case where the FPGA 5 needs a larger memory due to an increase in the scale of a program for a new wireless communication system in the future or an updated program for adding a new function to an existing wireless communication system. In addition, by adding a memory function, it can be used as a memory. In such a case, since the connection wiring is fixed in the conventional wireless device, it is impossible to connect to the I / O port of the memory and it is impossible to adopt such a method. On the other hand, in the case of the software defined radio of this embodiment, the changeable wiring 11 is composed of a rewritable device such as an FPGA. Therefore, even in such a case, a new wiring is added to the FPGA 5. It is possible to connect to the I / O of the added memory.

Next, FIG. 3 shows another example of the configuration of the radio signal processing apparatus 20 applied to the software defined radio according to this embodiment.

The radio signal processing apparatus of FIG. 3 is the same as the radio signal processing apparatus of FIG. 1 except that a dedicated IC 14 is added to the configuration of FIG.

In the configuration example of FIG. 3, the dedicated IC 14 is
Changeable wiring 1 in parallel with DSP4 and FPGA5
Connected by 1. The dedicated IC 14 is, for example, F
FT (Fast Fourier Transform)
fast processing such as fast Fourier transform (DSP) and the like which the DSP 5 and FPGA 5 lack in processing speed, or processing commonly used in a plurality of wireless communication systems, such as a filter function, a frequency conversion function, and an orthogonal modulation / demodulation function. It is for doing. The dedicated IC14 is
Since it is designed optimally for the processing to be executed, it can be expected to speed up the processing. Further, if the processing is not high speed and can be shared by a plurality of wireless communication systems, such as an orthogonal modulation / demodulation function, low power consumption can be achieved by executing the processing by the dedicated IC 14.

Note that the dedicated IC 14 is the same as the DSP 4 in that it loads and executes the program recorded in the rewritable storage device 3 necessary for the operation.

Next, the data input / output mode in this radio signal processing apparatus (or software defined radio to which this radio signal processing apparatus is applied) will be described.

In FIG. 4, an A / D, D / A converter 15 is connected to the I / O interface 9 of FIG. 1 or 3, and a microphone 16 and a speaker 17 are connected to this. Here, by inserting a codec function between the A / D, D / A converter 15 and the I / O interface 9, it is possible to support digital modulation and enable voice communication.

FIG. 5 shows a network I / O 18 connected to the I / O interface 9 shown in FIG. 1 or 3. The network I / O 18 is, for example, a serial connection I / O (RS-232C, USB, IEEE1).
394, etc.), PC card I / O, Ethernet I / O, infrared communication, and a modem connectable to a telephone line. This enables data communication with an information processing terminal such as a personal computer or PDA, another wireless device, a public line network, or the like.

Below, a software defined radio to which the present radio signal processing apparatus is applied will be explained using a more detailed concrete example.

Here, a case where a digital quadrature modulator / demodulator is formed by the ASIC 14 and a filter unit is formed by the FPGA 5 will be described as an example.

FIG. 6 shows an example of the configuration of the software defined radio.

In FIG. 6, the radio section 12 receives an RF wave from the antenna and supplies a signal to the A / D, D / A conversion section 1 by performing an amplification process and a frequency conversion process. The signal from the / D, D / A converter 1 is transmitted as an RF wave from the antenna.

The A / D and D / A conversion section 1 performs analog-digital conversion processing on the signal from the radio section 12 and supplies it to the digital quadrature modulator / demodulator (31, 32). Signal is subjected to digital-analog conversion processing and supplied to the wireless unit 12. The digital quadrature modulator / demodulator includes a multiplier 32 and an oscillator 31, and a demodulator 22 and a modulator 2 through a filter unit (33).
3 is connected. Modulation / demodulation processing is performed by the digital quadrature modulator / demodulator, the filter unit, the demodulation unit 22, and the modulation unit 23. The TDMA control unit 24 performs digital signal processing and connects to the codec unit 25.

The codec section 25 encodes and decodes voice, supplies the voice signal to the speaker 17 through the A / D and D / A converter 15, and the microphone 16 outputs A / D.
An audio signal is received through the D / D / A converter 15.

When the configuration of the software defined radio of FIG. 6 is realized by using the radio signal processing apparatus of this embodiment, for example, a digital quadrature modulator / demodulator is formed by the dedicated IC 14,
The filter unit is formed by the FPGA 5, and the demodulation unit 22, the modulation unit 23, the TDMA control unit 24, and the codec unit 25 are formed by the DSP.
4 and the wiring 11 which can be changed according to need is appropriately set. Note that, for example, the TDMA control unit 24 uses the CP
It may be realized by U7, and other functional blocks are not limited to the above-mentioned allocation method.

Next, the case where the functional block of FIG. 6 is realized in the radio signal processing apparatus of this embodiment will be described focusing on the “changeable wiring” (11).

FIG. 7 shows an example of wiring when the functional blocks of FIG. 6 are implemented in the radio signal processing apparatus of this embodiment.

In this case, the CPU 7, ROM 8 and memory 6
Is connected to the bus 26 having a fixed bit width.
It is also conceivable that the wiring is connected to the changeable wiring 11 without having. A general-purpose bus such as a PCI bus or an ISA bus may be used as the bus 26. Control wiring is connected from the bus 26 to the wireless unit 12 and the A / D, D / A conversion unit 1,
Signal input / output wirings are connected to the D / D / A converter 15 and the dedicated IC 14, the dedicated IC 14 and the FPGA 5, and the FPGA 5 and the DSP 4, respectively. The DSP 4 is further wired for connection with the I / O interface 9 for controlling input / output with the bus 26 and controlling input / output with the A / D and D / A converter 15 for voice. All or part of these wirings is performed by the changeable wiring 11.

FIG. 8 is a wiring diagram in the software defined radio of this embodiment for realizing the configuration of FIG.

As shown in FIG. 8, "changeable wiring"
(11) is an A / D, D / A converter 1, a dedicated IC 14,
It is connected to the FPGA 5, DSP 4, bus 26, A / D, D / A converter 15 by a plurality of wirings. By rewriting the wiring inside the changeable wiring 11 by a program such as FPGA as shown in FIG.
Connections are made as shown by the shaded areas in FIG. That is, in this case, the internal wiring of the changeable wiring 11 includes the fixed wiring to the A / D and D / A conversion unit 1 and the dedicated IC 1
4 fixed wiring, dedicated IC 14 fixed wiring and FPGA
5, fixed wiring with FPGA 5, fixed wiring with FPGA 5 and fixed wiring with DSP 4 are written so as to be connected to each other.

In the present embodiment, the radio signal processing device is provided with a DSP, an FPGA, and a dedicated IC as an example. However, not all of these elements are essential, and they may be provided as appropriate. It's good. Of course, D
Elements other than the SP, FPGA, and dedicated IC may be provided.

The present invention is not limited to the above-described embodiments, but can be implemented with various modifications within the technical scope thereof.

[0065]

According to the present invention, one wireless device can be easily adapted to a plurality of wireless communication systems.
In addition, when the hardware is changed to support various wireless communication systems, the wiring between the devices can be easily changed by rewriting the changeable wiring program.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a wireless signal processing device of a software defined radio according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a software defined radio according to the embodiment.

FIG. 3 is a diagram showing another configuration example of the radio signal processing device of the software defined radio according to the embodiment.

FIG. 4 is a diagram showing an example of a data input / output mode of the software defined radio according to the embodiment.

FIG. 5 is a diagram showing another example of the data input / output mode of the software defined radio according to the embodiment.

FIG. 6 is a diagram showing a more detailed internal configuration example of the software defined radio according to the embodiment.

FIG. 7 is a diagram for explaining changeable wiring.

FIG. 8 is a diagram for explaining changeable wiring.

FIG. 9 is a diagram for explaining a conventional wireless device.

[Explanation of symbols]

1, 15 ... A / D, D / A converter 2 ... memory 3 ... Rewritable storage device 4 ... DSP 5 ... FPGA 6 ... Memory 7 ... CPU 8 ... ROM 9 ... I / O interface 10 ... Input / output control unit 11 ... Changeable wiring 12 ... Wireless section 14 ... Dedicated IC 16 ... Mike 17 ... speaker 18 ... Network I / O 20 ... Wireless signal processing device 22 ... Demodulation unit 23 ... Modulator 24 ... TDMA control unit 25 ... Codec section 26 ... bus 31 ... Oscillator 32 ... Multiplier 33 ... Filter

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shinichi Sugano 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center Co., Ltd. (72) Inventor Masayuki Fujise 3-4 Hikarinooka, Yokosuka City, Kanagawa Prefecture Ministry of Posts and Telecommunications Communication Research Laboratory, Yokosuka Wireless Communication Research Center (72) Inventor Hiroshi Harada 3-4 Hikarinooka, Yokosuka City, Kanagawa Prefecture Ministry of Posts and Telecommunications Yokosuka Wireless Communication Research Center (56) Reference JP-A-11-55147 (JP, A) JP-A-11-289051 (JP, A) JP-A-11-18146 (JP, A) JP-A-10-321794 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H04B 1/40 H04L 27/22

Claims (5)

(57) [Claims] 1. An A / D and D / A converter, a first memory for temporarily storing data of the A / D and D / A converter, and a predetermined operation of a wireless device described by software. DSP that processes based on a program, FPGA that processes a predetermined operation of a radio device by hardware based on a program described in a hardware description language, and D
A rewritable first storage device that holds the SP and FPGA software, an input / output control device, an I / O interface, a CPU that executes software that controls the entire device, and a second storage that stores the software of the CPU A device, a wireless device including a second memory for temporarily storing data processed by the CPU, the A / D and D / A converter, the first memory, the DSP, the FPGA, The first storage device, the input / output control device, the I / O interface, the CP
A wireless device, characterized in that an FPGA connects at least some elements of the U, the second storage device, and the second memory. 2. A dedicated IC for processing the operation of a radio device by hardware is further provided, and the connection between the dedicated IC and other elements is also the FPGA.
The wireless device according to claim 1 , wherein the wireless device is performed by. Wherein the output control device, a radio device according to claim 1, characterized in that controlling the radio unit consisting of an analog circuit. 4. A D / A converter connected to a speaker is connected to the output of the I / O interface, and an A / D converter connected to a microphone is connected to the input of the I / O interface, The wireless device according to claim 1 , which enables a telephone call. 5. The wireless device according to claim 1 , wherein a network I / O device is connected to the I / O interface to enable data communication.