JP3410993B2 - Error correction device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a VBI data processing means included in a television video signal.

[0002]

2. Description of the Related Art In recent years, a service for transmitting program guides and data relating to programs has been started by using VBI data superimposed in a vertical blanking period of a video signal.

At this time, it is necessary to correct the error due to transmission distortion in real time to the transmitted data.

By the way, in a simple even-odd parity in which parity is added so that the total sum becomes 0 (even number) or 1 (odd number) for every several pieces of transmission information consisting of 0 and 1, it is clear whether or not a transmission error occurs. However, it is unknown where there is an error.
Further, if two or even errors occur in the original transmission information, the receiving side will recognize it as correct. Further, in reality, a transmission error also occurs in the parity itself. This state is shown in FIG. Therefore, correct information cannot be restored.

Therefore, a technique called code correction has been developed as a countermeasure. This is, for example, to reduce the problem of "finding and correcting an error" to the problem of "solving simultaneous equations" or to add redundancy to a signal.

If the former is specifically shown, the data (D ₂₇₁ ,
, D ₈₂ ) to which parity (P ₈₁ , ..., P ₀ ) is added, or code or transmission information (D ₂₇₁ , ..., D ₈₂ , P ₈₁ , ...)
P ₀ ).

At this time, the parity (P ₈₁ , ..., P ₀ ) is set so that the 271-th order code polynomial C (X) having this code as a coefficient is divisible by the generator polynomial G (X).

That is, the root of G (X) is a0, ..., A8
When set to 1, C (a1), ..., C (a81) = 0 are set.

If there is an error in transmission, the received code polynomial C '(X) does not have a1, ..., A81 as its root. That is, it cannot be divided by G (X).

Therefore, C '(X) is divided by G (X). If it is not divisible, it is determined that there is an error, and the error position and the correct value are obtained from the remainder. That is.

However, the principle itself and the BEST method targeted by the present invention are, for example, "Introduction to Code Theory" published by Shoseidou, and "Practical Error Correction Technology" published by Trikeps, "Teletext Broadcast Handbook" Kenroku. Company
This is a so-called well-known technique described in "Television Technology November 1987-October 1988 Mechanism of Error Correction Code" and the like. Therefore, further explanation is omitted.

Next, in the actual correction, as shown in FIG. 2, the division circuit 10 for dividing the input data by the generator polynomial.
1, a composite parity check conversion circuit 103 for converting a division result into a composite parity check, an adder circuit 104 for detecting how many errors the converted data has, a majority logic judgment circuit 105 for detecting an error bit, A buffer register 106 that holds input data for a certain period, an exclusive OR circuit 107, and an error correction completion signal generation circuit 109.
The error correction device of the BEST system configured from c and the error correction device performs error correction, and after the error correction of the BEST system is completed, the first switch 108 is allowed to pass, and CRC (cyclic) is applied to the input data in which the error is corrected. The redundancy check) processing circuit 110 performed the CRC. Here, BEST-mode error correction is to divide the received 192 bits of information bits and 82 bits of check bits into 272-bit data by a generator polynomial to be described later, and if there is a remainder, an error has occurred. This is a method of making a judgment, performing error correction processing, and again dividing the corrected data by the generator polynomial to confirm that the error has been completely corrected.

The determination of the error correction completion of the BEST method is made by using the output of each register of the division circuit and determining that the error correction is completed when the output becomes 0.

[0014]

However, in the above-mentioned conventional configuration, the output of the register of the division circuit becomes 0 in the middle of the error correction algorithm of the BEST method, and the error correction may be judged to be completed. .

The reason is as follows.

FIG. 3 shows a flowchart of a conventional error correction process.

In the figure, the majority logic decision value indicates the value of the error bit detection signal 104s, and 15 to 9 indicate constants when the majority decision logic 105 makes a majority decision.

As shown in the figure, the conventional second and subsequent iterations utilize that all register outputs 0s to 81s of the generator polynomial division circuit 101 become 0 when the generator polynomial is divided. However, if the number of error bits is larger than the error detection performance limit of the BEST method,
Since it may happen that the data is divided by the generator polynomial on the way, that is, even if there is an error, each register output 0s of the generator polynomial division circuit 101
Since 81s may all be 0, an erroneous determination may occur.

The service identification signal is CRC.
Since the error detection is performed in the above, error correction is not performed in the BEST method.

For this reason, it has been desired to realize an error correction device that does not cause an erroneous determination of error correction completion.

Further, it has been desired to develop a technique capable of performing error detection for a service identification signal performed using VBI data.

[0022]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a correction device in which an erroneous determination of error correction completion does not occur. Specifically, it has the following configuration.

[0023]

According to a first aspect of the present invention, a first signal is generated by converting an input signal by a generating polynomial dividing means, a decoding parity check converting means, and a sum calculating means. A correction bit number signal for converting the first signal by the majority logic judgment means and further for inputting the converted signal to the counting means to generate a correction bit number signal indicating the number of bits actually corrected. Generating means, first
Control signal generating an active control signal only when the signal and the correction bit number signal are equal to each other and the correction bit number signal is smaller than the correction capability signal given from the outside; signal interposed signal on the line for supplying the CR C processing means, a switch means switching operation is changed in accordance with the control signal from the control means, the control signal becomes conductive only when active,
The signal after error correction by the BEST method is that a switch means for supplying to the CR C processing unit.

With the above configuration, when there are more errors than the number of correction bits, an erroneous determination is made that error correction is completed even if there are errors, and therefore information is passed downstream with all errors not corrected. Can be eliminated.

According to a second aspect of the present invention, in the error correction device according to the first aspect, there is provided an input mode detecting means for detecting an input mode from the VBI data, and the control means has a correction capability given from the outside. It is an input mode use control means that uses information about the input mode input from the input mode detection means as a signal. As a result, it is possible to eliminate erroneous determination of error correction depending on the broadcast content.

According to a third aspect of the present invention, in the error correction device according to the first aspect, whether or not the input signal is an ADAMS signal for the electronic program guide service according to the communication protocol, data sent from the station, and the like. If the switch means detects that the signal is an ADAMS broadcast service identification signal, it supplies the signal after error correction by the BEST method to the CRC processing means.

With the above-described structure, since the CRC is used for the conventional detection, it is possible to detect the bit error of the service identification signal which is not made by the BEST method.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on its embodiments.

(First Embodiment) FIG. 4 shows the configuration of the error correction apparatus according to the present embodiment.

In the figure, reference numeral 100 is an input terminal.
Reference numeral 101 is a generator polynomial division circuit. 102 is a selection circuit. Reference numeral 103 is a decoding parity check conversion circuit. Reference numeral 104 is an adder circuit. Reference numeral 105 is a majority logic discriminating circuit. Reference numeral 106 is a buffer register having a FIFO function. 107 is an exclusive OR circuit. Reference numeral 108 is a first switch. 109 is
This is an error correction completion signal generation circuit. 110 is a CRC processing circuit. 111 is a second switch. 11
2 is an output terminal. The functions and operations of these parts are the same as those of the prior art shown in FIG. 2 except for the error correction completion signal generating circuit 109, and corresponding parts (parts) are designated by the same reference numerals. Reference numeral 113 is a VBI sampling data input terminal.

Further, 100s is an input signal (correctly, a line through which the signal is transmitted, but it is shown as such because it is self-evident and, if written correctly, the sentence becomes complicated and may be difficult to understand. This is also the case with other signals (lines).

102s is a selection signal.

The input signal 100s is a VBI superimposed on a predetermined period of the vertical blanking period of the video signal.
It is a serial signal obtained by digitizing the signal. The input signal 100s is a (272, 190) shortened difference set cyclic code. Here, the (272, 190) shortened difference set cyclic code is a code created by utilizing the property of a mathematical set called a complete simple difference set, and the majority decision logic (more than half of a large number of inputs is activated). Is a code that is decoded by using the gate) decoding method in which the output is activated. This enables error correction using the BEST method.

Here, the information bits are sequentially set, x is a binary number, the coefficient value of each term of the polynomial of the following equation 1 is obtained, and this polynomial is divided by a generator polynomial to be described later and the remainder of the following equation 2 is obtained. The coefficient value of each term of the polynomial of is used as a check bit.

[0035]

[Equation 1]

[0036]

[Equation 2] From the above, the input signal 100s is expressed by the following polynomial equation (3).

[0037]

[Equation 3] The input terminal 100 receives the input signal 100s.

The generator polynomial division circuit 101 uses the selection signal 1
02s is input, division is performed by a generator polynomial described later, and the remainder is output as 0s to 81s.

FIG. 5 shows the configuration of the generator polynomial dividing circuit 101. In the figure, 299 is a selection signal 102.
This is a terminal for inputting s. Reference numerals 200 to 281 denote 82 registers for sequentially storing the division result. 282-29
Reference numeral 8 denotes a select signal 299s, a register output signal 3s, a register output signal 9s, and a register output signal 17 which will be described later.
s, register output signal 21s, register output signal 23
s, register output signal 33s, register output signal 35
s, register output signal 39s, register output signal 47
s, register output signal 51s, register output signal 55
s, register output signal 65s, register output signal 66
s, register output signal 70s, register output signal 75
s, each of the register output signals 76s and the register output signal 81s are input, the exclusive OR is taken, and the exclusive OR output signals 282s to 298s are output, respectively.

Exclusive OR output signals 282s to 298s
Are registers 200, 204, 210, 218, 22
2, 224, 234, 236, 240, 248, 25
2, 256, 266, 267, 271, 276, 277
Are input respectively.

Here, the generator polynomial is expressed by the following equation 4 using x as each digit of a binary number, and the order corresponds to each of the upper order of 82 registers.

[0042]

[Equation 4] Also, the remainder is expressed by the following equation (5), each of which has an order equal to or less than the degree of the generator polynomial G (x), and 0s to 81
It is output as s. Let the coefficient value of each place be ex.

[0043]

[Equation 5] The selection circuit 102 selects the input signal 100s and the output signal 107s of the exclusive OR 107 according to the output signal 109s of the error correction completion signal generation circuit 109, and selects the selection signal 1
02s is output.

The decoding parity check conversion circuit 103
Register output signals 0s to 81s are input, and parity check signals 1p to 17p are output. In this conversion, some of the register output signals 0s to 81s are extracted, binary numbers are added, and the register output signals 0s to 81s are added.
Each of s exists only once in the parity check signals 1p to 17p. Table 1 shows the combinations taken out from the register output signals 0s to 81s.

[0045]

[Table 1] The adder circuit 104 uses the parity check signals 1p to 17p.
Is input, a normal addition operation is performed on the number 1 and an error bit detection signal 104s is output. Here, the value of the error bit detection signal 104s indicates the number of multiple bit errors in the error pattern according to the principle of the BEST method.

The majority decision logic decision circuit 105 receives the error bit detection signal 104s, performs a majority decision with a constant,
The error correction signal 105s is output.

The error correction signal 105s is a signal which becomes 1 when a bit for error correction is performed.

The buffer register 106 receives the input signal 10
0s is input, and the delay signal 106s is output after delaying for 273 stages of error detection.

The exclusive OR circuit 107 receives the error correction signal 105s and the delay signal 106s, performs an error correction process of inverting the erroneous bit by adding a binary number to the erroneous bit, The BEST method error correction signal 107s is output.

When the error correction completion signal generation circuit 109 determines that the error correction is completed, the first switch 108 allows the BEST method error correction signal 107s to pass therethrough and outputs the first passing signal 108s.

The error correction completion signal generation circuit 109 inputs the error bit detection signal 104s, the error correction signal 105s, and the input mode signal 113s, and receives the error correction completion signal 109.
Output s. Note that this configuration will be described later in detail.

Reference numeral 110 inputs the first passing signal 108s which is determined to have completed the error correction of the BEST method,
A CRC processing circuit that performs error detection by the CRC error detection method and outputs a CRC error detection signal 110s.

Here, CRC means data that is inserted in advance to detect an error in transmitted or recorded digital data. In this embodiment, the received data group is shown by the following CCITT recommended number 6. CRC
This is an error detection method in which a code generation polynomial F (x) is divided and if there is a remainder, it is determined that an error has occurred.

Here, the data group is one group of data to be transmitted, and is a group of data blocks of several data packets. A data packet is the information bit of 190 bits and 8 bits described above.
A 272-bit data that is a combination of 2 check bits, and a data block is a 176-bit data that excludes 16-bit data called a prefix that includes a service identification signal, etc., out of 190-bit information bits. That is.

[0055]

[Equation 6] 111 inputs the CRC error detection signal 110s,
When the C processing circuit 110 determines that there is no error,
The first passing signal 108s is directly used as the second passing signal 11s.
The second switch outputs 1s. 112 is
This is an output terminal for outputting the second passing signal 111s in which the error bit is corrected by the BEST error correction algorithm and there is no error in the CRC error detection.

FIG. 6 shows an error correction completion signal generation circuit 109.
Shows the configuration of.

In the figure, reference numeral 600 is an input terminal for inputting the error bit detection signal 104s. An input terminal 601 inputs the error correction signal 105s. 602
Is an input terminal for inputting the input mode signal 113s. A calculation circuit 603 receives the error correction signal 105s, accumulates the number of 1s generated for each corrected bit, and outputs the accumulated value as a calculation output signal 603s. 604 receives the error bit detection signal 104s and the calculated output signal 603s, determines whether or not the values of the two signals match, and if they match, outputs “1” as the match signal 604s, and does not match. If so, the matching circuit outputs "0" indicating that fact. 605 is a calculated output signal 60
3 s and the input mode signal 113 s are input, the value of the input mode signal 113 s is determined based on that, and the comparison output 605 s that becomes 0 when the value of the calculated output signal 603 s is smaller than the value of the input mode signal 113 S It is a comparison circuit for outputting. An output terminal 606 outputs the error correction completion signal 109s. Reference numeral 607 denotes a 2-input OR circuit which inputs the coincidence signal 604s and the comparison output 605s and outputs the error correction completion signal 109s.

Next, the operation of this error correction device will be described.

The input signal 100s is input from the input terminal 100 and input to the selection circuit 102.

The selection signal 102s is input to the generator polynomial dividing circuit 101.

The generator polynomial division circuit 101 shown in FIG.
In order to detect an error correction bit, a division operation by a generator polynomial is performed and register output signals 0s to 81s are output. The register output signals 0s to 81s indicate the remainder when divided by the generator polynomial.

The register output signals 0s to 81s are input to the decoding parity check conversion circuit 103, and the parity check signals 1p to 17p are output. The parity check signals 1p to 17p are input to the adder circuit 104,
When the selection signal 102s is all input to the generator polynomial division circuit 101, the error bit detection signal 104s is output. Error bit detection signal 10
The value of 4s indicates the number of error bits included in the input signal 100s. However, it is possible to reliably detect up to a 9-bit error in the present embodiment.

The error bit detection signal 104s is input to the majority logic decision circuit 105, and with respect to the constants shown in FIG.
A majority decision is made and an error correction signal 105s is output.

Since the error correction signal 105s becomes 1 in the bit in which the error occurs, by accumulating the number of 1s, it is possible to know how many bits the error correction has been applied to the input signal 100s.

The input signal 100s is input to the generator polynomial division circuit 101 and at the same time, input to the buffer register 106, delayed by 273 stages, and output as a delayed signal 106s.

Error correction signal 105s and delay signal 106s
Is input to the exclusive OR circuit 107 to perform error correction,
The BEST method error correction signal 107s is output. At the same time, the BEST mode error correction signal 107s is transmitted to the selection circuit 102.
To the error correction completion signal 109s, that is, until the value of the error correction completion signal 109s becomes 0, the above operation is repeated.

The second and subsequent operations are performed again on the BEST system error correction signal 107s in which the error bit is corrected, by B
It is determined whether or not the error-corrected data is divisible by the BEST polynomial by performing the division by the EST polynomial. When it is divisible by the generator polynomial, each register output of the generator polynomial division circuit 101 is 0s to 81s.
Becomes all 0.

Therefore, in this apparatus, the error bit detection signal 1
04s and the error correction signal 105s are input to the error correction completion signal generation circuit 109 to generate the error correction completion signal 109s, and the flow of error correction processing is controlled depending on whether the error correction completion signal 109s is 0 or not.

Here, the error correction completion signal generation circuit 109
The operation will be described with reference to FIG. From the input terminal 601,
The input error correction signal 105s is accumulated in the calculation circuit 603 by a normal addition operation with the number of 1s. The accumulated value is output as the calculation output signal 603s. The calculated output signal 603s indicates how many bits the error added to the input signal 100s is corrected.

The error bit detection signal 104s is input from the input terminal 600.

The error bit detection signal 104s indicates how many bits the error added to the input signal 100s is. However, up to 9-bit error can be reliably detected.

The error bit detection signal 104s is input to the coincidence circuit 604 together with the calculated output signal 403s, and it is determined whether or not the value of the calculated output signal 603s and the error bit detection signal 104s match. A coincidence signal 604s that becomes 0 is output. Here, the fact that the error bit detection signal 104s and the calculated output signal 603s match means that the number of error bits that can be detected is the same as the number of bits for which error correction has been performed.

The input mode signal 113s input from the input terminal 602 is input to the comparison circuit 605 together with the calculated output signal 603s.

Here, the input mode signal 113s indicates the limit value of the error detection capability of the error correction device.
When error correction is performed on the (272, 190) shortened difference set cyclic code by the BEST method, the detection capability limit is 9 of 9-bit error. The comparison circuit 605 compares the calculated output signal 603s with the input mode signal 113s, and if the calculated output signal 603s is small, the comparison output 60 becomes 0.
Output 5s. The 2-input OR circuit 607 receives the match signal 6
04s and the comparison output 605s are input, and the error correction completion signal 109s is output. The error correction completion signal 109s outputs 0 when both the coincidence signal 604s and the comparison output 605s are 0. At the same time, it indicates that the error correction is completed.

The BEST mode error correction signal 107s is input to the first switch 108, and the error correction completion signal 10s is input.
When 9s becomes 0, that is, when the error bit disappears, the first passing signal 108s is output to the CRC check processing circuit 110. In the CRC check processing circuit 110, the first passing signal 108s is input, error detection is performed by the CRC error detection method, and the CRC error detection signal 11
Output 0s.

The first passing signal 108s is also input to the second switch 111. With the second switch 111,
When there is no error in the CRC processing circuit 110, the CRC error detection signal 110s becomes 0, and the first passing signal 108
s is output as it is as the second passing signal 111s.
The second passing signal 111s is output from the output terminal 112.

(Second Embodiment) The present embodiment is characterized in that an input mode detection circuit is provided.

FIG. 7 shows an error correction device according to the second embodiment of the present invention. In this figure, 700 is a VBI sampling data input terminal, and 700s is VBI sampling data. Reference numeral 701 is an input mode detection circuit. The same reference numerals are given to portions (objects, constituent elements) having the same functions as those of the other previous embodiments, and description thereof will be omitted.

Next, the operation of this error correction device will be described, centering on the input mode detection circuit 701 different from the previous embodiment.

From the VBI sampling data input terminal 700,
Input VBI sampling data 700s.

Here, the VBI sampling data 700s is the data after the clock synchronization is reproduced corresponding to the CRI in the analog signal modulated in the amplitude direction and the signal logical identification is performed.

The VBI sampling data 700s is input to the input mode detection circuit 701, the input mode is detected from the framing code pattern, and the input mode signal 1
13s is output. The framing code is detected by pattern matching. Here, the framing code is called a byte synchronization code, and byte synchronization is reproduced based on this. Further, since the value of the framing code is determined in advance by the text broadcasting system, the broadcasting system can be discriminated by the value. When the broadcasting system is known, the error correction system is known, so that the limit value of the correction capability of the error correction device can be determined.

(Third Embodiment) The third embodiment is characterized in that an ADAMS broadcast SI detection circuit is provided as compared with the first embodiment.

FIG. 8 shows an error correction device according to the third embodiment of the present invention. In the figure, reference numeral 500 is an ADAMS broadcast SI detection circuit 500.

Next, the ADAMS broadcast SI detection circuit 800
The operation of this error correction device will be described with reference to FIG.

Here, the ADAMS broadcast is a broadcast in which the data of the program guide is multiplexed by using the VBI data superimposed in a predetermined period of the vertical blanking period of the video signal.

The ADAMS broadcast SI detection circuit 800 is
EST system error correction signal 107s is input, ADAMS
Broadcast service identification signal is detected by pattern matching,
SI detection signal 800s that becomes 0 when the patterns match
Is output. FIG. 9 shows an error correction completion signal generation circuit 109.
Shows the configuration of.

In the figure, the same reference numerals 600 to 60 are given to those having the same functions and the like as those of the error correction completion signal generating circuit 109 of the first embodiment shown in FIG.
6, and the description thereof is omitted.

As described above, the point that the terminal 900 for inputting the SI detection signal 800s which is the output of the ADAMS broadcast SI detection circuit 800 is provided and the point that the three-input OR circuit 901 is provided are different. , Which is a broadcast in which program table data is multiplexed using VBI data that is superimposed in a predetermined period of a vertical blanking period of a video signal.

In FIG. 9, the comparison output 605s, the SI detection signal 900s input from the input terminal 900, and the coincidence output 604s are ORed by the 3-input OR circuit 901, and the result is used as the error correction completion signal 109s. 6 in the first embodiment.

As a result, error correction by the CRC of the service identification signal of ADAMS broadcasting can also be performed.

Although the present invention has been described based on some embodiments thereof, it goes without saying that the present invention is not limited to these. That is, for example, the following may be performed.

1) For the convenience of manufacturing, etc., one constituent element (requirement, part) of the present invention may be a plurality of physical objects,
On the contrary, some components are integrated.

2) Another method is used for code correction. Therefore, the upper limit value of the error bit number is not 9. In addition to this, the CRC processing circuit is abolished.

3) Partial constituent elements (requirements, parts) of the present invention
Is configured not as hardware but as software.

[0096]

As can be seen from the above description, according to the present invention, error correction completion determining means for determining the completion of error correction even in a pattern having more error bits than the performance detection limit of the BEST method. By providing, it becomes possible to eliminate erroneous determination of error completion determination. As a result, it is possible to reduce wasteful processing in the CRC system on the downstream side and also to improve the usage efficiency of the CPU used therein.

Also, error correction of the service identification signal can be performed.

Especially, the effect becomes large in the ADAMS broadcasting.

[Brief description of drawings]

FIG. 1 is a diagram showing that correct decoding cannot be achieved by simple even-odd parity.

FIG. 2 is a configuration diagram of a conventional BEST-type error correction device.

FIG. 3 is a flowchart of conventional error correction processing.

FIG. 4 is a configuration diagram of an error correction device according to the first embodiment of the present invention.

FIG. 5 is a configuration diagram of a generator polynomial division circuit.

FIG. 6 is a configuration diagram of an error correction device according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of an error correction completion signal generation circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of an error correction device according to a third embodiment of the present invention.

FIG. 9 is a configuration diagram of an error correction completion signal generation circuit according to a third embodiment of the present invention.

[Explanation of symbols]

100 input terminals 101 generator polynomial division circuit 102 selection circuit 103 Decoding parity check conversion circuit 104 adder circuit 105 majority logic discriminating circuit 106 buffer register 107 Exclusive OR circuit 108 First switch 109 error correction completion signal generation circuit 110 CRC processing circuit 111 Second switch 112 output terminals 113 VBI sampling data input terminal 600 Error bit detection signal input terminal 601 Error correction signal input terminal 602 Input mode signal input terminal 603 Calculation circuit 604 Matching circuit 605 Comparison circuit 700 VBI sampling data input terminal 701 Input mode detection circuit 800 ADAMS broadcast SI detection circuit 900 SI detection signal input terminal 901 3-input OR circuit 102s selection signal 104s error bit detection signal 105s error correction signal 106s delayed signal 107s BEST system error correction signal 108s 1st passage signal 109s Error correction completion signal 110s CRC error detection signal 111s Second pass signal 113s Input mode signal 603s Calculation output signal 604s coincidence signal 605s comparative output 700s VBI sampling data 800s SI detection signal

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Claims (3)

(57) [Claims] 1. An input signal is converted by a generator polynomial division means, a decoding parity check conversion means, and a summation calculation means, and first.
And a corrected bit indicating the number of bits actually corrected by inputting the converted signal to the counting means and converting the first signal by the majority logic judgment means. Only when the correction bit number signal generating means for generating a number signal and the first signal and the correction bit number signal match and the correction bit number signal is smaller than the correction capability signal given from the outside, control means for generating a control signal which becomes active, a switch means for a signal after error correction is interposed on the signal line for supplying the CR C processing unit, the switching operation is changed in accordance with the control signal from the control means Therefore, it conducts only when the above control signal is active, and the BEST
Error correction device characterized in that it comprises a switch means for supplying a signal after error correction is CR C processing means, the by scheme. 2. An input mode detecting means for detecting an input mode from VBI data is provided, and the control means further includes information regarding the input mode input from the input mode detecting means as the correction capability signal given from the outside. The error correction device according to claim 1, wherein the error correction device is an input mode use control means to be used. 3. An ADAMS broadcast service identification signal detecting means for determining whether or not the input signal is an ADAMS signal, and the switch means further includes a BEST system if it detects that the input signal is an ADAMS broadcast service identifying signal. 2. The error correction device according to claim 1, wherein the error correction device is ADAMS-compatible switch means for supplying a signal after error correction by the CRC processing means.