JP3404808B2 - Decoding method and decoding device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for processing image signals (video signals) and acoustic or audio signals (audio signals). The present invention is specifically directed to MPEG (Motion Pictrure Image Coding Expert).
Group) etc., the video signal and the audio signal synchronized with this video signal are compressed and encoded and provided to the data transmission system or the data storage system as a bit stream. The present invention relates to an audio / video (AV) signal processing method and apparatus for inputting this bit stream from a system and expanding / decoding it. More specifically, the present invention relates to a method and apparatus for reducing the start-up delay during playback or channel switching when performing the above-mentioned decoded signal processing.

[0002]

2. Description of the Related Art A video signal (video signal) and a digital data storage medium such as a compact disc read only memory (CD-ROM), a laser disc (LD), a video tape, a magneto-optical recording medium (MO), and a DCC. Audio signals (audio signals) are compressed, multiplexed (multiplexed), and directly recorded as a bit stream. Then, the multiplexed bit stream is read again from the data storage medium, demultiplexed, and decompressed in reverse. Processing and reproducing (decoding) the original video signal (original video signal) and the original audio signal before compression processing are video tape recording / reproducing devices, multimedia systems, and other image and audio data processing devices. Is being done in. Also in television broadcasting, satellite broadcasting, multimedia systems, etc., video signals and audio signals are compressed and encoded, output as a multiplexed bit stream to a data transmission system or a data storage system, and then multiplexed. After inputting the bit stream and demultiplexing it, decompression processing reverse to compression is performed to decode the original video signal and audio signal.

Video signals and audio signals are compressed and encoded and recorded on a data storage medium such as a CD-ROM, LD, and video tape, and the encoded video signals and audio signals recorded on the data storage medium are expanded. ISO is used as an international standard as a moving picture coding standard for storage in which the original video signal and audio signal are decoded.
In the working group (WG) 11 in SC2 under the umbrella of JTCI, which handles common matters in the data processing field of JEC and JEC, MPEG (Motion Pictrure Im
age Coding Expert Group) standard MPEG1,
And the standard MPEG2 is known.

[0004] MPEG is a standard premised on a wide range of applications, and it is planned that phase synchronization (phase lock) will be taken and phase synchronization will not be taken (unlocked). In the case of phase synchronization, the video signal encoding clock (that is, frame rate) and the audio signal encoding clock (that is, audio signal sampling rate) have a common system clock reference (System Clock R
eference) Phase locked to the SCR. MPEG in this case requires a time stamp to be added to the multiplexed bitstream with a period of 0.7 seconds. When the phase synchronization is not taken, the video signal and the audio signal are processed independently and they are decoded based on the respective time stamps added at the time of encoding.

Also, MPEG defines 1 second as a buffering delay time of a system target decoder. Further, the MPEG stipulates that a directory for searching a video signal and an audio signal be provided when decoding.

FIG. 5 illustrates such an MPEG1 or MP.
It is a figure which shows the structural example at the time of applying EG2 to a video signal and an audio signal processing apparatus, and how the code processing system 100 inputs the uncompressed video signal S2 and the uncompressed audio signal S3, and how it is restrained. It shows how to generate some information about the parameter system target decoder 400 to form a constrained bitstream suitable for various decoding systems. The video signal and audio signal processing apparatus includes an uncompressed video signal source 2 that provides an original video signal before compression processing (original video signal), an uncompressed audio signal source 3 that provides an original audio signal before compression processing, A code processing system for inputting the non-compressed video signal S2 and the non-compressed audio signal S3, performing predetermined compression processing, encoding, and further multiplexing processing (multiplexing) to output a compression encoded signal S100 in a bit stream form. 100, and a data transmission system or a data storage system 5 for transmitting or storing the bitstream type compressed coded signal S1 from the code processing system 100. As the data transmission system or the data storage system 5, when data is stored, for example, a CD
ROM, LD, video tape, etc., and when data transmission is performed, for example, a television broadcast communication system, a communication satellite system, a data communication system, etc. The video signal and audio signal processing apparatus also receives the bit-stream-type compressed coded signal S5 sent from the data transmission system or the data storage system 5, and reverses the multiplexing process (multiplexing) in the code processing system 100. Decomposition processing (demultiplexing), decompression processing opposite to compression in the code processing system 100, and decoding equivalent to the uncompressed video signal S2 and uncompressed audio signal S3 before being input to the code processing system 100. Decoding processing system 6 for decoding the uncompressed video signal S6A and the decoded uncompressed audio signal S6B
Has 00. The video signal and audio signal processing device further includes a code processing system 100 and a decoding processing system 600.
In order to specify the processing of the above, the guideline (reference signal) S4A and the decoding processing system 6 to the coding processing system 100 are respectively provided.
A constraint parameter for transmitting the guideline (reference signal) S4B to A. Constraint parameter system target decoder (STD: System Target Decoder) 40
Has 0.

The constraint parameter system target decoder 400 is also called a hypothetical system target decoder, a system reference decoder, or a reference decoding processing system, but here,
Below, constraint parameter system target decoder,
Alternatively, it is simply called a system target decoder or the like. Constraint Parameter System Target Decoder 40
0 is CCITT H. It is used in international standards such as the H.261 and MPEG1 video standards and provides guidance for designers of video signal encoders and video signal decoders. In the MPEG1 system standard, the system target decoder (STD) also has a reference audio signal decoder. In these reference models, each video and audio signal decoder also has a buffer with the recommended buffer size, and a standard that describes how to operate the video and audio signal decoder. The model with the recommended buffer size is called the "constrained parameter system target decoder (STD)". In practice, it is expected that there will not be so many actual decoding systems that will outperform the constraint parameter system target decoder (STD). Therefore, when the bitstream is formed, and when it is necessary to reach a large number of real decoders, the coding system generally creates a bitstream suitable for the constraint parameter system target decoder. . These multiplexed bitstreams are Constraint System Parameter Streams (CSP).
S).

The constraint parameter system target decoder 400 has a demultiplexing unit 401, a video signal buffer 402, an audio signal buffer 403, a video signal decoder 404, and an audio signal decoder 405. In this example, the video signal buffer 402 has a storage capacity of 46 Kbytes and the audio signal buffer 403 has a storage capacity of 4 Kbytes. The demultiplexing unit 401 has a switching circuit, and the video signal decoder 404 and the audio signal decoder 405 are integrally configured by a high-speed digital signal processing device (DSP) having a configuration suitable for high-speed arithmetic processing. It is desirable in terms of structure and flexibility.

FIG. 6A shows a constraint parameter (multiplexing) system bit stream CPS input to the constraint parameter system target decoder 400.
The format of P is shown. This bit stream is composed of a plurality of packs (PACK) arranged in time series, and each pack includes a header (HEADER), a video signal packet (PACKET), and an audio signal packet. Each video signal packet includes a video signal for each frame of the video signal and a time stamp (TI) indicating the time of the frame.
Packet header including ME STAMP (PACK)
ET HEADER). Each audio signal packet has a predetermined unit
Each audio signal and a packet header containing a time stamp indicating the time of the unit. The time stamp of frame n + 1 for the video signal is called the video time stamp vts, and the time stamp of unit m + 1 for the audio signal is called the audio time stamp ats. That is, the code processing system 100 encodes the uncompressed video signal S2 and the uncompressed audio signal S3 into a multiplexing bit stream of the format shown in FIG. The constraint parameter system target decoder 400 sends out and inputs and decodes the multiplexed bitstream S5 including the compression coded signal based on this bitstream.

The uncompressed video signal S2 and the uncompressed audio signal S3 input to the code processing system 100 have different data numbers and speeds, and also different compression rates. Therefore, even if the video signal and the audio signal input to the code processing system 100 at the same time are compressed, the coded video signal and the coded audio signal having the same speed and the same size are not provided. Also, for example, regarding a video signal, the compression rate differs depending on the content of the video signal. The same applies to audio signals. Therefore, the coded video signal and the coded audio signal in a fixed state (condition) are not output from the code processing system 100. In the decoding processing system 600, the original video signal and audio signal are decoded to obtain a non-compressed video signal S6A.
And when decoding as the decoded uncompressed audio signal S6B, it is necessary to synchronize in timing. Therefore,
In order to realize such synchronization, MPEG stipulates that the above-mentioned time stamp is added to each of the video signal and the audio signal for each frame. That is, the video signal time stamp and the audio signal time stamp indicate the time that defines the clock for performing the synchronized decoding of the video signal and the audio signal, and the audio signal time stamp performs the decoding of the audio signal. Shows the time to generate the clock for. The purpose of using the time stamp is to solve the problem of buffering and to copy the data in the code system, in addition to the above-mentioned synchronization.

FIG. 7 is a block diagram of the decoding processing system 600.
The decoding processing system 600 includes a demultiplexing unit 601,
Video signal bit stream configuration conversion processing unit 602, video signal reception buffer 603, video signal decoder (decoder) 604, picture rate control circuit 605, audio signal bit stream configuration conversion processing unit 606, audio signal reception buffer 607, audio signal decoding A sampling rate control circuit 609 and a sampling rate control circuit 609. Demultiplexing unit 601
Is a multiplexed bitstream S of the format described above.
5 is input, video signal, video time stamp vt
s, audio signal, audio time stamp ats
Disassemble (separate). The video signal bit stream configuration conversion processing unit 602 inputs the separated video signal and video time stamp vts, and converts them into the format shown in FIG. 6 (B). The video signal reception buffer 603 sequentially stores the converted video signals and outputs them to the video signal decoder 604 in the stored order. Similarly, the audio signal bitstream configuration conversion processing unit 606 determines the decomposed audio signal and audio time stamp ats.
Is input to convert to the format shown in FIG.
The audio signal reception buffer 607 sequentially stores the converted audio signals and outputs them to the audio signal decoder 608 according to the stored order. Video signal decoder 60
4 is a video signal reception buffer 60 based on the timing signal output from the picture rate control circuit 605.
The video signal output from 3 is decoded. The audio signal decoder 608 includes a sampling rate control circuit 609.
The audio signal output from the audio signal receiving buffer 607 is decoded based on the timing signal output from the.

The above-mentioned video signal receiving buffer 603 and audio signal receiving buffer 607 will be described. It is impossible to decode the video signal and the audio signal by using the clocks which are completely matched at the time of decoding.
The first reason is that the compression rates are different as described above. For the second reason, decoding of an audio signal in the audio signal decoder 608 will be described, for example. The input data rate of the audio signal input to the audio signal decoder 608 which decodes at a fixed video rate and the transfer video rate of the audio signal output from the data transmission system or the data storage system 5 cause a sampling rate clock error. Change depending. Furthermore, since one audio signal and access unit are generally input to the audio signal decoder 608 at a time, the transfer rate of the multiplexed bit stream S5 from the data transmission system or the data storage system 5 and the audio signal decoder 6
It does not match the data rate of the audio signal input to 08. Therefore, an audio signal reception buffer 607 is provided in the preceding stage of the audio signal decoder 608, and is configured to adjust the above-mentioned data rate mismatch. FIG. 8 illustrates the relationship described above.

Further, as illustrated in FIG. 9, the video signal is transmitted for each frame (or, in the code processing system 100).
Since each field is compressed and variable length coding is performed, the input data rate to the video signal decoder 604 greatly changes depending on the compression of the video signal in the coding processing system 100. Therefore, the storage capacity of the video signal reception buffer 603 is larger than the storage capacity of the audio signal reception buffer 607. For example, the storage capacity of the video signal reception buffer 603 is 46 Kbytes, whereas the storage capacity of the audio signal reception buffer 607 is 4 Kbytes.
It is K bytes. FIG. 10 shows a video signal reception buffer 60.
3 or as a reception buffer of the audio signal reception buffer 607 (hereinafter, the video signal reception buffer 603 is exemplified). Figure 10
As shown in (A), this buffering includes:
The data amount obtained by subtracting the storage capacity of the video signal reception buffer 603 indicated by the broken line from the amount of data input to the video signal reception buffer 603 is the video signal reception buffer 60.
3 does not exceed the amount of data read out, that is, does not cause underflow, and the amount of data read out from the video signal reception buffer 603 is equal to the amount of data input to the video signal reception buffer 603. Ideally, it should not be exceeded, that is, should not cause overflow. However, as illustrated in FIG. 10B, this buffering may have overflows or underflows.

As a method of preventing overflow or underflow in this buffering, for example, the processing illustrated in FIGS. 11A to 11C is considered. The first method is called the “storage media slave method” as illustrated in FIG. 11A, and the storage capacity of the video signal reception buffer 603 is calculated from the data amount L1 input to the video signal reception buffer 603. Does not exceed the amount L3 of data read from the video signal reception buffer 603, and the amount L3 of data read from the video signal reception buffer 603 exceeds the amount L1 of data input to the video signal reception buffer 603. The amount of data input to the video signal reception buffer 603 is controlled as indicated by the curve L1 ′ so as not to exceed the limit. Curve L
2 shows a change in the amount obtained by subtracting the storage capacity of the video signal reception buffer 603 from the data L1 input to the video signal reception buffer 603, and a curve L2 ′ is the controlled actual data input to the video signal reception buffer 603. Shows the change in the amount of. The second method is called a “decoder slave method” as illustrated in FIG. 11B, and the data amount L1 input to the video signal reception buffer 603 is the storage capacity of the video signal reception buffer 603. The data amount L2 obtained by subtracting
The video signal decoder so that the amount L3 of data read from the video signal receiving buffer 603 does not exceed the amount L3 of data read from the video signal receiving buffer 603. The video signal reception buffer 60 by changing the frame rate of 604
Read data from 3. The change in the amount of data actually read from the video signal reception buffer 603 is shown by the curve L.
Shown as 3 '. The video signals have been described above,
Also in the case of audio signals, the audio signal decoder 608
The sampling rate of is changed to adjust the amount of data read from the audio signal reception buffer 607. The third method is to adjust the amount of data read from the video signal reception buffer 603 as illustrated in FIG. 11C. For example, the access unit is skipped or redisplayed to receive the video signal. The amount of data read from the buffer 603 is adjusted. The curve L3 ′ is adjusted to show the change in the amount of data read from the video signal reception buffer 603.

However, changing the frame rate or sampling rate of the above-mentioned decoder (decoder) or the transfer rate from the data transmission system or the data storage system 5 is related to the outside of the video signal and audio signal processing device. Because it affects the device
It cannot be changed freely and is limited to a certain range. As a result, when overflow or underflow frequently occurs in buffering, it cannot be completely prevented. The malfunction of the decoding process due to the overflow or underflow in the buffering occurs particularly at the time of starting the decoding. Therefore, in the decoder, there has been considered a method of solving this problem by performing a process called "startup delay (delay at start time)" that delays the decoding process at the initial stage of reproduction.

FIG. 12 shows various modes of buffering based on the startup delay. FIG. 12 (A) shows ideal buffering regardless of startup delay, and FIG. 12 (B) shows buffering when startup delay is properly performed.
FIG. 12C shows a case where the startup delay is long and the video signal reception buffer 603 overflows.
(D) shows a case where the startup delay is short and underflow occurs.

In MPEG, the system clock reference SCR for phase synchronization can be described in the header of each pack as described above, and the system clock reference SCR can be used to define the transfer bit rate. Furthermore, in MPEG, the video signal packet is described in the header of the audio signal packet, and the time stamp can be used to control the frame rate or the sampling rate. That is, FIG.
As illustrated in FIG. 3, the system clock reference SCR indicates the time of the multiplexed bitstream S5 input from the data transmission system or the data storage system 5 to the decoding processing system 600,
The time stamp of the video signal packet or the audio signal packet indicates the time when the video signal or the audio signal is output from the video signal reception buffer 603 or the audio signal reception buffer 607. These times, for example, can be recorded in the absolute time by using the reference clock 90KH _Z by using a crystal oscillator.
In this way, the difference between the system clock reference SCR and the time stamp can be used for the startup delay. In FIG. 13, a symbol DTS indicates a decoder time stamp which means a decoding time, a symbol PTS indicates a picture time stamp which means a decoding time of a video signal, that is, a picture, and a symbol H indicates a header.

As described above, when decoding an audio signal and a video signal in MPEG, it is necessary to synchronize the decoding results of both, and a time stamp is used for this synchronization. It is assumed that the decoding processing time of the video signal and the audio signal is 0 second. As shown in FIG. 14, in the frames other than the I picture and the P picture, that is, in the B picture, the decoding time of the access unit indicated by the time stamp is the same as the display time when the B picture is displayed. become. That is, among the video signals sequentially input to the video signal reception buffer 603 via the demultiplexing unit 601, the video signal of the I picture of the i th frame of the m th video signal packet:
After Frame i (I) is read from the video signal reception buffer 603 and decoded at time DTS _m , the video signals (frames) of I picture and P picture provided in the subsequent stage of the video signal decoder 604 are temporarily transferred. Store in I / P buffer. The decoding time and the display time are different between the I picture video signal and the P picture video signal. Therefore, in the header of the video signal packet corresponding to the video signal, DTS and PTS as time stamps indicating the decoding time and the display time are recorded, but the display time PTS of the I picture and P picture video signals is recorded. Is the same as the DTS of the next I picture and P picture, the display time P
TS can be omitted.

However, in the above-mentioned MPEG-based video signal and audio signal processing apparatus,
Video signal bitstream configuration conversion processing unit 602 and audio signal bitstream configuration conversion processing unit 60
I have encountered the problem that the circuit configuration of 6 becomes complicated.
Furthermore, the above-described video signal and audio signal processing device is premised on that the data input to the decoding processing system 600 is a multiplexed bit stream. For example, either a video signal or an audio signal is multiplexed. If it is input without input, it cannot be decoded, and there is a problem in its versatility in consideration of performing various kinds of decoding processing as a decoding processing system.

Therefore, the applicant of the present application (the inventor of the present application) has proposed a video signal and audio signal decoding apparatus which solves the above-mentioned problems (for example, Japanese Patent Application No. 5-63293 filed on February 26, 1993, See "Data Decoding Device"). FIG. 15 shows the configuration of this decoding device. The bit stream at this time is shown in FIG. 6 or FIG. In the bit stream shown in FIG. 16, a plurality of video signal packets and a plurality of audio signal packets are consecutive, and each of the plurality of video signal packets includes a first video signal packet header and a first picture group GOP0.
A fourth video signal packet header and a fourth picture group GOP3 are arranged. The time stamp of this video signal is stored in each video signal packet header. Video signals of 20 frames are stored in each picture group. An audio signal time stamp and an audio signal access unit AAU are stored in the audio signal packet.

This decoding device uses the demultiplexing 5
01, the clock generator 503 for generating a clock of DSP502,90KH _Z, overall time register 504, the video signal receiving buffer 505a, the audio signal receiving buffer 505b, a video signal decoder 506a, audio decoder 506b, a video signal time stamp buffer 507a, audio signal time stamp buffer 5
07b, video signal clock phase synchronization circuit (PLL)
508a and PLL 508b for audio signal clock. The video signal time stamp decomposed from the bit stream in the demultiplexing 501 is stored in the video signal time stamp buffer 507a, and the audio signal time stamp is stored in the audio signal time stamp buffer 507b. Also, the video signal decomposed from the bit stream is a video signal reception buffer 50.
The audio signal stored in 5a and decomposed is stored in the audio signal receiving buffer 505b. The data stored in these buffers 505a and 505b are decoded by the decoders 506a and 506b in synchronization with the clocks from the PLLs 508a and 508b, respectively. In this way, a simple circuit configuration can be obtained.

FIG. 17 illustrates the format of the multiplexed bit stream and its processing. However, this bit stream is shown only for the video signal and omitted for the audio signal. FIG. 18 shows the configuration of an MPEG video signal and audio signal processing device based on this bit stream. The constraint parameter system target decoder 410 includes a demultiplexing unit 41.
1, video signal buffer 412, audio signal buffer 413, directory data buffer 414, video signal decoder 415, audio signal decoder 416,
It has a directory decoder 417. Decoding processing system 61
0 is a constraint parameter system target decoder 410
Is configured similarly to. The code processing system 110 is shown in FIG.
The bit stream illustrated in (A) is generated. The bitstream is a pair of a first directory packet and a first video signal packet corresponding to the directory packet. The first position in the directory packet is the directory packet header,
Subsequently, the first to twentieth pointers P0 to P19 are stored. The video signal packet header is stored at the first position of the video signal packet, followed by the first to twentieth picture groups GOP0 to GOP19. The first pointer P0 is the first picture group GOP0.
The recording position of is specified. Other pointers also specify the position of the corresponding picture group.

As a specific example, a reproducing operation in the video tape recording / reproducing apparatus will be illustrated. In this case, the code processing system 1
10 is a recording system of the video tape recording / reproducing apparatus, and the data transmission system or the data storage system 5 is a video tape.
The decoding processing system 610 is a reproduction system. As shown in FIG. 17B, the user can
ard: FF) operation or first reverse (First Re
(verse: FR) operation before requesting the decoding processing system 610.
Sequentially reads the picture groups from the video tape 5 based on the recorded contents of the directory packet header and the specified contents of the pointer, stores the pointer in the directory buffer, stores the video signal in the video signal buffer, and decodes the video signal. And decode the video signal. As shown in FIG. 17C, when the user requests the first forward operation, the skip operation is performed until the directory data stored in the directory buffer becomes empty, and the picture group is skipped. Then, as shown in FIG. 17D, the pointer is returned to the position where the new directory is stored in the directory buffer. As shown in FIG. 17E, in the fast forward operation, the above-mentioned operation, that is, the feedback operation is performed.

In MPEG, the buffering delay time is specified as described above, and the buffering delay time when phase synchronization is not established is limited to within 1 second.

FIG. 19A is a schematic block diagram of the decoding processing system described above. In this illustration, for example, in a television receiver as an example of the above-described decoding processing system, one of the compressed video signals of a plurality of channels is channel-selected by the demultiplexing circuit 11, and the video signal buffer memory is selected. Video signal decoder 1 once accumulated in 12
6 illustrates a case where the video signal compressed in 6 is subjected to decoding processing such as decompression and output to the reproduction device 20. The demultiplexing circuit 11 functionally corresponds to the demultiplexer 601 shown in FIG. 7 and the demultiplexer 501 shown in FIG. 15, but the demultiplexers 501 and 601 in these examples have a video signal and an audio signal. While the signal is demultiplexed with the signal, the demultiplexing circuit 11 demultiplexes the video signals of a plurality of channels. The video signal buffer memory 12 operates similarly to the video signal receiving buffer 603 illustrated in FIG. 7 and the video signal receiving buffer 505a illustrated in FIG. Video signal decoder 16
Has the same function as the video decoder illustrated in FIGS. 7 and 15. The buffering process between the video signal buffer memory 12 and the video signal decoder 16 is the same as that described with reference to FIG. Although only the video signal processing system has been described in relation to the illustration, the same configuration and processing as described above can be performed for an audio signal.

As illustrated in FIG. 19A, the video signal of channel 1 is input to the video signal buffer memory 12 via the demultiplexing circuit 11, and the video signal buffered in the video signal buffer memory 12 is input. The video signal decoder 16 decodes the signal, and outputs the decoding processing result to the playback device 20. As illustrated in FIG. 19B, when channel switching from channel 1 to channel 2 occurs next, the demultiplexing circuit 11
The video signal of channel 2 is buffered in the video signal buffer memory 12 via the video signal decoder 1
6 performs a decoding process on this new buffered video signal.

[0027]

However, as shown in FIG.
Since the decoding apparatus illustrated in FIG. 1 has only one system of buffer memory 12 and a video signal decoder for a plurality of channels, the above-mentioned 1 second startup delay problem is encountered when switching channels. That is, the video signal is accumulated in the buffer memory 12 by the above-mentioned method and is discharged for the decoding process in the video signal decoder 16, but when the channel is switched at a certain point, it is selected before. Unless all the video signals of the selected channel are discharged from the buffer memory 12, the video signal of the newly selected channel cannot be input to the buffer memory 12 and the video signal decoding process cannot be performed. Therefore, a start-up delay occurs. Since the audio signal is reproduced in the same manner as the video signal, the startup delay similar to the above also occurs for the audio signal. During this start-up delay, the video signal and audio signal of the newly selected channel are not reproduced by the reproducing device 20, so that the video and audio of the newly switched channel are generated despite the user switching the channel. Can't get That is, the current decoding processing system has a problem in response when switching channels.

The problems described above and channel switching in a television receiver or the like occur, and also occur during playback of a video signal. Referring to FIG. 20, the problem of start-up delay during playback will be described. In this example, as shown by the curve CV1, the bit rate for decoding the first part is 3 mega (M) bits / second, and the second part is
The bit rate for decoding the part is 6 Mbit / sec. At the beginning of the first part, when the video signal decoder 16 starts the playback process, there is little start-up delay for this bitstream, which is not a problem. However, at the beginning of the second part, when the video signal decoder 16 starts the playback process, a 1 second startup delay is required for this bitstream, as described above.

FIG. 21 is a graph showing a state in which the video signal is accumulated in the buffer memory 12 after the start-up delay of 1 second. In FIG. 21, the access point has a large amount of image data (intra).
In case of a picture, only the access to the start time of the second part is possible. Intra pictures generally occur regularly in the bitstream of a video signal.
So, if the user requests the beginning of playback at the beginning of the second part, the startup delay of at least 1 second will cause the user to lose at least 1
For about a second, the reproduction information, that is, the reproduction video signal and the reproduction audio signal cannot be obtained.

FIG. 22 is a graph illustrating buffering when the bitstream has a startup delay longer than 1 second. If the bitstream is longer than 1 second, a fast, in other words expensive buffer memory is required, which allows a quick start-up delay with a transmission rate higher than the normal transmission rate. Curve abi (actual that connects *
decoder buffer input) indicates the input of the video signal to the actual buffer memory, and the curve abo (ac
tual decoder buffer output) indicates the output of the video signal to the actual buffer memory, and the curve ibo that connects the circles
(Intended decoder buffer output) indicates the output of the video signal to the buffer memory as a design value, and the curve ovf connecting + indicates the overflow limit of the buffer.
In this example, where the decoding processing system has a high-performance storage medium, the accumulation of the video signal in the buffer memory starts at a rate of, for example, 15 Mbit / sec. As a result, 0.5
After a second, a 7.5 Mbit video signal is accumulated in the buffer memory. The accumulated amount of the video signal is equal to the accumulated amount of the video signal at 1.67 seconds at the rate of 4.5 Mbit / sec. That is, in this example, 0.5 seconds is sufficient to start the buffer memory. In this example,
The video signal is accumulated at the rate of 15 Mbit / sec until the reading of the video signal is started at the rate of 6 Mbit / sec, and when the buffer memory is full, the video signal is accumulated at the rate of 6 Mbit / sec. To change the rate. However, although this method shortens the start-up delay, it requires expensive storage means,
Since rate control is performed, processing becomes complicated.

The present invention relates to the above-described decoding processing method for decoding the compressed video signal and / or the compressed audio signal, which shortens the start-up delay at the time of channel switching or at the time of playback. And a decoding processing system (apparatus).

[0032]

According to the present invention, in addition to one buffer memory means and one decoding means for buffering an image signal and an audio signal with a predetermined delay time, at least one buffer memory similar to the above. Means and at least one pseudo-decoder for invalidating the data stored in the buffer memory means. As described above, the buffer memory means buffers the compressed image signal and / or the compressed audio (sound) signal with a predetermined delay time. The decoding means performs decoding processing such as decompression on the data stored in the buffer memory means. The pseudo decoding means invalidates the data stored in the buffer memory means. Hereinafter, the case of channel selection and the case of playback will be exemplified.

The case of channel switching will be described. A decoding device of the present invention receives at least a compressed image signal for a plurality of channels, outputs a compressed image signal for a channel selected from the plurality of channels, and an image output from the selection output unit. Operatively connected to the selective output means to receive a signal,
At least two buffer memory units that can operate in parallel, and at least one decoding unit that is operatively connected to one of the buffer memory units and that reads and decodes the image signal stored in the connected buffer memory unit. Of the buffer memory means, the decoding means is not operatively connected to any one of the buffer memory means, and the image signal stored in the connected buffer memory means is invalidated. And at least one pseudo-decoding means for performing a digitization process. Preferably, one of the decoding means is provided in accordance with continuous channel switching,
The pseudo decoding means is provided two before and after the decoding means in terms of the channel position, three buffer memory means are provided, and the selection is made in the buffer memory means operatively connected to the decoding means. The image signal of the selected channel is applied from the output means to accumulate the image signal, and the decoding means decodes the image signal accumulated in the buffer memory means in which the image signal is accumulated, and the pseudo decoding means. Pseudo-decoding means at a position subsequent to the channel selection invalidates the image signal of the buffer memory means in which the image signal was stored immediately before the channel selection.

The case of playback will be described. The decoding device of the present invention includes at least two buffer memory means capable of operating in parallel for receiving at least a compressed image signal, and operatively connected to any of the buffer memory means, and stored in the connected buffer memory means. At least one decoding means for reading and decoding the generated image signal, and one of the buffer memory means, to which the decoding means is not operatively connected, operatively connected to one of the buffer memory means, And at least one pseudo decoding means for invalidating the image signal stored in the connected buffer memory means. In this decoding device, when playback is requested, the image signal from the requested playback time is buffered in the buffer memory means operatively connected to the pseudo decoding means, and the decoding means uses the new decoding means. The buffered image signal is decoded, and the pseudo decoding means invalidates the image signal stored in the buffer memory means in which the image signal before the playback request is stored.

[0035]

[Operation] The operation of channel switching will be described. When the channel is switched, the selection output means buffers the image signal of the newly selected channel in the buffer memory means in the unused state, and the decoding means decodes the newly buffered image signal. The pseudo decoding unit invalidates the image signal stored in the buffer memory unit in which the image signal of the channel before selection is still stored. Thereby, the image signal of the newly selected channel can be decoded without waiting for the time for the decoding means to discharge the image signal stored in the buffer memory means before selection, that is, without waiting for the startup delay. The pseudo decoding means does not need to have a function of actually performing the decoding processing, but simply invalidates the data in the buffer memory means, and its configuration is simple.

The action of playback will be described. When playback is requested, the image signal from the requested playback time is buffered in the unused buffer memory means, and the decoding means decodes the newly buffered image signal. The pseudo decoding means invalidates the image signal stored in the buffer memory means in which the image signal before the playback request is still stored.

[0037]

Embodiments of the decoding method and the decoding apparatus of the present invention will be described. FIG. 1 shows a video signal decoding apparatus 10 for decoding a video signal as a first embodiment of the decoding apparatus of the present invention.
It is a block diagram of. The decoding device shown in FIG. 1 corresponds to the decoding device described with reference to FIG. 19 as a conventional technique. That is, the video signal decoding device 10 illustrates a decoding process when channel switching is performed for a plurality of channels in, for example, a television receiver that performs a decoding process such as decompressing a compressed video signal. The audio signal has the same configuration, but is omitted for the sake of illustration.

The signal processing system for providing the video signal and the audio signal to the video signal decoding apparatus 10 is the signal processing system illustrated in FIG. 5 and FIG. The signal and the signal are simultaneously compressed, time stamped and sent to the data storage system 5 or the data transmission system 5, and the decoding processing system 6
At 00, the video signal decoding device 10 decodes such compressed video and audio signals. The data transmission system or the data storage system 5 is, for example, a satellite communication system or a data communication system as a data transmission system, and a data storage system such as a CD-RO.
M, LD, video tape, etc. are targeted. Hereinafter, in the present embodiment, a case where a satellite communication system, a CD-ROM, an LD or the like is used as the data transmission system or the data storage system 5 will be described.

The video signal decoding apparatus 10 shown in FIG.
Demultiplexing circuit 11, four first video signal buffer memories 12 arranged in parallel to fourth video signal buffer memory 15, four parallel first video signal decoders 16 to fourth arranged It has a video signal decoder 19 and one playback device 20. In the video signal decoding device 10, the demultiplexing circuit 11 outputs the video signal of the selected channel to the video signal buffer memory corresponding to the channel according to the channel switching. The present embodiment exemplifies a case where the number of channels is four. The first video signal buffer memory 12 to the fourth video signal buffer memory 15 cooperate with the corresponding video signal decoders to perform the buffering operation with the delay time of the above-described predetermined time. As the buffer memory, it is not necessary to use one that operates particularly at high speed as described with reference to FIG. First video signal decoder 16
Each of the fourth video signal decoders 19 basically has the same configuration and function as the decoder described with reference to FIG. 19, and the corresponding buffer memories 12 to 19 provided in the preceding stage thereof. The video signal stored in is decoded based on the decoding processing method described above. The video signal decoded by the video signal decoder corresponding to the selected channel is reproduced by the reproducing device 20. In the present embodiment, the reproducing apparatus 20 only reproduces a video signal, but when the reproducing apparatus 20 also decodes an audio signal, the reproducing apparatus 20 also reproduces an audio signal.

FIG. 1 shows a state in which channel 2 is selected. Therefore, in this state, the video signal is stored in the second video signal buffer memory 13 from the demultiplexing circuit 11, and the second video signal decoder 17 is stored in the second video signal buffer memory 13. The video signal is decoded, and the decoding result is output to the playback device 20. When the user switches from channel 2 to channel 1, the video signal of channel 1 is output from the demultiplexing circuit 11 to the first video signal buffer memory 12, and the video signal of channel 1 is output to the first video signal buffer memory 12. Has been accumulated. Along with this, the first video signal decoder 16 is activated for the decoding process, and the second video signal decoder 1
7 is suspended for the decoding process. This operatively connects the playback device 20 to the first video signal decoder 16 and disconnects the second real video signal decoder 17 from the playback device 20. The first video signal decoder 16 decodes the video signal stored in the first video signal buffer memory 12 and outputs the decoding result to the playback device 20.
There is no startup delay for this switch. It should be noted that although a new video signal is no longer input to the second video signal buffer memory 13 corresponding to the previously selected channel 2, it is still stored in the second video signal buffer memory 13 before channel switching. There is still video signal left. Therefore, the second video signal decoder 17 uses the startup delay function to perform the second video signal decoding.
The video signal remaining in the video signal buffer memory 13 is discharged so that the second video signal buffer memory 13 can be used without the start-up delay even when the next channel is switched.

As described above, when the buffer memory and the video signal decoder are provided in correspondence with the number of channels, it is possible to immediately respond to channel switching without a start-up delay. However, the video signal decoding apparatus 10 illustrated in FIG.
As many buffer memories and real video signal decoders as the number of channels are provided, as described above, each of the video signal decoders performs buffer processing in cooperation with the buffer memory, as well as synchronization processing based on time stamps, Since the decoding process such as the decompression process is performed at high speed, the circuit configuration is complicated, and the cost is high if configured using a DSP or the like. Therefore, another embodiment for solving the above problem will be described.

FIG. 2 is a block diagram of a video signal decoding apparatus 10A as a second embodiment of the decoding apparatus of the present invention. The video signal decoding apparatus 10A includes a demultiplexing circuit 11, a first video signal buffer memory 12 to a fourth video signal buffer memory 15, a first real video signal decoder 16 and a second real video signal. Decoder 17,
It has a first pseudo video signal decoder 21 and a second pseudo video signal decoder 22, and a reproduction device 20. Also in the second embodiment, since the number of channels is 4, four buffer memory systems are provided. The first real video signal decoder 16 and the second real video signal decoder 17 are shown in FIG.
Although it has substantially the same configuration and function as the first video signal decoder 16 and the second video signal decoder 17 illustrated in FIG. 2, in the second embodiment, "real" is added. Means that the decoding process is actually performed, and the first pseudo video signal decoder 2 that does not actually perform the decoding process
The “pseudo (Qu) of the first and second pseudo video signal decoders 22
asi) ”to distinguish it.

The first pseudo video signal decoder 21 and the second pseudo video signal decoder 22 substantially invalidate the video signal stored in the buffer memory operatively connected to the preceding stage. It is a thing. Some specific processing examples of this invalidation processing will be illustrated. In the first invalidation method, the pseudo video signal decoder 21 (or 22) uses the time stamp from the packet header described above and the picture stored in the buffer memory based on the picture rate from the video signal sequence layer. The header (head position) of is detected, and the video signal after that is invalidated. In the second invalidation method, the pseudo video signal decoder 21 (or 22) forcibly clears the control word indicating the storage state of the video signal stored in the buffer memory and the video signal is stored in the buffer memory. So that it doesn't exist. In the third invalidation method, since the buffer memory of the pseudo video signal decoder 21 (or 22) usually operates as a FIFO (First-in-First-Out) in many cases, this FIFO processing state is cleared to Make sure there is no video signal in the buffer memory.
Since the first pseudo video signal decoder 21 and the second pseudo video signal decoder 22 are simple memory control processing in this way, they can have a simple configuration and can be inexpensively constructed. That is, the complicated circuit configuration of the first real video signal decoder 16 and the second real video signal decoder 17 does not occur. Moreover, since the first pseudo video signal decoder 21 and the second pseudo video signal decoder 22 forcibly invalidate the video signal in the buffer memory, even if the next channel is selected, it can respond immediately.

FIG. 2A shows a state in which the first real video signal decoder 16 and the second real video signal decoder 17 are processing the channel 1 video signal and the channel 2 video signal, respectively. Indicates. As shown in FIG. 2B, when the user selects the channel 3, the demultiplexing circuit 11 has the third video signal buffer memory 14 already empty by the first pseudo video signal decoder 21. To output the video signal of channel 2. As a result, the video signal starts to be stored in the third video signal buffer memory 14. At the same time, the first real video signal decoder 16 is disconnected from the operatively connected first video signal buffer memory 12 and operatively connected to the third video signal buffer memory 14, The video signal stored in the video signal buffer memory 14 is decoded. By this decryption processing, the playback device 20 receives the second
Is operatively connected to the first real video signal decoder 16 and the video signal decoded by the first real video signal decoder 16 is output to the playback device 20. On the other hand, a first pseudo video signal decoder 21 is operatively connected to the first video signal buffer memory 12 separated from the first real video signal decoder 16 and is connected to the first video signal buffer memory 12. Disable the remaining video signal.

In the second embodiment, since the buffer memories are provided by the number of channels, the connection relationship between the demultiplexing circuit 11 and the first video signal buffer memory 12 to the fourth video signal buffer memory 15 is fixed. Incidentally, the first video signal buffer memory 12 to the fourth
Of the video signal buffer memory 15, the first real video signal decoder 16 and the second real video signal decoder 17, and the first pseudo video signal decoder 21 and the second pseudo video signal decoder 22. The case where the connection relationships are operatively connected has been illustrated. In the second embodiment, the first pseudo video signal decoder 21 performs the invalidation process of the video signal of the buffer memory operatively connected to the first real video signal decoder 16 to obtain the second pseudo video signal. The video signal decoder 22 is the second
The video signal in the buffer memory operatively connected to the pseudo video signal decoder 22 in FIG. Since the video signal decoding apparatus 10A of the second embodiment is provided with the two real video signal decoders 16 and 17, even if the channel selection is arbitrarily performed, there is no start-up delay for the channel that is quickly selected. In addition, a decoded video signal can be provided.

FIG. 3 is a block diagram of a video signal decoding apparatus 10B as a third embodiment of the decoding apparatus of the present invention. The video signal decoding device 10B has a configuration particularly suitable for a system in which channels are switched in order. That is, pressing the up shift button in the channel select switch (not shown) once increases the number of channels by one and pushes the down shift button to 1.
This is a configuration suitable for a channel selection method in which the number of channels decreases by one when pressed twice. The video signal decoding device 10B includes a demultiplexing circuit 11, a first video signal buffer memory 12 to a third video signal buffer memory 14, a real video signal decoder 16, and a first pseudo video signal decoder 2.
It has first and second pseudo video signal decoders 22 and a playback device 20. That is, the video signal decoding device 10B includes three buffer memories 12 to 15 and one real video signal decoder 16 regardless of the number of channels.
Two pseudo video signal decoders 21 and 22 are provided. The real video signal decoder 16 performs a decoding process on the video signal of the selected channel. When the number of channels is increased by one, the first pseudo video signal decoder 21 invalidates the video signal remaining in the buffer memory which the real video signal decoder 16 has read until then. When the number of channels decreases by one, the second pseudo video signal decoder 22 invalidates the video signal remaining in the buffer memory which was read by the real video signal decoder 16 until then.

In FIG. 3A, the channel 2 is selected, and the actual video signal decoder 16 reads the video signal from the second video signal buffer memory 13 which stores the video signal of the channel 2, Playback device 20 after decryption processing
The state in which the decoding processing result is output is shown in FIG. When the user presses the up shift button in the channel selection switch, channel 3 is selected, as shown in FIG. 3 (B). The demultiplexing circuit 11 has a third pseudo video signal decoder 22 which has been previously disabled by the third pseudo video signal decoder 22.
The video signal of channel 3 is started to be output to the video signal buffer memory 14 of. The connection relationship between the real video signal decoder 16 and the buffer memory is changed to the second by the channel switching.
The video signal buffer memory 13 is switched to the third video signal buffer memory 14. The real video signal decoder 16 decodes the video signal stored in the third video signal buffer memory 14 having a new connection relationship. on the other hand,
The first pseudo video signal decoder 21 invalidates the video signal in the second video signal buffer memory 13 in which the switched channel 2 video signal remains. Further, when the user presses the up shift button in the channel selection switch, channel 4 is selected as shown in FIG. 3 (C). The demultiplexing circuit 11 starts to output the channel 4 video signal to the first video signal buffer memory 12 which has been previously invalidated by the second pseudo video signal decoder 22. The connection relationship between the real video signal decoder 16 and the buffer memory is switched from the third video signal buffer memory 14 to the first video signal buffer memory 12 by the channel switching. The actual video signal decoder 16 decodes the video signal stored in the first video signal buffer memory 12 having a new connection relationship. On the other hand, the first pseudo video signal decoder 21 invalidates the video signal of the third video signal buffer memory 14 in which the switched channel 3 video signal remains.

The case where the user pushes the upper shift button in the channel selection switch has been described. However, in the case where the user pushes the lower shift button, the second order is reversed in the reverse order.
The pseudo video signal decoder 22 of the real video signal decoder 16
Disables the buffer memory separated from.
Thus, in the third embodiment, the buffer memory,
The connection state of the real video signal decoder 16 and the pseudo video signal decoders 21 and 22 changes depending on the channel selection state. According to the third embodiment, it is sufficient to provide three parallel buffer memories, one real video signal decoder 16, and two pseudo video signal decoders 21 and 22 without depending on the number of channels. However, the video signal decoding device 10B can be realized at low cost.

FIG. 4 is a block diagram of a video signal decoding apparatus 10C as a fourth embodiment of the decoding apparatus of the present invention. The video signal decoding device 10C includes a demultiplexing circuit 1
1, first video signal buffer memory 12 and second video signal buffer memory 13, real video signal decoder 1
6. Pseudo video signal decoder 21 and reproducing device 20
Have. That is, the video signal decoding device 10B has two buffer memories 12 independent of the number of channels.
˜15, one real video signal decoder 16 and one pseudo video signal decoder 21. The real video signal decoder 16 performs a decoding process on the video signal of the selected channel. The pseudo video signal decoder 21 invalidates the video signal remaining in the buffer memory read by the real video signal decoder 16 until then.

In FIG. 4A, the channel 1 is selected, and the actual video signal decoder 16 reads the video signal from the first video signal buffer memory 12 which stores the video signal of the channel 1, Playback device 20 after decryption processing
The state in which the decoding processing result is output is shown in FIG. When the user selects channel 2, channel 2 is selected, as shown in FIG. The demultiplexing circuit 11 includes a second video signal buffer memory 13 that has been invalidated in advance by the pseudo video signal decoder 21.
Then, the video signal of channel 2 is started to be output. The connection relationship between the real video signal decoder 16 and the buffer memory is changed by the channel switching to the first video signal buffer memory 12
To the second video signal buffer memory 13. The actual video signal decoder 16 decodes the video signal stored in the second video signal buffer memory 13 having a new connection relationship. On the other hand, the pseudo video signal decoder 21 uses the first video signal of the switched channel 1 as the first video signal.
The video signal in the video signal buffer memory 12 is invalidated.

As described above, in the fourth embodiment, the connection states of the buffer memories 12 and 13, the real video signal decoder 16 and the pseudo video signal decoder 21 change depending on the channel selection state. According to the fourth embodiment, two parallel buffer memories, 1
Since only one real video signal decoder 16 and one pseudo video signal decoder 21 need be provided, the circuit configuration is simple and the video signal decoding device 10C can be realized at low cost.

Although the above-mentioned first to fourth embodiments exemplify the case of performing channel selection, the above-mentioned video signal decoding device can be applied to the case of performing playback.
In the case of playback, the difference between channel selection and playback is that the video signal before playback corresponds to the video signal of the previously selected channel, and the video signal after playback is of the newly selected channel. It corresponds to a video signal. That is, for example, when the video signal decoding device 10C of FIG. 4 is illustrated, in FIG. 4A, when the video signal before playback is decoded as channel 1, when there is playback, channel 2 is used. As a result, the video signal to be played back is decoded. As a result, the real video signal decoder 16 starts playing back the second video signal buffer memory 13 from the time of playback.
The pseudo video signal decoder 21 invalidates the video signal stored in the first video signal buffer memory 12, and prepares for the next playback. According to the present invention, even in playback, the video signal after playback can be reproduced without a start-up delay.

It is needless to say that the playback processing is not limited to the video signal decoding device illustrated in FIG. 4 and the video signal decoding device illustrated in FIGS. 1 to 3 can be applied.

The above embodiments have described the case where the compressed and input video signal is buffered and the decoding processing such as decompression is performed. However, the present invention is not limited to such processing of the video signal and the compression processing is performed. When buffering the input audio signal and performing decoding processing such as decompression,
Also, both the compressed and input video signal and audio signal can be processed in the same manner as described above.

[0055]

As described above, according to the present invention, a video signal and an audio signal can be reproduced without a start-up delay in either case of playback or channel switching.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a video signal decoding device as a first embodiment of a decoding device of the present invention.

FIG. 2 is a configuration diagram of a video signal decoding device as a second embodiment of the decoding device of the present invention.

FIG. 3 is a configuration diagram of a video signal decoding device as a third embodiment of the decoding device of the present invention.

FIG. 4 is a configuration diagram of a video signal decoding device as a fourth embodiment of the decoding device of the present invention.

FIG. 5 is a configuration diagram of a conventional video signal and audio signal processing device based on MPEG.

6 is a diagram showing a format of a constraint parameter bitstream in FIG. 5, FIG. 6A shows a bitstream multiplexed in the code processing system in FIG. 5, and FIG. 6B is a format-converted signal in a decoding processing system. Indicates the format.

7 is a configuration diagram of a decoding processing system shown in FIG.

FIG. 8 is a diagram showing a timing relationship between an audio signal input to an audio signal receiving buffer and an audio signal input to an audio signal decoder in a conventional decoding processing system.

FIG. 9 is a diagram showing another timing relationship between the audio signal input to the audio signal receiving buffer and the audio signal input to the audio signal decoder in the conventional decoding processing system.

FIG. 10 is a diagram showing overflow and underflow in a buffer.

11 is a diagram showing a method for preventing the overflow or underflow shown in FIG.

FIG. 12 is a diagram illustrating a startup delay.

FIG. 13 is a diagram showing another buffering process.

FIG. 14 is a diagram showing still another buffering process.

FIG. 15 is a block diagram of a decoder of the prior application.

16 is a diagram showing a bitstream processed by the decoder shown in FIG.

FIG. 17 is a diagram showing another conventional bit stream.

FIG. 18 is a block diagram of another conventional video signal and audio signal processing device based on MPEG.

FIG. 19 is a diagram showing an outline of a conventional decoding device.

FIG. 20 is a first graph showing a startup delay.

FIG. 21 is a second graph showing a startup delay.

FIG. 22 is a third graph showing a startup delay.

[Explanation of symbols]

1 ... Code processing system 2 ... Uncompressed video signal source 3 ... Uncompressed audio signal source 4 ... Constraint parameter system target decoder 5..Data transmission system or data storage system 6. Decoding processing system 10-10C ··· Video signal decoding device 11. Demultiplexing circuits 12-15 ... Video signal buffer memory 16-19 ... Real video signal decoder 20..Playback device 21-24 ... Pseudo video signal decoder

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04B 14/04 G11B 20/10 H04J 3/22 H04N 7/24

Claims (5)

(57) [Claims] 1. At least a compressed image signal is received for a plurality of channels, an image signal compressed for a selected one of the plurality of channels is buffered in a buffer memory means with a predetermined delay time, and the buffered. A method for decoding a newly selected image signal, wherein the image signal of the newly selected channel is buffered in an unused buffer memory means, the newly buffered image signal is decoded, and A decoding method for invalidating an image signal accumulated in a buffer memory means in which an image signal of a channel is accumulated. 2. A means for receiving at least a compressed image signal for a plurality of channels and outputting a compressed image signal for a channel selected from the plurality of channels, and an image signal output from the selection output means. At least two parallel operable buffer memory means operatively connected to the select output means for receiving and buffering the image signal with a predetermined delay time; and operably connected to any of the buffer memory means Is
At least one decoding means for reading and decoding the image signal stored in the connected buffer memory means, and one of the buffer memory means to which the decoding means is not operatively connected. A decoding device operatively connected to the memory means and having at least one pseudo decoding means for invalidating the image signals stored in the connected buffer memory means. 3. The decoding means is provided one, the pseudo decoding means is provided two in front and in the back of the decoding means in terms of channel position, three buffer memory means are provided, and the channel switching is provided. Is sequentially and continuously performed, and the image signal of the channel selected from the selection output means is applied to the buffer memory means operatively connected to the decoding means to accumulate the image signal, and the decoding means is The image signal accumulated in the buffer memory means in which the image signal is accumulated is decoded, and the pseudo decoding means at the position following the channel selection of the pseudo decoding means stores the image signal immediately before the channel selection. The decoding device according to claim 2, wherein the image signal of the buffer memory means is invalidated. 4. Accepting at least a compressed image signal,
A method of buffering a compressed image signal in a buffer memory means with a predetermined delay time and decoding the buffered image signal, comprising the steps of: when playback is requested; An image stored in the buffer memory means in which the image signal is buffered in the unused buffer memory means, the newly buffered image signal is decoded, and the image signal before the playback request is stored. A decoding method that nullifies the signal. 5. Accepting at least a compressed image signal,
At least two buffer memory means capable of operating in parallel for buffering the image signal with a predetermined delay time, and operably connected to any of the buffer memory means,
At least one decoding means for reading and decoding the image signal stored in the connected buffer memory means, and one of the buffer memory means to which the decoding means is not operatively connected. At least one pseudo-decoding means operatively connected to the memory means for invalidating the image signals stored in the connected buffer memory means, the playback being requested when playback is requested. The image signal from the back time is buffered in the buffer memory means operatively connected to the pseudo decoding means, the decoding means decodes the newly buffered image signal, and the pseudo decoding means is A decoding device for invalidating the image signal stored in the buffer memory means in which the image signal before the playback request is stored.