JP3400196B2 - Cell interval control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ATM (Asynchronou).
s Transfer Mode: Used for asynchronous transfer mode. The present invention is suitable for use in ATM exchanges. The present invention is suitable for use in a cell copy device. In particular, it relates to a cell interval control technique. The present invention relates to an improvement of a prior application (Japanese Patent Application No. 7-097055, which has not been published when the present application is filed).

[0002]

2. Description of the Related Art Fixed length packets called cells are used for ATM communication. Generally, the cell transfer rate is
The upper limit is set by the contract between the telecommunications carrier and the user. Specifically, an upper limit is set for the number of cells arriving per unit time, and cells arriving beyond that are discarded. The user side is required to comply with this contract condition and avoid the situation where the cell is discarded. One way to do this is to control the cell spacing. Cells arriving in bursts, ignoring the contract conditions, are stored in a temporary cell buffer and retransmitted at cell intervals that comply with the contract conditions.

This conventional example will be described with reference to FIGS. FIG. 17 is a conceptual diagram of a conventional cell spacing control device. FIG. 18 is a diagram showing the spacing between input and output cells of the conventional cell spacing control device. FIG. 19 is a block diagram of a conventional cell spacing control device. FIG. 20 is a diagram for explaining a conventional cell buffer. FIG. 21 is a conceptual diagram of an ATM communication network. In the cell interval control device 1 of the conventional example, cells that arrive in a burst are temporarily stored in the cell buffer CB, which is a FIFO memory, and retransmitted at a predetermined cell interval T. At this time, the burst property can be reduced by increasing T to some extent, but it is necessary to increase the capacity of the cell buffer CB. Further, if T is made small to reduce the capacity of the cell buffer CB, there is a drawback that the cell is transmitted at a high peak rate even though a small burst is continued for 5 cells, which is useful for cell interval control. It loses its character.

In FIG. 19, reference numeral 1 ₁ is a RAM for storing cells, reference numeral 1 ₂ is a cell writing controller, reference numeral 1 ₃
Is a cell read controller, reference numeral 1 ₄ is a read cycle generating circuit, and reference numeral 1 ₈ is a control unit. RAM 1 ₁ write as the cell buffer 20 shows the FIFO operation by the read address. The control unit ₁₈ prevents the read address from overtaking the write address.
In addition, buffer overflow control is performed by the write address catching up with the read address.

The cell spacing control device is the AT shown in FIG.
In the M communication network, it is built in a subscriber exchange, a relay exchange, or the like, and generally a plurality of them are provided to control the cell transmission interval.

[0006]

As described above, the conventional cell spacing control device can achieve only a constant read rate or cell spacing without depending on the amount of cells in the cell buffer. Therefore, when the cell transmission interval T is set to be large, it is necessary to increase the capacity of the cell buffer in order to prevent the cells from overflowing from the cell buffer. Further, if the capacity of the cell buffer is suppressed, Since the transmission interval T has to be made small, in fact, even if the cell transmission interval T is made large, the cell transmission interval T that is still small must be given to a short burst that does not overflow the cell buffer. However, the usefulness of cell spacing control is reduced.

The present invention has been made against such a background, and an object thereof is to provide a cell interval control device capable of varying a cell transmission interval in accordance with a traffic volume. It is an object of the present invention to provide a cell interval control device capable of autonomously varying the cell transmission interval according to the load condition of an input cell. An object of the present invention is to provide a cell spacing control device that can downsize a cell buffer.

[0008]

The generation of the read address of the output interval control circuit is controlled in accordance with the amount of load calculated from the number of cells arriving at the cell buffer per unit time. For example, if the read address of the output interval control circuit is generated in a cycle that is inversely proportional to the amount of load, the read interval becomes shorter in a traffic situation in which a large number of cells arrive per unit time, and the number of cells accumulated in the cell buffer is kept small. be able to. Further, in a traffic situation in which cells arrive at a small number per unit time, the read interval becomes long, and more effective cell interval control can be performed.

As a result, it is possible to perform control such that the same effect can be obtained even if the capacity of the cell buffer is reduced, as compared with the method of reading cells at a constant speed all the time.

The applicant of the present invention filed Japanese Patent Application No. 7-09
Although a cell interval control device was proposed in No. 7055, in the prior application, a threshold value was set in the range of the queue length of the cell buffer, and cell transmission interval control was performed according to the cell accumulation amount of the cell buffer. The present invention is to improve the point that the prior application could not be taken according to the same scale of the input cell amount and the output cell amount, in the present invention, set an arbitrary unit time,
The amount of load is observed by counting the number of cells that arrive at the cell buffer within the unit time. As a result, the scale of the input cell amount (cell number / unit time) and the scale of the output cell amount (cell number / unit time) can be aligned. Therefore, it is necessary to judge whether the arrived bursts are long continuous bursts for which the cell transmission interval T needs to be shortened or short continuous bursts for which the cell transmission interval T does not need to be shortened. Compared to the previous application, it can be done more accurately.

That is, the present invention is a cell interval control device provided with a cell buffer for accumulating incoming cells and an output interval control circuit for controlling cell reading of the cell buffer.

Here, the feature of the present invention resides in that a means for controlling the read address generation cycle of the output interval control circuit is provided according to the number of cells arriving in the cell buffer per unit time.

A plurality of thresholds are provided for the number of cell arrivals per unit time of the cell buffer, and the controlling means is
The cycle may be changed stepwise every time this threshold is exceeded.

Alternatively, the controlling means may be configured to change the cycle steplessly according to the number of cells arriving in the cell buffer per unit time.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an overall configuration diagram of an embodiment of the present invention. FIG. 2 is a block diagram of the apparatus of the present invention.

[0016] The present invention includes a cell buffer CB for storing the incoming cells, a cell interval control device 1 and an output interval control circuit 1 ₅ for controlling the cell reading of the cell buffer CB.

Here, the feature of the present invention is that the cell counter 1 ₆ as means for controlling the generation cycle of the read address of the output interval control circuit 1 ₅ according to the number of cells arriving in the cell buffer CB per unit time. , A load calculation circuit 1 ₇ and a timer 1 ₉ .

[0018]

【Example】

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram of the load calculation circuit ₁₇ . FIG. 4 is a diagram showing the status of signals input to and output from the time counter 17 ₂ . FIG. 5 is a diagram showing a table setting example of the comparison circuit 17 ₁₂ . FIG. 6 is a flowchart showing the operation of the comparison circuit 17 ₁₂ . FIG. 7 shows the comparison circuit 17 ₁₂
FIG. 6 is a diagram showing a relationship between a cell counter value Co that is an input of the cell counter and a cell transmission interval T that is an output of the cell counter. Horizontal axis takes the value Co of the cell counter 1 _6, taking cell transmission interval T on the vertical axis.
FIG. 8 is a diagram showing the relationship between the waveform of the input cell and the obtained average load. Figure 9 is a diagram for explaining an output interval control circuit 1 _5.

Reference numeral 1 in FIG. 1 is a cell interval control device, and reference numeral 2
Indicates a cell input line, and reference numeral 3 indicates a cell output line. Reference numeral 1 ₁ RAM as the cell buffer of FIG. 2, reference numeral 1 ₂ cell writing controller, reference numeral 1 ₃ cell read controller, reference numeral 1 ₅ output interval control circuit, reference numeral 1 ₆ cell counter,
Reference numeral ₁₇ is a load calculation circuit, reference numeral ₁₈ is a control unit,
Reference numeral ₁₉ indicates a timer. In FIG. 3, reference numeral 17 ₂ is a time counter, reference numeral 17 ₁₂ is a comparison circuit, reference numerals 17 _{4 to} 17 ₆ and 1 are provided.
Reference numerals 7 _{8 to} 17 ₁₀ denote signal lines. In FIG. 9, reference numeral 18 ₁ is an integrating counter, reference numeral 18 ₂ is a comparing circuit, reference numerals 18 ₄ , 1
Reference _numerals 8 ₆ and 18 ₁₀ denote signal lines.

The cell interval control device 1 controls the output cell transmission interval T according to the load condition of the input cell. That is, if the observed load is low, the read rate is slowed accordingly. That is, the cell interval is widened. As described above, the wider the cell interval, the lower the burst property, and it is possible to effectively use resources and transfer information.

In FIG. 1, the cell transmission interval T ₁ is set for the observed load ρ ₁ , and the cell transmission interval T is set for the load ρ ₂ .
_2, showing the state of outputting the cell transmission interval T ₃ to the load _{ρ 3 (ρ 1> ρ 2} > ρ 3 → T 3 <T 2 <T 1).

As shown in the configuration diagram of FIG. 2, the cell counter 1 ₆ counts the number of arriving cells, and based on the value Co of the cell counter 1 ₆ , the load calculation circuit 1 ₇ calculates the average load ρ and the average load ρ. The output cell transmission interval T is obtained from Output interval control circuit 1 ₅ controls the output interval of the cells according to the cell transmission interval T supplied from the load calculation circuit 1 _7.
The control unit ₁₈ has a RAM as a cell buffer.
In 1 _1, as already described with reference to FIG. 20, as the read address does not overtake the write address, also performed a buffer overflow control by the write address catches up with the read address.

FIG. 3 shows a configuration example of the load calculation circuit ₁₇ .
By the time counter 17 ₂ in FIG. 3 for counting the clock signal from the timer 1 _9, advance signal line 1
Cell counter 1 _{6 at} every time Tp set via 7 ₁₃
A read instruction is issued via the signal line 17 ₄ . The cell counter 1 ₆ sends the counted value Co to the comparison circuit 17 ₁₂ via the signal line 17
Notify via ₆ . The time counter 17 ₂ is the comparison circuit 1
An operation instruction is given to 7 ₁₂ via a signal line 17 ₉ and a reset instruction is given to a cell counter ₁₆ via a signal line 17 ₅ . Upon receiving the instruction, the comparison circuit 17 ₁₂ obtains the cell transmission interval T by using the value Co notified from the cell counter ₁₆ and the table in which the value is set in advance through the signal line 17 ₁₄ in the comparison circuit 17 ₁₂ . The output interval control circuit 1 ₅ is notified via the signal line 17 ₈ . Here, a value obtained by dividing the value Co of the cell counter 1 ₆ by the time Tp is the observed average load ρ, and the cell output interval is determined based on the value Co of the cell counter 1 ₆ by determining the cell load interval based on the average load ρ. Equivalent to determining the sending interval. FIG. 4 shows the signals transmitted on the signal lines 17 ₁₀ and 17 ₄ . The time Tp can be arbitrarily set by the time counter 17 ₂ . In the embodiment of the present invention, the value of the time Tp is determined by judging the traffic characteristics of the ATM communication network. When the time Tp is shortened, the response characteristic of the cell interval control device 1 becomes agile. However, in some cases, it is not always preferable from the viewpoint of cell spacing control because it responds promptly even to continuous bursts that are short enough to make the cell transmission interval short. Further, if the time Tp is lengthened, it does not respond to a continuous burst that is short enough not to shorten the cell transmission interval, which is effective from the viewpoint of cell interval control.
However, from the viewpoint of the response characteristic of the cell interval control device 1, the response characteristic becomes dull.

[0024] 5 through operation flow a table configuration example of the comparator circuit 17 ₁₂ in FIG. 7 and the comparison of the time circuit 17 ₁₂
The relationship between the value Co of the cell counter _{16 as} an input and the cell transmission interval T as an output is shown. In this example, time Tp = 10
(Cell time). As shown in FIG. 5, the time Tp is 1
When set to 0 cell time, the comparison value "5" indicates that one cell has arrived in two cell time, and the cell transmission interval T in this case has the minimum value "1". Comparison value "0" is 1
The situation shows that no cell has arrived at 0 cell time, and the cell transmission interval T in this case has a maximum value of "10", but in this case there is no actual cell transmission, and the comparison value "1", that is, The value "5" of the cell transmission interval T in the situation where one cell has arrived in 10 cell times becomes a substantially maximum value.

In this way, the comparison value "0" shown in FIG.
The cell transmission interval T is determined using "1", "2", "3", and "5" as threshold values.

As shown in FIG. 6, the set time Tp
The value Co of the cell counter ₁₆ is input every (10 cell time) (S0), and if the value Co is larger than "5" (S0).
1), the cell transmission interval T = 1 is set (S5). Value Co
Is less than or equal to "5" and greater than "3" (S2),
The cell transmission interval T = 2 is set (S6). If the value Co is equal to or smaller than "3" and larger than "2" (S3), the cell transmission interval T = 3 is set (S7). Value Co is "2"
If it is less than or equal to "1" (S4), the cell transmission interval T = 5 is set (S8). If the value Co is "1" or less, the cell transmission interval T = 10 is set (S9).

According to the set values and the setting procedure shown in FIGS. 5 and 6, the relationship between the value Co of the cell counter ₁₆ and the cell transmission interval T as shown in FIG. 7 is established.

The arrow in FIG. 8 represents the minimum cell transmission timing, and cells are transferred in accordance with this timing. A solid arrow indicates that a cell is input.
In this example, the relationship between the change in the value Tc of the time counter 17 ₂ and the value Co of the cell counter ₁₆ and the obtained average load ρ and cell output interval T when Tp = 10 (cell time) is shown. As shown in FIG. 7, it can be seen that the value of the cell transmission interval T is updated every time Tp.

[0029] Figure 9 shows a configuration example of an output interval control circuit 1 _5. Integrating counter 18 ₁ in FIG. 9 counts via the signal line 17 ₁₀ a clock signal from the timer 1 _9. Comparison circuit 18 ₂ in accordance with the timer 1 ₉ for each cell cycle, reads the cell transmission interval T, which is notified via the signal line 17 _8, and an integrating counter 18 value of ₁ Ta via the signal line 18 ₄ Make a comparison. At this time, if Ta ≧ T, the comparison circuit 18 ₂ resets the integration counter 18 ₁ (Ta = 0).
Is instructed via the signal line 18 ₁₀ , and further, the signal line 1
A cell output instruction is given via 8 ₆ . As a result, one cell is output for each T cell. In this way, the read cycle of the cell read controller 1 ₃ is controlled in order to control the cell transmission interval T from the RAM _{1 1 serving} as a cell buffer according to the observed load condition.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a block diagram of the load calculating circuit _{17 according to} the second embodiment of the present invention. FIG. 11 is a diagram showing the relationship between the value of the average load ρ and the cell transmission interval T in the second embodiment of the present invention, where the horizontal axis represents the average load ρ.
And the cell transmission interval T on the vertical axis. Figure 12 is a block diagram of an output interval control circuit 1 ₅ of the second embodiment of the present invention. FIG. 13 shows the cell transmission interval T of the second embodiment of the present invention.
FIG. 6 is a diagram for explaining the setting situation of FIG. FIG. 14 is a flow chart for explaining the procedure for setting the cell transmission interval T according to the second embodiment of the present invention. The cell spacing control device 1 of the second embodiment of the present invention is similar to the load calculation circuit 1 _{7 of} the first embodiment of the present invention.
There cell transmission intervals T to be notified to the output interval control circuit 1 ₅ is to take discrete values, in the present invention the second embodiment takes a continuous value. Further, the cell transmission interval T to be used in the output interval control circuit 1 ₅ the present invention the first embodiment is carried out in a continuous value while taking discrete values. Therefore, the load calculation circuit 1 ₇
And configuration of the output interval control circuit 1 ₅ is different.

Reference numeral 17 _{3 in} FIG. 10 is a division circuit, reference numeral 17
₁₁ is a cell interval calculation circuit, reference numerals 17 _{4 to} 17 ₁₀ , 17 ₁₃
17 ₁₅ indicates a signal line. 12, reference numeral 18 ₁ is an integrating counter, reference numeral 18 ₂ is a comparing circuit, reference numeral 18 ₃ is a subtracting circuit,
Reference numerals 18 ₄ to 18 ₉ indicate signal lines.

FIG. 10 shows a configuration example of the load calculation circuit ₁₇ . By the time counter 17 ₂ in FIG. 10 for counting the clock signal from the timer 1 _9, the signal line 17 ₄ cell counter 1 ₆ every time a preset Tp
A read instruction is issued via. The cell counter 1 ₆ notifies the counted value Co to the division circuit 17 ₃ via the signal line 17 ₆ . The time counter 17 ₂ supplies the signal line 1 to the division circuit 17 _3.
The operation instruction is given via 7 ₉ and the cell counter 1
_A reset instruction is given to ₆ via a signal line 17 ₅ . The division circuit 17 _{3 that} has received the instruction divides the value Co notified from the cell counter 1 ₆ by the time Tp. This value is the observed average load ρ. Cell interval calculation circuit 17 ₁₁ is notified via the signal line 17 ₈ to output interval control circuit 1 ₅ obtains the cell transmission interval T from average load ρ as shown in FIG. 11. Here, in order to prevent the cell transmission interval T from becoming infinitely large as shown in FIG. 11, it is considered to suppress the maximum cell transmission interval T to a certain value. In FIG. 10, the signal line 1
The maximum value is set in the cell interval calculation circuit 17 ₁₁ via 7 ₁₅ .

[0033] Figure 12 shows a configuration example of an output interval control circuit 1 _5. FIG integration counter 18 ₁ of 12 counts via the signal line 18 ₉ the clock signal from the timer 1 _9. Comparison circuit 18 _2, every cell period following the timer 1 _9, the cell transmission interval T, which is notified through the signal line 17 ₈
And the value Ta of the integration counter 18 ₁ through the signal line 18 _4.
Read and compare. At this time, if Ta ≧ T, the comparison circuit 18 ₂ instructs the subtraction circuit 18 ₃ to perform subtraction on the signal line 1
Give via 8 ₅ . Furthermore, the cell read controller 1
_A cell read instruction is given to ₃ via the signal line 18 ₆ . The subtraction circuit 18 _{3 that} has received the subtraction instruction reads the value of the integration counter 18 ₁ via the signal line 18 ₇ , subtracts the cell transmission interval T from the value, and outputs the value of the integration counter 18 ₁ to the signal line 18 ₈ . To update through.

The concept of cell output will be described with reference to FIG. Here, the case where the average load ρ = 0.4 is taken as an example.
In the graph of FIG. 13A, the horizontal axis represents time, and the vertical axis represents the value Tc of the integrating counter 18 ₁ . Integrating counter 18
The value of ₁ increases in proportion to the passage of time, and the time when the cell transmission interval T is exceeded becomes the cell output timing. At this time, the value Tc of the integration counter 18 ₁ is subtracted by the cell transmission interval T. Further, FIG. 13B shows a state of the output cell when the output control is performed with the arrival cell. In FIG. 13A, when the average load ρ = 0.4 (T = 1 / ρ = 2.5), the cell is transmitted when the value Tc of the integration counter 18 ₁ exceeds “2.5”. is doing. By setting the value of this average load ρ as a threshold value in a stepless manner, the cell transmission interval T can be determined.

FIG. 14 shows a flow chart of load observation and cell transmission timing determination. The value Tc of the integration counter 18 ₁ is compared with the time Tp. If Tc> Tp (S11), then ρ = Co / Tp T = 1 / ρ Co = 0 Tc = 0 (S12). Subsequently, if Ta <T (S13), Ta = 1 / ρ (S14), and the cell is transmitted (S16). After that, Ta = Ta−T is set (S17), and Ta = Ta + 1 Co = Co + 1 is set (S19). If Ta ≧ T, then (S13), Ta = Ta + 1 and Co = Co + 1 (S19).

If Tc ≦ Tp (S11) and Ta> 1 / ρ (S15), the cell is transmitted (S16). After that, Ta = Ta−T is set (S17), and Ta = Ta + 1 Co = Co + 1 is set (S19).

If Ta ≦ 1 / ρ (S15), the cell is not transmitted (space transmission) (S18), and Ta = Ta + 1 Co = Co + 1 (S19).

Next, application examples of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 15 is a diagram showing data transfer between exchanges connected in multiple stages. FIG. 16 is a diagram showing an example in which the device of the present invention is installed at the output of the cell copy device.
In the case of FIG. 15, in the exchange of the next stage, the cell intervals are controlled as much as possible in the exchanges of the preceding stages, so that the buffer can be reduced.

In the case of FIG. 16, the cell copy device may generate a plurality of cells at the same time and the burst property may be large. Therefore, it is useful to control the burst property by the device of the present invention.

[0040]

As described above, according to the present invention,
The cell transmission interval can be changed according to the traffic volume. As a result, the cell transmission interval can be changed autonomously according to the load condition of the input cell.

Since the effective cell interval control can be performed without depending on the increase in the capacity of the cell buffer, the device can be downsized.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 3 is a block configuration diagram of a load calculation circuit.

FIG. 4 is a diagram showing a state of signals input to and output from a time counter.

FIG. 5 is a diagram showing a table setting example of a comparison circuit.

FIG. 6 is a flowchart showing the operation of a comparison circuit.

FIG. 7 is a diagram showing a relationship between a cell counter value Co which is an input of a comparison circuit and a cell transmission interval T which is an output.

FIG. 8 is a diagram showing the relationship between the waveform of an input cell and the average load obtained.

FIG. 9 is a diagram illustrating an output interval control circuit.

FIG. 10 is a block configuration diagram of a load calculation circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram showing the relationship between the value of the average load ρ and the cell transmission interval T according to the second embodiment of the present invention.

FIG. 12 is a block configuration diagram of an output interval control circuit according to a second embodiment of the present invention.

FIG. 13 is a diagram for explaining a setting situation of a cell transmission interval T according to the second embodiment of the present invention.

FIG. 14 is a flowchart for explaining a procedure for setting a cell transmission interval T according to the second embodiment of the present invention.

FIG. 15 is a diagram showing data transfer between exchanges connected in multiple stages.

FIG. 16 is a diagram showing an example in which the device of the present invention is installed at the output of the cell copy device.

FIG. 17 is a conceptual diagram of a conventional cell spacing control device.

FIG. 18 is a diagram showing the spacing between input and output cells of a conventional cell spacing control device.

FIG. 19 is a block configuration diagram of a conventional cell spacing control device.

FIG. 20 is a diagram for explaining a conventional cell buffer.

FIG. 21 is a conceptual diagram of an ATM communication network.

[Explanation of symbols]

1 Cell Interval Control Device 1 ₁ RAM 1 ₂ Cell Write Controller 1 ₃ Cell Read Controller 1 ₄ Read Cycle Generation Circuit 1 ₅ Output Interval Control Circuit 1 ₆ Cell Counter 1 ₇ Load Calculation Circuit 1 ₈ Control Section 1 ₉ Timer 2 Cell Input Line 3 Cell output line 17 _{4 to} 17 ₆ , 17 _{8 to} 17 ₁₀ , 17 _{13 to} 17 ₁₅ , 1
8 ₄ to 18 ₁₀ Signal line 17 ₂ Time counter 17 ₃ Division circuit 17 ₁₁ Cell interval calculation circuit 17 ₁₂ , 18 ₂ Comparison circuit 18 ₁ Integration counter 18 ₃ Subtraction circuit

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Naoaki Yamanaka 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Takafumi Kobayashi 1015 Kamedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited In-company (72) Inventor Tsuguo Kato 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) Reference JP-A-4-336831 (JP, A) JP-A-2-170645 (JP, A) ) JP-A-6-252938 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/00 H04L 13/00

Claims (3)

(57) [Claims] 1. A cell buffer for accumulating incoming cells,
In a cell interval control device including an output interval control circuit for controlling cell reading of the cell buffer, a read address of the output interval control circuit is generated according to the number of cells actually arriving per unit time of the cell buffer. A cell interval control device comprising means for controlling a cycle. 2. Actually per unit time of the cell buffer
A plurality of threshold values are provided to the cell number arriving arriving to the output
Means for controlling the generation period of the read address of power interval control circuit, the cell spacing control apparatus as claimed in claim 1, wherein the generating circumference <br/> period of said read address changing stepwise each time exceeds the threshold value. 3. A read address is issued by the output interval control circuit.
The cell interval according to claim 1, wherein the means for controlling the raw cycle changes the generation cycle of the read address steplessly according to the number of cell arrivals that actually arrive per unit time of the cell buffer. Control device.