JP3400166B2 - Digital data processing apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data processing device and method, and for example, a digital data processing device and a digital data processing device suitable for use in a device for receiving a television broadcast based on electronic program guide information transmitted via a satellite. Regarding the method.

[0002]

2. Description of the Related Art In recent years, in the United States, MPEG (Movie)
ng Picture Experts Group)
Cable television (CATV: Cable Television) by applying high-efficiency coding technology such as
And digital direct satellite broadcasting (DSS: Digital)
Satellite System (Hughes C)
systems) in which video signals and audio signals are digitized, digital data is transmitted via a satellite, and the receiving side receives and demodulates the digital signals.

In these systems, a dedicated digital data processing device (decoder) is required on the receiving side. In these digital data processing devices, it is necessary to generate a clock from transmitted digital data and process video data and audio data based on the clock.

Conventionally, to generate such a clock,
A PLL (Phase Locked Loop) circuit is used. That is, in the transmission data, SCR (Sys) is used as the reference data for generating the clock.
tem Clock Reference), and a clock is generated based on this SCR.

[0005]

However, the PLL circuit in the conventional digital data processing device is within an allowable range when the phases of the clocks generated on the receiving side and the SCR deviate from each other to some extent for some reason. There was a problem that it takes time to return to the phase error clock.

Further, it is difficult to generate a clock having a small phase error, and there is a possibility that a buffer for temporarily storing data may overflow or underflow in order to process digital data.

The present invention has been made in view of such a situation, and it is an object of the present invention to quickly generate a clock having a phase within the allowable error range. Moreover, it is possible to generate a clock having a more accurate phase.

[0008]

A digital data processing apparatus according to claim 1, wherein a phase error as a difference between a time reference value and a count value, and the time reference value and the count value at a predetermined reference timing. The difference phase error as a difference from the reference phase error as a difference between the reference phase and the allowable difference phase error comparing means for comparing the difference phase error with the predetermined allowable difference phase error, and the reference phase And a reset means for resetting the error and setting the phase error at that time.

According to another aspect of the digital data processing device of the present invention, the comparing means determines a phase error as a difference between the time reference value and the count value and a difference between the time reference value and the count value at a predetermined reference timing. The sum of the difference phase error as the difference from the reference phase error, the phase error at that time, and the phase error immediately before that time is multiplied by a predetermined coefficient, and the phase error at that time and the phase immediately before that time It is characterized in that a control value divided by an interval as a difference from the error is calculated, and the control value is added to the control signal at that time to obtain a new control signal.

According to a seventh aspect of the present invention, in the digital data processing method, the phase error as the difference between the time reference value and the count value and the reference phase error as the difference between the time reference value and the count value at a predetermined reference timing. The difference phase error as a difference between and is compared with a predetermined allowable difference phase error, and when the difference phase error is larger than the allowable difference phase error, the reference phase error is reset and set to the phase error at that time. And

In the digital data processing method according to the present invention, a phase error as a difference between the time reference value and the count value and a reference phase error as a difference between the time reference value and the count value at a predetermined reference timing are provided. The difference between the phase error at that time, the phase error at that time, and the sum of the phase error immediately before that time are multiplied by a predetermined coefficient, and the difference between the phase error at that time and the phase error immediately before that time. The control value divided by the interval is calculated, and the control value is added to the control signal at that time to obtain a new control signal.

[0012]

In the digital data processing device and the digital data processing method according to claim 7, the reference phase error is reset in accordance with the result of comparison with the allowable differential phase error. Set to phase error.

Further, in the digital data processing device and the digital data processing method according to claim 8, the sum of the differential phase error, the phase error at that time, and the phase error immediately before that time is calculated. , A predetermined coefficient is multiplied, and a control value obtained by dividing the sum by an interval is calculated. Then, the control value is added to the control signal at that time to obtain a new control signal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an AV (Audio) to which the present invention is applied.
3 shows an example of the configuration of a Video) system. In the case of this embodiment, the AV system is an IRD (Integrated Re) that demodulates a signal received by the parabolic antenna 3 via a satellite (broadcast satellite or communication satellite) not shown.
It is composed of a receiver / decoder 2 and a monitor device 4. The monitor device 4 and the IRD 2 are AV
The line 11 and the control line 12 are connected to each other.

For the IRD 2, the remote commander 5
It is possible to input an instruction by an infrared (IR: Infrared) signal. That is,
When a predetermined button switch 50 (FIG. 5) of the remote commander 5 is operated, an infrared signal corresponding to
The IR receiver 39 of the IRD 2 is emitted from the R transmitter 51.
(FIG. 4).

FIG. 2 shows an electrical connection state of the AV system 1 of FIG. The parabolic antenna 3 is an LNB
(Low Noise Block downconv
erter) 3a, converts the signal from the satellite into a signal of a predetermined frequency and supplies it to the IRD 2. IRD2
Outputs its output to, for example, a composite video signal line,
The signal is supplied to the monitor device 4 via an AV line 11 composed of three lines, an audio L signal line and an audio R signal line.

Further, the IRD 2 has an AV device control signal transmission / reception unit 2A, and the monitor device 4 has an AV device control signal transmission / reception unit 4A. These are wired S
IRCS (Wired Sony Infrared)
They are mutually connected by a control line 12 made of a Remote Control System (trademark).

FIG. 3 shows an example of the front structure of the IRD 2. On the left side of IRD2 is the power button switch 111
Is provided. This power button switch 111 is
Operated when turning the power on or off. The LED 112 lights up when the power is turned on. LEDs 113 and 114 are provided on the right side of the LED 112, and the LED 113 lights up when the DSS mode in which a signal from a satellite is received and output is selected, and, for example, an RF signal input from a cable box to an RF input terminal, It is turned off when the television (TV) mode in which the output from the RF output terminal is performed via the RF modulator 41 (FIG. 4) is selected. The LED 114 is adapted to turn on when a predetermined message is transmitted to the IRD 2 via the satellite. When the user outputs and displays this message on the monitor device 4 and confirms it, the LED 114 is turned off.

When the TV / DSS button switch 115 is turned on, the DSS mode is set, and when it is turned off, the TV mode is set. Also, the menu button switch 121
Is operated when the menu is displayed on the monitor device 4.

An up button switch 117, a down button switch 118, a left button switch 119 and a right button switch 120 are arranged on the upper, lower, left and right sides of the select button switch 116, respectively. The up button switch 117, the down button switch 118, the left button switch 119, and the right button switch 120 are operated when moving the cursor in the vertical and horizontal directions. Also, select button switch 1
16 is operated when confirming the selection (when selecting).

FIG. 4 shows an example of the internal structure of the IRD 2 for receiving the above-mentioned DSS. The RF signal output from the LNB 3a of the parabolic antenna 3 is supplied to the tuner 21 of the front end 20 and demodulated. The output of the tuner 21 is supplied to the QPSK demodulation circuit 22 and QPSK demodulated. The output of the QPSK demodulation circuit 22 is supplied to the error correction circuit 23, which detects and corrects the error, and corrects it if necessary.

I consisting of CPU, ROM, RAM, etc.
CAM (Conditi) composed of C card
The key required for deciphering the cipher is stored in the onal access module 33 together with the deciphering program. Since the signal transmitted via the satellite is encrypted, a key and a decryption process are required to decrypt this code. Therefore, this key is read from the CAM 33 via the card reader interface 32,
It is supplied to the demultiplexer 24. The demultiplexer 24 uses this key to decrypt the encrypted signal.

The CAM 33 also stores billing information and the like in addition to the key and decryption program required for decryption.

The demultiplexer 24 receives a signal output from the error correction circuit 23 of the front end 20 and outputs it to a data buffer memory (SRAM: Stat).
icRandom Access Memory) 35
Make it remember once. Then, this is read out as appropriate, the decoded video signal is supplied to the MPEG video decoder 25, and the decoded audio signal is supplied to the MPEG audio decoder 26.

The MPEG video decoder 25 appropriately stores the input digital video signal in the DRAM 25a and executes the decoding process of the digital video signal compressed by the MPEG system. The decoded digital video signal is supplied to the NTSC encoder 27,
It is converted into an NTSC luminance signal (Y), a chroma signal (C), and a composite signal (V). The luminance signal and the chroma signal are output as S video signals via the buffer amplifiers 28Y and 28C, respectively. Further, the composite signal is output via the buffer amplifier 28V.

As the MPEG video decoder 25, SGS-Thomson Microselect is used.
tronics MPEG2 decoding LSI (STi35
00) can be used. The outline is, for example, “Nikkei Electronics” 1994.
(No. 603) pp. 101-110, Mart.
Introduced by Mr. in Bolton.

In addition, MPEG2-Transports
As for stream, ASCII Corporation August 1994
"Latest MPEG Textbooks," issued March 1, pages 231 to 2
An explanation is given on page 53.

The MPEG audio decoder 26 appropriately stores the digital audio signal supplied from the demultiplexer 24 in the DRAM 26a, and executes the decoding process of the audio signal compressed by the MPEG system. The decoded audio signal is D / A converted in the D / A converter 30, the left channel audio signal is output through the buffer amplifier 31L, and the right channel audio signal is output in the buffer amplifier 31R.
Is output via.

The RF modulator 41 converts the composite signal output by the NTSC encoder 27 and the audio signal output by the D / A converter 30 into an RF signal and outputs the RF signal. Further, the RF modulator 41 allows an NTSC-type RF signal input from an AV device such as a cable box to pass through when the TV mode is set,
It is directly output to the VCR and other AV equipment (not shown).

In the case of this embodiment, these video signal and audio signal are supplied to the monitor device 4 via the AV line 11.

CPU (Central Process)
or Unit) 29 executes various processes according to programs stored in the ROM 37. For example, the tuner 21, the QPSK demodulation circuit 22, the error correction circuit 2
Control 3 and so on. Also, the AV device control signal transmitting / receiving unit 2
A is controlled, and another A is controlled through the control line 12.
It outputs a predetermined control signal to the V device (in this embodiment, the monitor device 4) and receives a control signal from another AV device.

A predetermined command can be directly input to the CPU 29 by operating the operation button switch (FIG. 3) on the front panel 40. Further, when the remote commander 5 is operated, an infrared signal is emitted from the IR transmitter 51, the infrared signal is received by the IR receiver 39, and the light reception result is supplied to the CPU 29. Therefore,
The CPU can also be operated by operating the remote commander 5.
A predetermined command can be input to 29.

In addition to the MPEG video data and audio data supplied from the front end 20, the demultiplexer 24 also includes an EPG (Electrical).
Import Program Guide data etc.,
The data is supplied to and stored in the EPG area 35A of the data buffer memory 35. The EPG information is information on programs of each broadcast channel from the current time to several tens of hours later (for example,
Program channel, broadcast time, title, category, etc.)
Is included. Since this EPG information is transmitted frequently, the latest EPG can always be held in the EPG area 35A.

EEPROM (Electrically)
Erasable Programmable Rea
In the d Only Memory) 38, the data (for example, the reception history of the tuner 21 for four weeks, the channel number (last channel) received immediately before the power-off) which is desired to be retained after the power-off is appropriately stored in the d Only Memory 38. To be done.
Then, for example, when the power is turned on, the same channel as the last channel is received again. ROM 37 when the last channel is not stored
The channel stored as the default is received. Further, when the sleep mode is set, the CPU 29 determines that the front end 2 is active even when the power is off.
0, demultiplexer 24, data buffer memory 35
For example, the minimum circuit is put into an operating state, the current time is measured from the time information included in the received signal, and control such as causing each circuit to perform a predetermined operation (so-called timer recording) at a predetermined time is also executed. For example, an external VCR (Video)
The timer automatic recording is executed in conjunction with the Cassette Record).

Further, the CPU 29 has a predetermined OSD (O
When it is desired to generate n-Screen Display data, the MPEG video decoder 25 is controlled. MP
The EG video decoder 25 generates predetermined OSD data in response to this control, writes it in the OSD area 25aA (FIG. 10) of the DRAM 25a, and further reads it out,
Output. As a result, predetermined characters, figures, etc. (eg, menus, general program guides as a type of EPG), etc. can be output to the monitor device 4 and displayed appropriately.

Although not shown in FIG. 4,
The IRD 2 receives the received SCR (System Cloc).
k Reference) and a circuit (FIG. 12) for generating a clock that is synchronized with the MPEG video decoder 2 is generated under the control of the CPU 29.
5, MPEG audio decoder 26, NTSC encoder 27, etc.

FIG. 5 shows a configuration example of the button switch 50 of the remote commander 5. Directional button switch 2
01 to 204 are operated when moving (direction operation) the cursor in four directions of up, down, left and right. The button switch 200 can be pressed (selected) in the vertical direction with respect to the upper surface of the remote commander 5. The menu button switch 134 is operated when the menu screen is displayed on the monitor device 4. The exit button switch 135 is operated when returning to the original normal screen.

Channel up / down button switch 1
33 is operated to increase or decrease the number of the broadcast channel to be received. The volume button switch 132 is operated when moving the volume up or down.

The numeric button (numeric keypad) switch 138 displaying the numbers 0 to 9 is operated when inputting the displayed numbers. Enter button switch 13
When the operation of the numeral button switch 138 is completed, numeral 7 indicates the end of numeral input, and is operated subsequently.
When the channel is switched, a new channel number, a call sign (name), a logo, and a banner consisting of a mail icon are displayed for 3 seconds. There are two types of burners, one having a simple structure including the one described above and one having a more detailed structure including the name of the program (program), the broadcast start time, the current time, etc. in addition to these. Yes, display button 136
Is operated when switching the displayed burner type.

TV / video switch button switch 139
Is operated when switching the input of the monitor device 4 to the input (VCR or the like) from a tuner or a video input terminal built in the television receiver. TV set/
The DSS switch button switch 140 is operated when selecting the television mode or the DSS mode. When you operate the number button switch 138 to switch channels,
The channel before switching is stored, and the jump button switch 141 is operated when returning to the original channel before switching.

The guide button switch 143 is operated to directly display the general guide (EPG) on the monitor device 4 without using the menu.

Cable button switch 145, television button switch 146 and DSS button switch 147
Is a button switch for function switching, that is, for switching the device category of the code of the infrared signal emitted from the remote commander 5. The cable button switch 145 is operated when a signal transmitted via the cable is received by a cable box (not shown) and is displayed on the monitor device 4, whereby the signal is transmitted.
The device category code assigned to the cable box is emitted as an infrared signal. Similarly, the television button switch 146 is operated when displaying a signal received by the tuner built in the monitor device 4. The DSS button switch 147 is operated when the signal received via the satellite is received by the IRD 2 and is displayed on the monitor device 4.

LEDs on the back of these button switches
Are arranged, and the cable button switches 145,
Lights when the TV button switch 146 or the DSS button switch 147 is turned on. This indicates to which category the device the code was transmitted when the various buttons were pressed.

When the cable power button switch 151, the television power button switch 152, and the DSS power button switch 153 are respectively operated, the power of the cable box, the monitor device 4, or the IRD 2 is turned on or off.

FIG. 6 shows an example of the internal structure of the remote commander 5. A CPU 72, which constitutes a microcomputer (hereinafter referred to as a microcomputer) 71, constantly scans a button switch matrix 82 to detect an operation of a button switch 50 of the remote commander 5 shown in FIG. The CPU 72 executes various kinds of processing according to the programs stored in the ROM 73 and causes the RAM 74 to store necessary data as needed.

When outputting the infrared signal, the CPU 72 drives the LED 76 via the LED driver 75 to output the infrared signal.

Direct Broadcast Sa
For more information on tellite System, see Nikkei BP “Nikkei Electronics” “Technology that Supports US Information Super Highway”, Issue 24, October 24, 1994.
Pages 189 to 189, L. W. Butterworth
h, J. P. Godwin, D.M. Introduced by Mr. Radbel.

FIG. 7 shows this Direct Broadcast.
7 shows a transmission data generation procedure performed by an encoder of the ast Satellite System.
On EPG day, guide data, channel data, and program (Pr)
data). The guide data is data regarding the entire program guide, the channel data is data regarding the channel, and the program data is data regarding the program (program). The details will be described later with reference to FIG.

Of these data, the channel data and the program data are divided for each channel, and the data of a predetermined number of channels are collected as a segment. In the embodiment of FIG. 7, the channel data and program data of channel 1 and channel 2 are
The data is segment 1 data, the channel data and program data of channel 3 and channel 4 are segment data, and the channel data and program data of channel 5 and channel 6 are segment 3 data, respectively. There is.

Then, these channel data and program data are divided into packets of a predetermined size,
A header is added to each packet, and data is transmitted in packet units.

In the encoder on the transmitting side, as shown in FIG. 8, not only such channel data and program data but also guide data, video data and audio data are packetized and mounted on the satellite.
It is transmitted to the 2.2GH _Z ~12.7GH _Z BSS high output transponder for the band. In this case, packets of a plurality of channels (up to 9) are multiplexed and transmitted with a signal of a predetermined frequency assigned to each transponder. That is, each transponder transmits signals of a plurality of channels on one carrier. Therefore, for example, if there are 23 transponders, the maximum is 2
Data of 07 (= 9 × 23) channels can be transmitted.

In the IRD2, the front end 20
At, a carrier wave of one frequency corresponding to one predetermined transponder is received and demodulated. With this, up to 9
Packet data for each channel is obtained. And
The demultiplexer 24 temporarily stores each packet obtained from this demodulated output in the data buffer memory 35 and reads it. Regarding the packet of EPG data (guide data, channel data, and program data), the data portion excluding the header is stored in the EPG area 35A. The video packet is supplied to the DRAM 25a,
It is stored and decoded by the MPEG video decoder 25. The audio packet is supplied to and stored in the DRAM 26a, and is decoded by the MPEG audio decoder 26.

Details of the processing in the encoder of FIG.
As described on pages 180 to 189 of the above-mentioned Nikkei Electronics "Technology for Supporting US Information Super Highway", scheduling is performed so that the transfer rates are the same in each transponder. The transmission rate per carrier assigned to each transponder is 40 Mbits / sec.

In the case of an image with a lot of motion such as a sports program, the MPEG video data occupies many packets. Therefore, when the number of such programs increases, the number of programs that can be transmitted by one transponder decreases.

On the other hand, MPEG video data of an image with little movement such as an announcement scene of a news program can be transmitted with a small number of packets.
Therefore, when there are many such programs, the number of programs that can be transmitted by one transponder becomes large.

FIG. 9 shows a state of use inside the DRAM 25a. Now, for example, the screen of the monitor device 4 is changed to 7
It is composed of 20 x 480 pixels and the brightness is 8 for each pixel.
It is expressed in bits, and the color difference is 8 for every 2 pixels.
In terms of bits, the number of bits required to form one screen is 4147200 (= 720 × 480 × 1.
5 × 8) bits. If one word is made up of 64 bits, this value is 64800 words, which is 0xFD20 words when expressed in hexadecimal.

Since this value is too large as a value that can be set in the register in the MPEG video decoder 25 that manages the DRAM 25a, if this value is shifted to the LSB side by 5 bits, the 0xFD20 becomes 0x7.
It becomes EQ. Since the value set in this register must be a multiple of 4, if the value of 0x7EQ is set to a value larger than that value and closest to a multiple of 4, then 0x7E
It becomes C.

Therefore, in this embodiment, buffer memories 0 to 2 are provided for storing image data of I picture, P picture and B picture, respectively, and the capacity of each is 64,896 words. . As the storage area for OSD data, 1
An area of 8176 words is secured and 4 bits are set as a bit buffer memory area for temporarily storing the input data.
An area of 9280 words is reserved.

FIG. 10 shows E of the data buffer memory 35.
The storage state of the EPG data (program guide data) stored in the PG area 35A is schematically shown. C
As described with reference to FIGS. 7 and 8, the PU 29 transmits the EPG data encoded in the encoder on the transmission side and transmitted in packet units to the EPG area 35.
It is stored in A as shown in FIG.

As shown in the figure, program guide data (Data of Program Guide)
(EPG data) is sequentially stored in the order of guide data, channel data, and program data.

In this guide data, Date representing the current date, Time representing the current time, Number of Segment representing the total number of segments, the number of each segment and the corresponding transponder number are stored as a list. Transponder
list, which is a list of the number of each segment and the number at the beginning of the channel of the segment Cha
nnel List is included.

Next to such guide data, channel data are arranged in the order of segment 1, segment 2, segment 3 ... Each segment has
Data of a predetermined number of channels is arranged. In this embodiment, segment 1 has channel 1 and channel 2 data, and segment 2 has channel 3 and channel 4 data.

The data of each channel includes Channel Number indicating the channel number, Channel Name indicating the call sign (name) of the broadcasting station,
Logo to identify the broadcaster Logo (logo)
ID, Data IDs for identifying MPEG video data and MPEG audio data, Number of Programs indicating the number of programs (programs) of the channel (for example, channel 1), and a location (address where the first program data of a predetermined channel is stored). ) (For example, in the case of channel 2, a First value representing the offset value from the beginning of the program segment (in FIG. 10, the beginning of Program 1-1) up to the address where the first program data Program2-1 is stored) Program's Off
set is included.

The program data includes a Program Title indicating a program name and S indicating a broadcast start time.
start Time, Ti representing the broadcast time of the program
meLength, program genre (category)
, A Subcategory that represents a finer classification of the genre (category), a Rating that represents the age limit of the program, and a Program Descr that stores detailed content of the program.
option (for example, pay per view
The condition for decrypting the r View encrypted program data is also included here).

Such program data is also arranged for each segment. In this embodiment, the program data of segment 1 is Program
Eight channels 1 from 1-1 to Program1-8
Data, and Program2-1 to Program
2-7 data of 7 channels 2.

FIG. 11 schematically shows the processing of data until the screen of the general guide is displayed on the monitor device 4.

The CPU 29 presets the transfer destination of the data input from the front end 20 in the register 24a incorporated in the demultiplexer 24. The data supplied from the front end 20 is temporarily stored in the data buffer memory 35, read by the demultiplexer 24, and transferred to the transfer destination set in the register 24a.

For example, of the data stored in the data buffer memory 35, DATA ID of'MP stored in the register 24a of the demultiplexer 24 is used.
Only the data portion of the packet that has a header that matches EGVideo 'is transferred to MPEG video decoder 25. In addition, the DAT stored in the register 24a
The data portion of the packet having a header that matches A ID of'MPEG Audio 'is transferred to the MPEG audio decoder 26.

Similarly, the data portion of the packet having a header that matches the DATA ID of'Guide 'stored in the register 24a is the Address of'Guide' stored in the register 24a.
Is transferred to and written in the EPG area 35a of the data buffer memory 35 designated by. EP in this way
EPG data is stored in the G area 35A as shown in FIG.

The header becomes unnecessary when this transfer is completed, and is discarded.

In this way, for example, 120 Kbytes
Of EP in the EPG area 35A having a capacity of
When the G data is stored, the demultiplexer 24 sends CP
It outputs a full-up status signal to U29. When the CPU 29 receives this control signal, the E
The acquisition of the PG data is stopped, and thereafter, at the time of displaying the EPG, decoding processing such as decompression, sorting, and decoding processing of the compressed EPG data is executed.

In this way, for example, EPG data for 200 channels from the current time to 4.5 hours after is E
The EPG data (guide data, channel data, and program data), which is taken into the PG area 35A, can be received from any transponder. That is, the same EPG data is transmitted to any transponder.

Next, the CPU 29 creates a sort table 230 for searching data of a predetermined channel from the EPG data stored in the EPG area 35A,
It is stored in the SRAM 36. This sort table 230
Corresponds to the entire EPG table 240 for searching each program for 4.5 hours from the current time of all channels (for example, 200 channels). CPU 29
Reads out, from the EPG table 240, data of a program (program) in a predetermined range of time for a channel in a display area 250 in a predetermined range from the EPG area 35A and writes it as bit map data in the OSD area 25aA of the DRAM 25a. . Then, the MPEG video decoder 25 reads out the bitmap data of the OSD area 25aA and outputs it to the monitor device 4, so that the monitor device 4 receives a guide EP such as a general guide.
G can be displayed.

When a character or the like is displayed as OSD data, since the character data stored in the EPG area 35A is compressed, a process of restoring the character data is performed using the dictionary. For this reason, the compression code conversion dictionary is stored in the ROM 37. The compression code conversion dictionary includes a syllable dictionary and a word dictionary. One syllable dictionary and three word dictionaries are prepared.

A word is represented by 2-byte data, and the first 1 byte is a number representing the dictionary type of these three types of words, and is 0, 1 or 2. Of the 2-byte data, the remaining 1 byte arranges words prepared in advance in the order of 0 to 255, and one word is represented by the number. When transmitting a predetermined word, the encoder on the transmitting side transmits the word by transmitting the 2-byte code. The same dictionary as this conversion dictionary prepared on the encoder side is prepared in the ROM 37, and the 2-byte code is restored to the original word using this conversion dictionary.

When characters other than the prepared words are transmitted, one word is transmitted by combining a predetermined one of 252 kinds of prepared syllables. This syllable is represented by a 1-byte code.

The ROM 37 also stores a correspondence table (address conversion table) between character codes and storage positions of font bitmap data. By referring to this conversion table, the bitmap data corresponding to the predetermined character code can be read and written in the OSD area 25aA. Of course, this bit map data itself is also stored in the ROM 37 at a predetermined address.

Further, the ROM 37 stores Logo data for displaying Logo and
A conversion table of an ogo ID and an address for calling the Logo data (bitmap data) corresponding to the ogo ID is stored. When the Logo ID is known, the L stored in the address corresponding to the ID
By reading the ogo data and writing it in the OSD area 25aA, it is possible to display the Logo or the like of each broadcasting station on the monitor device 4.

The sort table stored in the SRAM 36 is prepared in the order of the channel numbers. When the sort table is used to extract a specific channel or program or change the order,
Rewrite this sort table. However,
As will be described later, this sort table is a table in which position information (pointers) of channel data and program data is stored, and pointers of program data and channel data are a set. Therefore, when the program data and the channel data are rewritten, they are rewritten in units of sets.

FIG. 12 shows an MPEG video decoder 25 and an MPEG audio decoder 26 in the IRD2.
And the like represent a configuration example of a digital PLL circuit for generating a clock necessary for executing the above-described processing. The data (bit stream) supplied from the demultiplexer 24 is the transport I
It is supplied to the SCR detection circuit 311 of C301 and the SCR latch signal generation circuit 312. In this bit stream, an SCR (System) as a time reference value that serves as a reference when decoding video data and audio data is included.
em Clock Reference) is included. That is, the encoder shown in FIG.
Also encoded and transmitted.

SCR is MPEG1 (ISO / IEC
11172), the packet is arranged in the header of a pack formed by a plurality of packets, and the MPEG2 (ISO / ISO /
In IEC 13818), it is arranged in a pack header in MPEG2-PS and in a transport packet in MPEG2-TS.

Alternatively, as shown in the bit stream of FIG. 13, the corresponding video AUX packet is arranged before the video packet containing the video data, the SCR for the video is contained therein, and the audio data is contained therein. The corresponding audio A before the audio packet
A UX packet may be arranged and an SCR for audio may be accommodated therein. The video and audio SCRs usually have the same value, but since they are synchronized, they may have different values.

The SCR detection circuit 311 detects the SCR included in the input bit stream (when there is a video and audio SCR as shown in FIG. 13, one of them is detected), It is output to the phase comparison unit 321. When the SCR latch signal generation circuit 312 detects the SCR from the bit stream, the SCR latch signal generation circuit 312 generates the SCR latch signal synchronized with the detection timing of the SCR and supplies the SCR latch signal to the clock terminal of the register 313.

The register 313 holds the count value output by the counter 314 at the timing when the SCR latch signal is supplied from the SCR latch signal generation circuit 312, and stores it in the STC (System Time C).
lock), and the phase comparison unit 32
Output to 1.

Phase comparison unit 3 composed of CPU 29
21 compares the phases of the SCR output from the SCR detection circuit 311 and the LTIME output from the register 313,
A precisePC corresponding to the phase error is generated, and the phase comparison output unit 315 of the transport IC 301 is generated.
Output to. The phase comparison output unit 315 includes the phase comparison unit 32.
The precisionPC supplied from the No. 1 is D / A converted and output to the low pass filter 322.

The low-pass filter 322 smoothes the analog signal supplied from the phase comparison output unit 315, and a voltage controlled oscillator (VCO: Voltage Controller).
dOscillator) 323. The VCO 323 generates a clock having a frequency of 27 MHz having a phase corresponding to the control voltage supplied from the low pass filter 322, and uses this clock as the MPEG video decoder 25, the MPEG audio decoder 26, N.
It is supplied to the TSC encoder 27 and the like. Further, this clock is supplied to the counter 314 and counted. As described above, the circuit shown in FIG. 12 constitutes a so-called digital PLL circuit.

Next, the operation of the embodiment shown in FIG. 12 will be described. The SCR detection circuit 311 detects the SCR included in the bitstream. This SCR is a value generated by counting the clock that is the reference when encoding video data, audio data, etc. on the encoder side shown in FIG. Therefore, this value becomes SCR (0) at the first timing (predetermined reference timing (timing of 0)) as shown in FIG. 14, and at timings m and n, SCR (m) and SCR (n). Becomes The SCR detection circuit 311 uses such SCR (0), SCR (m), S
CR (n) and the like are detected and output to the phase comparison unit 321.

On the other hand, the counter 314 counts the clock output from the VCO 323. When the SCR latch signal generation circuit 312 detects an SCR in the bitstream, the SCR latch signal generation circuit 312 generates an SCR latch signal and outputs it to the register 313. As a result, the register 313 holds the count value of the counter 314 at the timing when the SCR is detected in the bitstream as LTIME.
Therefore, the LTIM held in this register 313
The value of E also changes as time passes, as shown in FIG. That is, at a timing of 0 (predetermined reference), it becomes LTIME (0), at a timing of m, it becomes LTIME (m), and at a timing of n, it becomes LTIME (n).

These LTIME (0) and LTIME
(M) and LTIME (n) are SCR (0) and SC respectively when there is no phase error with SCR.
It has the same value as R (m) and SCR (n). However, in practice, the phase error d (0) (= S
CR (0) -LTIME (0)), d (m) (= SCR
(M) -LTIME (m)), d (n) (= SCR
(N) -LTIME (n)) will exist.

Therefore, the phase comparison unit 321 detects the SCR and LT.
Compare the phase with IME, and obtain the phase error precision
Ask for a PC. The phase comparison output unit 315 is the phase comparison unit 3
The phase error precisionPC output from 21 is D / A converted into a phase error PC and supplied to the VCO 323 via the low pass filter 322. As a result, VCO32
Servo is applied so that the phase of the clock generated by 3 coincides with the phase of the SCR (so that the phase error PC becomes 0).

Next, referring to FIG. 15, the phase comparison unit 321
The phase comparison process in 1) will be described in more detail.
First, in step S1, the CPU 29 determines that the absolute value of the differential phase error D (n) at that timing (n timing in this case) is the drift 1 of this PLL circuit.
It is determined whether it is larger than the allowable value A.

That is, it is determined whether or not the following equation is established. | D (n) |> A ... (1) Here, D (n) is represented by the following equation. D (n) = d (n) -d (0) ... (2) Further, as described with reference to FIG. 14, d (n) = SCR (n) -LTIME (n) ... ( 3)

In step S1, the differential phase error D
When it is determined that the absolute value of (n) is larger than the allowable value A, the process proceeds to step S2, and the phase error d (n) at the current timing of n is set to the phase error d at the reference timing (timing of 0). Set to (0). That is, when the absolute value of the differential phase error D (n) is large enough to exceed the allowable value A, it takes time to absorb this error in the PLL circuit, and therefore the target phase error d (0) is reset. Then, the current phase error d (n) is set. Then, from this time, the phase error is controlled again. This makes it possible to lock the PLL circuit more quickly. Therefore, when it is determined in step S1 that the absolute value of the differential phase error D (n) is equal to or smaller than the allowable value A, the process of step S2 is skipped.

Next, in step S3, the interval inter
It is determined whether val is larger than the minimum interval B. That is, the following equation is determined.

Interval> B (4) Here, the interval interval is expressed by the following equation. interval = SCR (n) -SCR (m) ... (5) This m timing represents the timing when the SCR immediately before the current n timing is detected.

In step S3, the interval interv
When it is determined that al is larger than the minimum interval B, it is considered that a phase error to be adjusted has occurred between timing m and timing n. Therefore, in this case, the process proceeds to step S4 and the following equation is calculated. Control_value = [D (n) + d (n) -d (m)] × K / (interval) (6) precisionPC = precisePC + Control_value (7) Here, the coefficient K is a constant.

D (n) in the above equation (6) is Con
This is a component that vibrates troll_value around d (0), and (d (n) -d (m)) is the Contro
It is a component that makes l_value converge to 0. Conventionally,
To find this Control_value, type D
Only one of (n) or (d (n) -d (m)) was considered. As a result, Control_value
The value of e cannot be set accurately, and the video data or audio data is not stored in the DRAM 25a or the DRAM 2
In 6a, overflow or underflow sometimes occurred. In this embodiment, the Control_value is calculated in consideration of the two components, and this value is added to the previous phase error precisionPC to calculate the current phase error precisionPC, so that an accurate phase error is calculated. Therefore, it is possible to suppress the occurrence of overflow or underflow in the memory.

After the above calculation is performed in step S4, the process proceeds to step S5, and it is determined whether or not the absolute value of the detailed phase error precisionPC obtained in step S4 is smaller than the upper and lower limit values C. To do. That is, the following equation is calculated. ｜ precisePC ｜ ＜ C ・ ・ ・ (8)

When it is determined in step S5 that the absolute value of precisePC is equal to or greater than the limit value C, the process proceeds to step S6 and the phase error p
Clip the value of recisePC to its limit. That is, it is prohibited that the value of precisePC becomes larger than necessary. As a result, the phase of the clock generated by the PLL circuit is prevented from moving to the opposite polarity phase more than necessary, and it takes longer to converge the phase. In step S5, precis
When it is determined that the absolute value of ePC is smaller than the limit value C, the process of step S6 is skipped.

Next, in step S7, the phase error precisionP set in step S4 or step S6 is set.
The value of C is output to the phase comparison output unit 315 and converted into an analog signal.

In step S3, the interval interv
If it is determined that al is equal to or smaller than the minimum interval B, the interval interval is short even if time elapses from the timing m immediately before to the current timing n, and adjustment is made during that time. It is unlikely that the phase error deviates as much as necessary. Therefore, in this case, no special processing is executed and the phase error PC at the previous timing is output as it is.

In the above embodiments, the present invention is applied to IRD.
The case of application to 2 was explained as an example, but this IRD
Can be substantially built in the monitor device 4 (television receiver). The present invention also provides IRD2
Besides, it can be applied to other digital data processing devices that process digital signals in synchronization with a clock.

[0103]

As described above, according to the digital data processing device of the first aspect and the digital data processing method of the seventh aspect, the reference is made corresponding to the comparison result of the differential phase error with the allowable differential phase error. Since the phase error is set to the phase error at that time, the clock can be generated quickly.

According to the digital data processing device and the digital data processing method of the eighth aspect, a predetermined difference is added to the sum of the differential phase error, the phase error at that time, and the immediately preceding phase error. Along with multiplying the coefficient, the control value divided by the interval is calculated, and the control value is added to the control signal at that time to obtain a new control signal.
It is possible to generate a clock with a small phase error.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration example of an AV system to which the present invention is applied.

FIG. 2 is a block diagram showing an electrical connection state of the AV system of FIG.

FIG. 3 is a front view showing a configuration example of the front surface of the IRD 2 of FIG.

FIG. 4 is a block diagram showing an internal configuration example of an IRD 2 in FIG.

5 is a plan view showing a configuration example of an upper surface of a remote commander 5 of FIG.

FIG. 6 is a block diagram showing an internal configuration example of a remote commander 5 in FIG.

FIG. 7 is a diagram illustrating segmentation of channel data and program data.

[Fig. 8] Fig. 8 is a diagram illustrating a process in the encoder on the transmission side and a process of the IRD 2 that receives the output thereof.

FIG. 9 is a diagram illustrating division of storage areas of the DRAM 25a of FIG.

10 is an EP stored in the EPG area 35A of FIG.
It is a figure explaining G data.

FIG. 11 is a diagram illustrating the operation of the demultiplexer.

FIG. 12 is a block diagram illustrating a configuration example of a digital PLL circuit that generates a clock.

FIG. 13 is a diagram for demonstrating a bitstream carrying an SCR.

14 is a timing chart illustrating the operation of the embodiment of FIG.

15 is a flowchart illustrating the operation of the embodiment of FIG.

[Explanation of symbols]

1 AV system 2 IRD 3 parabolic antenna 4 Monitor device 4A CRT 5 Remote Commander 21 tuner 23 Error correction circuit 24 demultiplexer 25 MPEG Video Decoder 25a DRAM 26 MPEG Audio Decoder 26a DRAM 29 CPU 35 data buffer memory 35A EPG area 36 SRAM 37 ROM 38 EEPROM 39 IR receiver

Continuation of front page (56) Reference JP-A-8-46605 (JP, A) JP-A-8-149428 (JP, A) JP-A-8-212701 (JP, A) JP-A-3-243034 (JP , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/033 H03L 7/10 H04N 7/24

Claims (8)

(57) [Claims] 1. A detection means for detecting a time reference value for generating a clock serving as a reference for processing digital data, a generation means for generating the clock in response to a predetermined control signal, and the generation means. Counting means for counting the generated clock, acquisition means for acquiring the count value of the counting means at the timing when the time reference value is detected by the detection means, and the control signal for controlling the generation means Therefore, the time reference value detected by the detection means,
In a digital data processing device comprising: a comparison unit that compares the phase with the count value acquired by the acquisition unit, the comparison unit has a phase error as a difference between the time reference value and the count value, and a predetermined value. An allowable difference phase error comparing means for comparing a difference phase error as a difference between the reference phase error as a difference between the time reference value and the count value at a reference timing of a predetermined allowable difference phase error, and the allowable difference Corresponding to the comparison result of the phase error comparison means,
And a reset means for resetting the reference phase error and setting the phase error at that time. 2. The comparing means multiplies the sum of the differential phase error, the phase error at that time, and the phase error immediately before then by a predetermined coefficient, and the phase error at that time The digital data processing device according to claim 1, further comprising a calculation unit that calculates a control value divided by an interval as a difference from the phase error immediately before that time. 3. The digital data processing device according to claim 2, wherein the arithmetic unit adds the control value to the control signal at that time to obtain a new control signal. 4. The limiting means for limiting the value of the control signal to the limit value when the control signal obtained by adding the control values is larger than a predetermined limit value. Item 3. The digital data processing device according to item 3. 5. The digital data processing apparatus according to claim 4, further comprising a decoding unit that decodes the transmitted digital data by using the clock generated by the generation unit. 6. A detection means for detecting a time reference value for generating a clock as a reference for processing digital data, a generation means for generating the clock in response to a predetermined control signal, and the generation means. Counting means for counting the generated clock, acquisition means for acquiring the count value of the counting means at the timing when the time reference value is detected by the detection means, and the control signal for controlling the generation means Therefore, the time reference value detected by the detection means,
In a digital data processing device comprising: a comparison unit that compares the phase with the count value acquired by the acquisition unit, the comparison unit has a phase error as a difference between the time reference value and the count value and a predetermined value. The difference phase error as the difference between the reference phase error as the difference between the time reference value and the count value at the reference timing, the phase error at that time, and the sum of the phase errors immediately before that, the predetermined A coefficient is multiplied, and a control value divided by an interval as a difference between the phase error at that time and the phase error immediately before at that time is calculated, and the control value is added to the control signal at that time. A digital data processing device, characterized in that the control signal is newly provided. 7. A time reference value for generating a clock serving as a reference for processing digital data is detected, the clock is generated in response to a predetermined control signal, the generated clock is counted, and the time is calculated. The count value of the clock at the timing when the reference value is detected is acquired, the detected time reference value and the phase of the acquired count value are compared, and the control signal is set in accordance with the phase error. In the digital data processing method to generate, the phase error as the difference between the time reference value and the count value, and as the difference between the reference phase error as the difference between the time reference value and the count value at a predetermined reference timing The differential phase error is compared with a predetermined allowable differential phase error, and when the differential phase error is larger than the allowable differential phase error, the reference phase error is reset, The digital data processing method, wherein the phase error is set. 8. A time reference value for generating a clock serving as a reference for processing digital data is detected, the clock is generated in response to a predetermined control signal, the generated clock is counted, and the time is calculated. The count value of the clock at the timing when the reference value is detected is acquired, the detected time reference value and the phase of the acquired count value are compared, and the control signal is set in accordance with the phase error. In the digital data processing method to generate, the difference as the difference between the phase error as the difference between the time reference value and the count value and the reference phase error as the difference between the time reference value and the count value at a predetermined reference timing. The phase error, the phase error at that time, and the sum of the phase error immediately before that time is multiplied by a predetermined coefficient,
A control value divided by an interval as a difference between the phase error at that time and the immediately preceding phase error at that time is calculated, and the control value is added to the control signal at that time to obtain a new control signal. A digital data processing method comprising: