JP3398979B2 - Demodulator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator and, for example, to a demodulator for demodulating a digital phase modulation signal. 2. Description of the Related Art With the development of digital transmission, for example, so-called two-phase modulation (BPSK) and four-phase modulation (QPSK) using satellite communication, the ground station equipment has been developed. Demodulators for demodulating digital modulation signals are also required to be smaller and have lower power, and demodulators composed of digital circuits have been developed. More specifically, for example, a QPSK demodulator for demodulating a QPSK modulated signal, as shown in FIG. 6, uses a so-called intermediate oscillation signal using mutually orthogonal local oscillation signals supplied from a so-called local oscillator (not shown). Multipliers 101 _I and 101 _Q for reproducing so-called quadrature quasi-synchronous demodulation of a frequency signal (hereinafter referred to as an IF signal) to reproduce a two-phase modulated signal;
The analog / digital (hereinafter, referred to as A / D) converters 102 _I , 1 1 convert the phase modulated signals of each series from 01 _I , 101 _Q into digital signals using a sampling clock from a clock recovery circuit 107 described later.
02 _Q and a complex multiplying circuit 103 for so-called quadrature demodulation of the QPSK modulated signal converted into a digital signal by the A / D converters 102 _I and 102 _Q to reproduce a baseband signal.
A carrier phase detection circuit 104 for detecting a phase error for reproducing a carrier (hereinafter referred to as a carrier), a loop filter 105 for reproducing the carrier, and a phase error filtered by the loop filter 105. A so-called digital VCO that generates carriers (hereinafter referred to as NCO:
Numerically Controlled Oscillator) 106
And a clock recovery circuit 107 for recovering a sampling clock or the like based on the baseband signal from the complex multiplication circuit 103. Then, a so-called DPLL (Digital Phase Lo) is used.
In the clock recovery circuit 107 constituting the clock loop, a sampling clock or the like twice as large as the bit clock of the transmission data is reproduced, and the QPSK modulated signal is converted into a digital signal using this sampling clock. To the NCO 106, and reproduces the carrier in the complex multiplication circuit 103, and quadrature-demodulates the QPSK modulated signal using the carrier to reproduce the baseband signals of the I and Q sequences. It has become. In other words, in this QPSK demodulator, the A / D converter 102
To NCO 106 operate with the sampling clock reproduced by the clock reproducing circuit 107, and demodulate the QPSK modulated signal by digital signal processing. Then, the baseband signals I and Q obtained in this way are discriminated between 1 and 0 based on the bit clock reproduced by the clock reproducing circuit 107 in an identification reproducing circuit (not shown) at the subsequent stage, or Viterbi decoding. After such data processing, error correction and the like are performed as necessary. As a result, the original data is reproduced. [0005] The above-mentioned NC
O106 is two read-only memories (hereinafter referred to as ROM) in which carriers orthogonal to each other, that is, sine wave waveform data whose phases are shifted from each other by π / 2 are stored in advance.
The phase accumulator generates a read address of the ROM based on the filtered phase error supplied from the loop filter 105, and uses the read address to read two ROMs orthogonal to each other. And supplies these carriers to the complex multiplying circuit 103. The operating speed of the above-described phase accumulator and ROM is slower than that of the A / D converters 102 _I and 102 _Q and the complex multiplying circuit 103. The operating speed of the whole QPSK demodulator is the operating speed of the NCO 106. Limited by
There is a problem that it cannot operate at high speed. In other words, the conventional QPSK demodulator has a problem that the data transmission rate (so-called data rate) cannot be made too high. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a demodulator capable of increasing the data rate as compared with a conventional demodulator. [0008] In order to solve the above-mentioned problems, a demodulation apparatus according to the present invention comprises an analog / digital conversion means for converting a phase modulation signal into a digital signal using a sampling clock. Complex multiplication means for reproducing a baseband signal by multiplying a phase modulation signal converted into a digital signal by an analog / digital conversion means with a carrier, and detecting a phase error of the carrier based on the baseband signal from the complex multiplication means A phase detecting means, a filter means for filtering a phase error from the phase detecting means, a carrier wave generating means for generating a carrier based on the filtered phase error from the filter means, and supplying the carrier to the complex multiplying means. Reproduces a single sampling clock with a predetermined frequency based on the baseband signal from the complex multiplying means A sampling clock regenerating means for supplying the sampling clock to the analog / digital converting means and the complex multiplying means; and a frequency dividing means for dividing a single sampling clock having a predetermined frequency supplied from the sampling clock regenerating means by N And Then, at least one of the phase detection means, the filter means, and the carrier generation means is operated by a clock having a predetermined frequency from the frequency dividing means and obtained by dividing a single sampling clock by N. In the demodulation device to which the present invention is applied, at least one of the phase detection means, the filter means and the carrier generation means is operated by a clock obtained by dividing the sampling clock by N. An embodiment of a demodulation device according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a circuit configuration when the present invention is applied to a so-called four-phase modulation (QPSK) demodulator. As shown in FIG. 1, the QPSK demodulator includes quadrature quasi-synchronous demodulation of a so-called intermediate frequency signal (hereinafter referred to as an IF signal) and multipliers 11 _I and 11 _Q for reproducing a two-phase modulated signal. An analog / digital (hereinafter referred to as A / D) converter for converting the phase modulated signals of the respective series from the multipliers 11 _I and 11 _Q into digital signals using a sampling clock from a clock recovery circuit 17 described later. 12 _I , 12 _Q and the A / D converter 12 _I ,
A complex multiplying circuit 13 for reproducing a baseband signal by so-called quadrature demodulation of a QPSK modulated signal converted to a digital signal from 12 _Q, and a carrier phase for detecting a phase error for reproducing a carrier (hereinafter referred to as a carrier). Detection circuit 14 and loop filter 1 for regenerating carrier
5, a so-called digital VCO (hereinafter referred to as NCO: Numerically Controlled Oscillator) 16 for generating a carrier based on the phase error filtered by the loop filter 15, and sampling based on a baseband signal from the complex multiplying circuit 103. The clock recovery circuit 17 for recovering a clock or the like, and a frequency dividing circuit 18 for dividing the sampling clock from the clock recovery circuit 17 by N are provided. A so-called DPLL (Digital Phase Lo)
cked Loop), the frequency f of which is at least twice the frequency fb of the bit clock.
A sampling clock having a s is reproduced, and the A / D converters 12 _I and 12 _Q convert the QPSK modulated signal into a digital signal using the sampling clock, and then convert the QPSK modulated signal into a digital signal. The carrier is reproduced in the carrier reproducing circuit, and Q
The PSK modulation signal is quadrature-demodulated to reproduce each baseband signal of the I and Q sequences. In other words,
The QPSK modulation signal is demodulated by digital signal processing. More specifically, the multipliers 11 _I and 11 _Q perform quadrature quasi-synchronous demodulation on the IF signal using mutually orthogonal local oscillation signals supplied from a so-called local oscillator (not shown),
The two-phase modulation signal is reproduced. The A / D converters 12 _I and 12 _Q are connected to the multiplier 1
The phase modulation signals of each series supplied from 1 _I and 11 _Q are
Each bit signal is converted into a digital signal using a sampling clock having a frequency twice as high as that of the bit clock supplied from the clock recovery circuit 17, for example. The complex multiplying circuit 13 includes an A / D converter 1
The respective phase modulated signals converted into digital signals at 2 _I and 12 _Q are subjected to the operations shown in the following formulas 1 and 2 such as multiplying the mutually orthogonal carriers from the NCO 16 to reproduce the baseband signals I and Q. . I + jQ = (X + jY) (C + jS) = (XC-YS) + j (XS + YC) Therefore, I = (XC-YS) Equation 1 Q = (XS + YC) Equation 2 Note that C = cos2πf _C t ··· Equation 3 S = sin2πf _C t ··· Equation 4 where X is a phase modulation signal from the A / D converter 12 _I , and Y is from the A / D converter 12 _Q. , And C and S are mutually orthogonal carriers supplied from the NCO 16 and represented by the above formulas 3 and 4, respectively. Note that f _C represents the frequency of the carrier. The baseband signals I and Q obtained in this way are used to determine whether a bit clock reproduced by the clock reproduction circuit 17 in a subsequent stage identification reproduction circuit (not shown) determines 1 or 0, After data processing such as Viterbi decoding is performed, error correction and the like are performed as necessary. As a result, the original data is reproduced. On the other hand, as shown in FIG. 2, for example, the carrier phase detection circuit 14 constituting the Costas loop excludes the sign bits representing the polarities of the baseband signal I and the baseband signal Q from the complex multiplication circuit 13. An exclusive-OR circuit 14a that performs an exclusive-OR operation, an exclusive-OR circuit 14b that performs an exclusive-OR operation on the sign bits of the baseband signal Q and the baseband signal I, and an exclusive-OR circuit 14a is composed of a subtracter 14c for subtracting the output of the exclusive OR circuit 14b from the output, performs calculation of the following formula 5, detects a phase error delta _C carriers, the phase error delta _C in the loop filter 15 Supply. [0020] _{Δ C = Isign (Q) -Qsign} (I) ··· Equation 5 [0021] The loop filter 15, for example, as shown in FIG. 3, cumulative addition of phase error delta _C from the subtracter 14c And a delay unit 15b for delaying the output of the adder 15a by N sampling clocks.
When, a multiplier 15c for multiplying the β phase error delta _C from the subtractor 14c, a multiplier 15d for multiplying the α to the output of the adder 15a, the output of the output multiplier 15d of the multiplier 15c And an adder 15e for adding. That is, the loop filter 15 is a first-order recursive digital filter, and has a transfer function H
The (Z) filters by multiplying the phase error delta _C, and supplies the filtered phase error delta _C to NCO 16. H (Z) = (Z / (Z−1)) × (α + β) − (1 / (Z−1)) × β (6) The NCO 16 is, for example, as shown in FIG. To
An adder 16a for adding the address step δf the filtered phase error delta _C from the adder 15e, an adder 16b for accumulating the output of the adder 16a, the output of the adder 16b N A delay unit 16c that delays by the sampling clock and a read-only memory (hereinafter referred to as R
OM) 16d and a ROM 16e in which the waveform data of the carrier S shown in the above equation 4 is stored in advance. [0024] Then, in this NCO16 phase error delta _C that is filtered is supplied from the loop filter 15,
For example ROM16d, with adding the address step δf is the step of reading addresses 16e, the address step δf is summed phase error delta _C integrated by accumulating, as a read address the integration values obtained were orthogonal to each other The waveform data of the carriers S and C are read, and the waveform data is supplied to the complex multiplication circuit 13. Thus, the complex multiplication circuits 13 to NCO 16
In Costas type carrier reproducing circuit configured in, is played carriers orthogonal to each other, such as phase errors delta _C becomes 0, the demodulation of the QPSK modulation signal is performed using these carriers. On the other hand, the clock reproducing circuit 17, a clock phase detecting circuit for detecting a phase error of the sampling clock, the loop filter consists of so-called VCO, etc., detects a phase error delta _S of the sampling clock to the example, the base band signals I, after filtered by the loop filter having the same structure as the phase error delta _S the above loop filter 15, and controls the VCO based on the filtered phase error delta _S. Therefore, from this clock recovery circuit 17, such as a phase error delta _S becomes zero,
That is, a sampling clock whose phase matches that of the baseband signal I is reproduced. The reproduced sampling clock is supplied to the A / D converters 12 _I , 12 _Q ,
It is supplied to the complex multiplication circuit 13 and the frequency division circuit 18. The frequency dividing circuit 18 frequency-divides the sampling clock supplied from the clock reproducing circuit 17 by N, and supplies the obtained clock to the carrier phase detecting circuits 14 to NCO 16. That is, in this QPSK demodulator, the carrier phase detection circuits 14 to NCO 16 operate at 1 / N of the sampling clock. Specifically, as shown in FIG. 5B, for example, the sampling clock is a bit clock (FIG. 5C) having the same frequency as the data transmission speed (so-called data rate).
5A), the sampled values # 1, # 2, # 3,... (Odd numbers are in synchronization with the sampling clock) from the complex multiplication circuit 13 as shown in FIG. 5A. (Significant data at symbol points, and even numbers represent data at change points). And the carrier phase detection circuit 1
4 fetches every fourth sample value # 1, # 5, # 9,... Using a clock obtained by dividing the sampling clock as shown in FIG.
Detecting a phase error delta _S carriers using these sample values, and supplies the NCO16 phase error delta _S detected via the loop filter 15. Therefore, the carrier phase detection circuits 14 to NCO 16 operate at 1 / N of the sampling clock, for example, at 1/4 clock. Thus, in this QPSK demodulator, the NCO 16 that limits the overall operation speed can be operated at a frequency of 1 / N (for example, 1/4) as compared with the conventional device. If the maximum operation speed of the QPSK demodulator is the same, the entire QPSK demodulator can be operated at a higher speed (for example, four times) than the conventional device. In other words, the data rate can be increased. Further, for example, when the data rates are the same, the carrier phase detection circuits 14 to NCO 16 can be operated at a lower speed as compared with the conventional device, and the power consumption can be greatly reduced. Also, the data rate is low, and there is room for reading the ROMs 16d and 16e.
In the PSK demodulation apparatus, the number of ROMs can be reduced by storing waveform data of carriers orthogonal to each other in one ROM in advance and reading out the two carriers in a time-division manner. Further, for example, it is also possible to store only one part of the waveform data of one cycle of the sine wave and to form the other part of the waveform data from the one part of the waveform data, thereby reducing the capacity of the ROM. It is possible. The present invention is not limited to the above-described embodiment. For example, the carrier phase detecting circuits 14 to N
At least one of the CO 16 is set to the sampling clock N
By operating with the divided clock, power consumption can be reduced. Further, it goes without saying that the present invention can be applied to a demodulation device in digital modulation such as so-called BPSK demodulation and MSK modulation. As is apparent from the above description, in the demodulation device to which the present invention is applied, at least one of the phase detection means, the filter means, and the carrier generation means divides the sampling clock by N. By operating with a clock, the carrier generation means, which limits the overall operation speed, can be operated at a frequency of 1 / N as compared with the conventional device. For example, the maximum operation speed of the carrier generation means is the same. In this case, the entire demodulation device can be operated at a higher speed than the conventional device. In other words, the data rate can be increased. Further, for example, when the data rates are the same, the phase detecting means to the carrier wave generating means can be operated at a lower speed as compared with the conventional apparatus, and the power consumption can be greatly reduced. Further, in a demodulator having a low data rate, the number and capacity of the ROMs constituting the carrier generation means can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a circuit configuration of a QPSK demodulator to which the present invention is applied. FIG. 2 is a block diagram illustrating a specific circuit configuration of a carrier phase detection circuit included in the QPSK demodulation device. FIG. 3 is a block diagram illustrating a specific circuit configuration of a loop filter included in the QPSK demodulation device. FIG. 4 is a block diagram showing a specific circuit configuration of an NCO included in the QPSK demodulation device. FIG. 5 is a time chart for explaining the operation of the QPSK demodulation device. FIG. 6 is a block diagram showing a circuit configuration of a conventional QPSK demodulator. [Description of Signs] 12 _I , 12 _Q: A / D converter 13: Complex multiplication circuit 14: Carrier phase detection circuit 15: Loop filter 16: NCO 17: Clock recovery Circuit 18 ・ ・ ・ Division circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/00 H04L 7/00

Claims (1)

(57) [Claim 1] Analog / digital conversion means for converting a phase modulation signal into a digital signal using a sampling clock, and phase modulation converted into a digital signal by the analog / digital conversion means Complex multiplying means for multiplying a signal by a carrier to reproduce a baseband signal; phase detecting means for detecting a phase error of the carrier based on the baseband signal from the complex multiplying means; and phase from the phase detecting means. Filter means for filtering an error; a carrier generation means for generating a carrier based on the filtered phase error from the filter means; and supplying the carrier to the complex multiplication means; and a baseband signal from the complex multiplication means. A single sampling clock is reproduced at a predetermined frequency based on A sampling clock regenerating means for supplying to the analog / digital conversion means and the complex multiplying means; and a frequency dividing means for dividing a single sampling clock having a predetermined frequency supplied from the sampling clock regenerating means by N; A demodulator characterized in that at least one of a phase detector, a filter, and a carrier generator is operated at a predetermined frequency from the frequency divider and a clock obtained by dividing a single sampling clock by N.