JP3381339B2 - Error diffusion circuit for pseudo halftone display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo-halftone display device (for example, a plasma display panel) in which the number of bits of a drive signal is reduced to increase the light emission brightness and the image quality is not deteriorated. The present invention relates to an error diffusion circuit of a display device (hereinafter simply referred to as PDP).

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention is paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system by a digitized video input signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs can be divided into two types, AC type and DC type, which have different basic characteristics. In DC type PDPs, there have been reports of improvement methods for brightness and life, which have already been issues, and progress toward practical application is being made. is there.

However, in the AC type PDP, although sufficient characteristics have been obtained in terms of brightness and service life, with regard to gradation display, only a maximum of 64 gradation display has been reported at the prototype level. A future 256-gradation method based on the die driving method (ADS subfield method) has been proposed. The structure of the PDP 10 used in this method is shown in FIG.
The drive sequence and drive waveform are as shown in FIGS. 4A and 4B.

In FIG. 3, an X sustain electrode 12 and a Y sustain electrode 13 which form a pair are formed on the lower surface of the surface glass substrate 11 on the display surface side by a transparent electrode and an auxiliary electrode. The auxiliary electrode forms the bus electrode 23 on a part of the transparent electrode in order to prevent a voltage drop due to the resistance of the transparent electrode. A dielectric layer 14 is provided on the X sustain electrode 12 and the Y sustain electrode 13, and a stripe rib 18 is formed on the dielectric layer 14 to separate the coupling between the cells. Further, a protective layer 15 made of a MgO film is deposited. Address electrodes 17 are formed on the back glass substrate 16 facing each other. The stripe-shaped ribs 18 on the stripes are provided between the address electrodes 17, and the address electrodes 17 are covered with R.
The (red) phosphor 19, the G (green) phosphor 20, and the B (blue) phosphor 21 are separately formed. In the discharge space 22, Ne +
Xe mixed gas is enclosed.

In FIG. 4A, one frame has a relative luminance ratio of 1, 2, 4, 8, 16, 32, 64, 12.
It is composed of 8 sub-fields of 8, and 256 gradations are displayed by combining the brightness of 8 screens. In FIG. 4B, each subfield is composed of an address period for writing refreshed data for one screen and a sustain period for determining the brightness level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display. The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

[0006]

In the AC driving method as described above, as the number of gradations increases, the number of bits in the address period as the preparation period for lighting and emitting the panel within one frame period increases. The sustain period as a light emitting period becomes relatively short, and the maximum brightness decreases. In this way, the brightness gradation emitted from the panel surface is
Since it depends on the number of bits of the signal to be handled, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission brightness is reduced. Conversely, if the number of bits of the signal to be handled is reduced, the light emission brightness is increased. The number of displays is reduced and the image quality is deteriorated.

The present applicant has proposed an error diffusion circuit 28 of a pseudo halftone display device as shown in FIG. 5 in order to solve the above-mentioned problems (Japanese Patent Application No. 5-229542).
issue). In the error diffusion circuit 28 shown in FIG. 5, the video output terminal 3 is connected to the video signal input terminal 30 via the vertical direction addition circuit 31, the horizontal direction addition circuit 32 and the bit conversion circuit 33.
4 is connected, and the error detection circuit 35 is connected to the output side of the horizontal direction addition circuit 32.

Then, the error detection circuit 35 is connected to the PDP 10
(Read-only memory) 3 that stores the data of the correction brightness level preset for the brightness gradation correction of
8. Setting data of this ROM 38 and horizontal direction addition circuit 3
The subtraction circuit 39 outputs a difference signal from the diffused output signal from 2 and outputs an error signal, and the weight circuits 40 and 41 output a difference weight signal by weighting the difference signal with a predetermined weight.

At the output side of the weighting circuits 40 and 41 of the error detection circuit 35, a reproduction error E (i, i) that occurs in the pixel h line before the original pixel A (i, j), for example, one line in the past.
j-1) is connected to the vertical direction addition circuit 31 via the h line delay circuit 36, and the original pixel A
It is connected to the horizontal direction addition circuit 32 via a d dot delay circuit 37 that outputs a reproduction error E (i-1, j) that occurs d dots before (i, j), for example, one dot in the past. There is.

Then, the diffusion output signal in which the error is incorporated and diffused by the vertical direction addition circuit 31 and the horizontal direction addition circuit 32 is sent to the bit conversion circuit 33, and the diffusion output quantized by n bits by the bit conversion circuit 33. Signal to m
(≦ n−1) bits and converted from the video output terminal 34 to P
It is output to DP10 as a drive signal. In this way
An original image input signal is diffused by incorporating an error, and a signal having a bit number smaller than that of the original image input signal allows a smooth response to be obtained without lowering the emission brightness.

However, in the error diffusion circuit 28 shown in FIG. 5, when video signals of the same level are continuously input to the video signal input terminal 30, for example, an 8-bit original pixel video signal is FF, FF, ... , FF, the error weight output values output from the weight circuits 40 and 41 to the h-line delay circuit 36 and the d-dot delay circuit 37 are the same and continuous. ,
There is a slight problem that the PDP 10 displays a pseudo pattern which is a regular repeating pattern.

Next, the phenomenon of creating this pseudo pattern will be described with reference to FIG.
This will be described with reference to FIG. It is assumed that the light emission luminance level with respect to the drive signal to the PDP 10 is actually measured and the light emission luminance level is normalized by its maximum value to obtain the stepwise measurement line shown in FIG. In this example, the video input signal is 8 bits, and the drive signal is 4 bits. A corrected luminance line represented by y = ax + b is obtained based on the measured line. This corrected luminance line is y
Since it is slightly deviated from the ideal line of = x, it is necessary to correct it. The luminance line corrected for this is shown in FIG. 7, where {(corrected luminance line gradient a
-1) -Corrected luminance line contact piece b} is corrected. As shown in FIG. 7, stepwise data when the correction luminance line is corrected to be y = x is stored in the ROM (read only memory) 38.

FIG. 8 is an enlarged view of a part of FIG. In this FIG. 8, a: video input pixel value (in the case of a constant value) b: pseudo halftone levels e1, e2, e3 for the input a: error output d1, d2, d3: error weight output,

Further, as shown in the figure, the emission brightness level Br
Is black, black, black, and Br + 1 is white, white, and white. (1) b-Br = e1, e1 × Kh = d1, a + d1 =
Since it is e2, a + d2 = black. (2) Since a + d2 = e3, a + d2 = white. (3) Since d3 = 0, a + d3 = a, which is black. (4) Because the above is repeated, black, white, black, black, white, black,
Black, white, black, ... and black, white, black appear at regular intervals.
That is, a pseudo pattern appears. The above is considered only in the horizontal direction, but the same applies to the vertical direction. Therefore, considering both horizontal and vertical directions, a repeating pattern appears two-dimensionally.

The present invention has been made in view of the above-mentioned problems, and minimizes the shading error between the input signal and the light emission luminance while reducing the bit number of the output drive signal more than the bit number of the input signal. An object of the present invention is to provide an error diffusion circuit of a pseudo halftone display device which can prevent the generation of a pseudo pattern even when video signals of the same level are continuously input.

[0016]

An error diffusion circuit of a pseudo halftone display device according to the present invention adds a reproduction error generated in the past from the original pixel to a video signal of an input n-bit original pixel. An addition circuit, a bit conversion circuit for converting the diffusion output signal output from the reproduction error addition circuit into an m (≦ n−1) -bit signal and outputting the signal to the display panel, and for correcting the brightness gradation of the display panel. An error detection circuit that detects a difference between a preset correction luminance level and a diffusion output signal output from the reproduction error addition circuit, weights and outputs the difference, and an error weight output signal output from the error detection circuit are predetermined. An error diffusion circuit including a delay circuit for delaying by a pixel and outputting as a reproduction error to the reproduction error addition circuit, wherein the pseudo random pulse signal is generated at a dot or line unit timing. A pseudo random pulse generating circuit to be generated, and when the number of consecutive occurrences of H or L level of the pseudo random pulse signal of the pseudo random pulse generating circuit exceeds a set value, outputs an inversion signal of the pseudo random pulse signal and sets it. A correction amount control circuit that outputs a non-inverted signal of the pseudo random pulse signal when the value does not exceed, and an output signal of this correction amount control circuit is multiplied by ± k (| k | <1) times and output. It is characterized by comprising a correction coefficient circuit and a correction addition circuit for adding the signal output from the correction coefficient circuit to the signal in the error diffusion circuit.

[0017]

The error detection circuit detects and weights the difference between the diffused output signal output from the reproduction error addition circuit and the preset correction luminance level, and outputs the weighted signal. The delay circuit delays the error weight output signal output from the error detection circuit by a predetermined number of pixels and outputs it as a reproduction error to the reproduction error addition circuit. The reproduction error adding circuit adds the reproduction error from the delay circuit to the input n-bit video signal of the original pixel.

As described above, the n-bit diffused output signal obtained by incorporating the reproduction error of the peripheral pixels generated in the past from the original pixel into the original pixel video signal by the reproduction error addition circuit and diffusing it is m (n -1 bit or less) and is output to the display panel (for example, PDP) from the video output terminal. Therefore, a signal having a smaller number of bits than the original image input signal can provide a smooth response without lowering the emission brightness.

Further, the correction addition circuit adds the pseudo random pulse signal generated by the pseudo random pulse generation circuit, multiplied by ± k by the correction coefficient circuit, and controlled by the correction amount control circuit to the signal in the error diffusion circuit. Therefore, even if the level of the input original pixel video signal is the same and continuous, it can fluctuate in the video output signal (driving signal) output from the video output terminal to the display panel (for example, PDP), and the same continuous value can be obtained. It does not become. Therefore, it is possible to prevent (suppress) the generation of the pseudo pattern on the display panel.

Moreover, since the cycle of the pseudo random pulse signal is lengthened, the period in which the H level (for example, 1) or L level (for example, 0) continuously appears becomes long, which causes noticeable noise. Even in such a case, the correction amount control circuit, when the number of consecutive occurrences of the H or L level of the pseudo random pulse signal generated by the pseudo random pulse generation circuit exceeds the set value, the inversion signal of the pseudo random pulse signal. Is output, it is possible to reduce the period in which the H or L level of the pseudo-random pulse signal component included in the video output signal continuously appears, and reduce the noticeable noise.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an error diffusion circuit of a pseudo halftone display device according to the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals. In FIG. 1, reference numeral 30 denotes a video signal input terminal of an n-bit original pixel A (i, j). The video signal input terminal 30 includes a vertical direction addition circuit 31, a correction addition circuit 50, and a horizontal direction addition circuit 3.
2, the bit conversion circuit 33 further reduces the number of bits, and the bit conversion circuit 33 is connected to the video output terminal 34. The vertical direction addition circuit 31 and the horizontal direction addition circuit 32 constitute a reproduction error addition circuit.

Reference numeral 52 is a pseudo random pulse generation circuit for generating a pseudo random pulse signal at a timing of dot or line unit. This pseudo-random pulse signal is a signal which can be regarded as a random pulse signal because it has a certain period of repetition but its period is sufficiently long. The pseudo random pulse generation circuit 52 is composed of a primitive polynomial circuit and an M-sequence code generation circuit. This primitive polynomial circuit is composed of, for example, a 19th-order primitive polynomial circuit mainly composed of 19 flip-flop circuits and 3 adder circuits, and has a cycle (2 ¹⁹ -1) (that is, cycle 52).
4, 287), H (for example, 1) and L (for example, 0) random pulse signals are output. Here, the cycles 524 and 287 represent that the length of one cycle is 524 and 287 times the unit pulse period.

A correction amount control circuit 54 is coupled to the output side of the pseudo random pulse generation circuit 52. The correction amount control circuit 54 includes the pseudo random pulse generation circuit 5
The correction amount monitoring circuit 56 that monitors whether or not the number of consecutive occurrences of H level (for example, 1) or L level (for example, 0) of the pseudo random pulse signal of 2 exceeds a set value (for example, 3).
And an inverting circuit 58 which inverts and non-inverts the pseudo random pulse signal of the pseudo random pulse generating circuit 52 based on the monitoring signal of the correction amount monitoring circuit 56 and outputs the pseudo random pulse signal. When the number of consecutive appearances of the level exceeds the set value, an inverted signal of the pseudo random pulse signal is output, and when the number of consecutive appearances does not exceed the set value, the pseudo random pulse signal is output as it is.

The output side of the correction amount control circuit 54 is ± k
It is coupled to the correction addition circuit 50 via a correction coefficient circuit 60 which multiplies the coefficient by (| k | <1) times and outputs it.
An error detection circuit 3 is provided on the output side of the horizontal addition circuit 32.
5 is connected. The error detection circuit 35 has a ROM 38 in which data of a correction brightness level for brightness gradation correction is set and stored in advance, a correction brightness level set in the ROM 38, and a diffusion output signal output from the horizontal addition circuit 32. The subtraction circuit 39 calculates the difference between the error detection signals and outputs the error detection signal, and the weighting circuits 40 and 41 which output the error weighting signal obtained by weighting the error detection signal output from the subtraction circuit 39 with a predetermined weight.

The load circuits 40 and 4 of the error detection circuit 35
The vertical direction adder circuit 31 and the horizontal direction adder circuit 32 are connected to the output side of 1 via an h line delay circuit 36 and a d dot delay circuit 37, respectively. The h-line delay circuit 36 delays the error-weighted output signal output from the weighting circuit 40 by h-line, and the original pixel A (i,
j), a reproduction error (for example, when h = 1, a reproduction error E (i, j-1) that occurred in the past by one line when h = 1) is output, and the d dot delay circuit 3 is output.
Reference numeral 7 delays the error weight output signal output from the weight circuit 41 by d dots, and is d from the original pixel A (i, j).
Reproduction error for the pixel before the dot (for example, when d = 1, the reproduction error E (i-1,
j)) is output.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. 2, 6 and 7. (1) When the corrected luminance line is a straight line As shown in FIG. 6, the emission luminance level with respect to the drive signal to the PDP 10 is actually measured, and based on the actual measurement line obtained by normalizing the emission luminance level with its maximum value, y = A corrected luminance line represented by ax + b is obtained. This corrected luminance line is y = x
Since it is slightly deviated from the ideal line, it is necessary to correct it. The luminance line corrected for this is shown in FIG. 7, where {(corrected luminance line gradient a−
1) -Corrected luminance line contact piece b} is corrected.
The step-shaped data when the correction luminance line is corrected so that y = x as shown in FIG. 7 is stored in the ROM 38.

When the corrected luminance line is y = x, the corrected luminance level becomes the same as the emission luminance level. Therefore, assuming that the number of drive output bits is m, the brightness level data of 2 m power words (2 4 power 16 words when m = 4) is R.
It may be stored in the OM 38. In addition, in FIG.
When the corrected luminance line y = ax + b almost coincides with y = x, the actual measurement data shown in FIG. 6 is stored in the ROM 38 without performing the processing shown in FIG. Good.

The principle of the error diffusion method in the above configuration is similar to that of the previously proposed circuit of FIG. 5, where density modulation is performed with two luminance gradations, and a visual effect is given within a small area having a certain spread. This is to create pseudo gradation and obtain multiple gradations. This will be described in more detail with reference to FIG. A (i, j): input pixel value of current processing target A (i, j-1): input pixel value one line before (when h = 1) A (i-1, j): one dot before Input pixel value (in the case of d = 1) δv: Error load value of diffusion output pixel from one line before δh: Diffusion output from one dot before Diffusion output input to error detection circuit 35 The subtraction circuit 39 takes the difference between the signal and the data from the ROM 38 to obtain an error output signal.

This error output signal is applied to the weight circuits 40 and 41.
Then, Kv (<1) and Kh (= 1−Kv) are weighted error weight output signals δv and δh, respectively, and the 1-line delay circuit 36 (in the case of h = 1) and the 1-dot delay circuit 37.
(In the case of d = 1), it is incorporated into the original pixel A (i, j) by the vertical direction addition circuit 31 and the horizontal direction addition circuit 32, and C (i, j) = A (i, j) + δv + δh Become.

C (i, j): diffused output pixel value of the current processing target δv = Kv × [f {C (i, j-1)}-Br] δh = Kh × [f {C (i- 1, j)}-Br] f {C (i, j)}: correction luminance Br for C (i, j): emission luminance level.

The diffusion output signal in which the error is incorporated and diffused is sent to the bit conversion circuit 33, and this bit conversion circuit 33 is transmitted.
The spread output signal quantized with n bits at m (≤n
-1) Converted to bits and output from the video output terminal 34. In this way, the original video input signal is diffused by incorporating an error, and a signal having a bit number smaller than that of the original video input signal allows a smooth response to be obtained without lowering the emission brightness.

Further, the correction addition circuit 50 outputs from the pseudo random pulse generation circuit 52 and the correction amount control circuit 54.
Then, the pseudo random pulse signal multiplied by ± k in the correction coefficient circuit 56 is added to the input signal at the output side of the vertical direction addition circuit 31 for each dot or line, and thus is input to the video signal input terminal 30. Even if the level of the original pixel video signal has the same continuous value, it is possible to prevent the continuous data from fluctuating and generating a regular repeating pattern in the diffused output. Therefore, it is possible to prevent (suppress) the generation of the pseudo pattern on the PDP 10.

At this time, the pseudo random pulse generation circuit 5
2 generates a random pulse signal in a cycle of a predetermined length (for example, cycles 524 and 287), and the number of appearances of H (for example, 1) and L (for example, 0) in this cycle is equal to 52.
The sum of the data when the correction addition is performed in the period of 4,287 pulses and the sum of the data when the correction addition is not performed are equal, and the correction addition amount of the image data is ± 0. Is.

In addition, the correction amount control circuit 54 generates a pseudo random pulse when the number of consecutive occurrences of the H or L level of the pseudo random pulse signal generated by the pseudo random pulse generation circuit 52 exceeds a set value (for example, 3). Since the inverted signal of the signal is output, the period in which the H or L level of the pseudo random pulse signal component included in the video output signal continuously appears can be shortened to make noise inconspicuous.

(2) When the corrected luminance line is not a straight line When it is desired to correct the luminance of the PDP 10 in a curved shape (gamma correction, etc.), the corrected luminance line is set to a desired curve, and the error value from the emission luminance level is set. It is obtained and set and stored in the corrected luminance level setting circuit in the same manner as in the case of (1) above. Other actions are the same as in the case of the above (1).

In the above embodiment, the reproduction error addition circuit is composed of the vertical direction addition circuit and the horizontal direction addition circuit, and the correction addition circuit is inserted between the vertical direction addition circuit and the horizontal direction addition circuit. The present invention is not limited to this.
For example, the reproduction error addition circuit may be configured by only one of the vertical direction addition circuit and the horizontal direction addition circuit. Further, the correction addition circuit may be provided at an appropriate position where the pseudo random pulse signal can be added to the signal in the error diffusion circuit.
For example, in FIG. 1, between the video signal input terminal 30 and the vertical direction addition circuit 31, the output side of the horizontal direction addition circuit 32, or between the subtraction circuit 39 and the weight circuits 40 and 41,
The correction addition circuit 50 may be inserted.

In the above embodiment, the case where the display panel is a PDP has been described, but the present invention is not limited to this, and the present invention can be applied to the case of a display panel other than the PDP (for example, a liquid crystal display panel).

In the above embodiment, the correction amount control circuit is composed of the correction amount monitoring circuit and the inverting circuit, but the present invention is not limited to this, and the pseudo random pulse signal H
Alternatively, it outputs an inverted signal of the pseudo random pulse signal when the number of consecutive appearances of the L level exceeds the set value, and outputs a non-inverted signal of the pseudo random pulse signal when the number of consecutive appearances does not exceed the set value. I wish I had it.

[0039]

As described above, the error diffusion circuit of the pseudo halftone display device according to the present invention has a reproduction error addition circuit (for example, a vertical direction addition circuit or a horizontal direction addition circuit), a bit conversion circuit, an error detection circuit, and a delay. This error detection circuit detects the difference between the corrected luminance level and the diffused output signal, weights it, and outputs it to the delay circuit. With a signal having a smaller number of bits, a smooth response can be obtained without lowering the emission brightness.

Further, since the correction addition circuit adds the pseudo random pulse signal generated by the pseudo random pulse generation circuit and multiplied by ± k by the correction coefficient circuit to the signal in the error diffusion circuit, the original pixel image to be input. Even if the signal levels have the same continuous value, they can fluctuate in the video output signal (driving signal) output from the video output terminal to the display panel (for example, PDP) and do not have the same continuous value. Therefore, it is possible to prevent (suppress) the generation of the pseudo pattern on the display panel.

In addition, the cycle of the pseudo random pulse signal is lengthened to lengthen the period in which the H or L level continuously appears, and even when noise is likely to stand out, the correction amount control circuit Since the inversion signal of the pseudo random pulse signal is output when the number of consecutive occurrences of the H or L level of the pseudo random pulse signal generated by the pseudo random pulse generation circuit exceeds the set value (for example, 3), the video output By shortening the period in which the H or L level of the pseudo-random pulse signal component included in the signal continuously appears,
Noise can be made inconspicuous.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error diffusion circuit of a pseudo halftone display device according to the present invention.

FIG. 2 is an explanatory diagram of coordinate positions of pixels.

FIG. 3 is a perspective view of a PDP (an example of a display panel) used in a 256 gradation method.

FIG. 4 is a drive sequence diagram and a drive waveform diagram in the 256 gradation method.

FIG. 5 is a block diagram of an error diffusion circuit of the pseudo halftone display device that the present applicant has already proposed.

FIG. 6 is an actual measurement diagram of drive signal vs. emission luminance level.

FIG. 7 is a characteristic diagram of a corrected brightness level.

8 is an enlarged view in which a part of the actual measurement line of the drive signal vs. emission luminance level shown in FIG. 6 is extracted.

[Explanation of symbols]

10 ... PDP (plasma display panel), 1
1 ... Surface glass substrate, 12 ... X sustain electrode, 13
... Y sustain electrode, 14 ... Dielectric layer, 15 ... Protective layer, 16 ... Back glass substrate, 17 ... Address electrode,
18 ... Strip-shaped ribs, 19 ... R (red) phosphor, 2
0 ... G (green) phosphor, 21 ... B (blue) phosphor, 22 ...
Discharge space, 23 ... Bus electrode, 30 ... Video signal input terminal, 31 ... Vertical direction addition circuit (one example of reproduction error addition circuit), 32 ... Horizontal direction addition circuit (one example of reproduction error addition circuit), 33 ... Bit conversion circuit , 34 ... video output terminal,
35 ... Error detection circuit, 36 ... h line delay circuit, 37
... d dot delay circuit, 38 ... ROM, 39 ... subtraction circuit, 40, 41 ... weight circuit, 50 ... correction addition circuit, 5
2 ... Primitive polynomial circuit (an example of a pseudo random pulse generating circuit), 54 _{1 to} 54 ₃ , 62 ... Adder circuit, 56 ... Correction coefficient circuit, 60 ... M sequence code generating circuit (an example of pseudo random pulse generating circuit), D _{0 to} D ₁₈ ... Flip-flop circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa, Ltd.Fuji General Co., Ltd. (56) References JP-A-7-121135 (JP, A) JP-A-5-114999 (JP, A) JP-A-6-284275 (JP, A) JP-A-5-199413 (JP, A) JP-A-2-107062 (JP, A) JP-A-3-291691 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/20 641 G09G 3/28 G09G 3 / 288 G09G 5/00

Claims (3)

(57) [Claims] 1. A video signal of an input n-bit original pixel,
A reproduction error adding circuit that adds a reproduction error generated in the past from the original pixel, and a diffusion output signal output from the reproduction error adding circuit are converted into an m (≦ n−1) bit signal and output to a display panel. A bit conversion circuit, and an error detection circuit for detecting a difference between a correction brightness level preset for brightness gradation correction of the display panel and a diffusion output signal output from the reproduction error addition circuit, weighting and outputting the error. And a delay circuit for delaying the error weight output signal output from the error detection circuit by a predetermined number of pixels and outputting it as a reproduction error to the reproduction error addition circuit, at a timing of dot or line unit. Pseudo-random pulse generation circuit for generating a pseudo-random pulse signal and H of the pseudo-random pulse signal of this pseudo-random pulse generation circuit
Alternatively, a correction amount control circuit that outputs an inverted signal of the pseudo random pulse signal when the number of consecutive appearances of the L level exceeds a set value and outputs a non-inverted signal of the pseudo random pulse signal when the number of consecutive appearances of the L level does not exceed the set value. And a correction coefficient circuit that outputs the output signal of the correction amount control circuit by multiplying the coefficient by ± k (| k | <1) times, and the signal output from this correction coefficient circuit to the signal in the error diffusion circuit. An error diffusion circuit of a pseudo halftone display device, comprising: a correction addition circuit for adding. 2. A correction amount control circuit for monitoring whether or not the number of consecutive occurrences of H or L level of a pseudo random pulse signal of a pseudo random pulse generation circuit exceeds a set value, and the correction amount control circuit. The error diffusion circuit of the pseudo halftone display device according to claim 1, further comprising: an inverting circuit that inverts and non-inverts the pseudo random pulse signal of the pseudo random pulse generating circuit based on a monitoring signal of the monitoring circuit and outputs the inverted signal. 3. The reproduction error adder circuit comprises a vertical direction adder circuit and a horizontal direction adder circuit connected in series from the input side to the output side, and the correction adder circuit is the vertical direction adder circuit and the horizontal direction adder circuit. The delay circuit, which is inserted between the circuits, delays the error weight output signal output from the error detection circuit by h lines and outputs it to the vertical direction addition circuit, and outputs it from the error detection circuit. 3. A d-dot delay circuit for delaying an error weight output signal by d dots and outputting the delayed signal to the horizontal addition circuit.
An error diffusion circuit of the described pseudo-halftone display device.