JP3355556B2 - A / D conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D having a low bit output.
The present invention relates to an A / D conversion circuit for performing A / D conversion of a high-bit output using a converter.

[0002]

2. Description of the Related Art Conventional A / D conversion circuits include a parallel comparison type and an integration type. The parallel comparison type A / D conversion circuit
It has 2N comparators for obtaining N-bit resolution, a resistor group for setting a reference value of each comparator, and an encoder for converting the output of each comparator into an N-bit binary code. The advantage is that high-speed conversion can be obtained.

[0003] An integrating A / D conversion circuit includes an integrator for integrating an input voltage and a reference voltage, a switch for switching between the input voltage and the reference voltage, and a comparator for comparing the output of the integrator with a reference value. And a counter that counts the output signal period of the comparator in principle, and has the advantage that high resolution A / D conversion can be realized with a relatively simple configuration.

[0004]

However, the parallel comparison type A / D conversion circuit requires 2N comparators to convert the number of N bits, so that the circuit scale becomes large.
Further, the integration type A / D conversion circuit has a problem that the conversion speed is slow.

An object of the present invention is to provide an A / D conversion circuit capable of high-speed and high-bit output without increasing the circuit scale even if an A / D converter with a low bit output is used. That is.

[0006]

For this purpose, a first aspect of the present invention provides a signal separating circuit for separating each signal component from an input signal having M signal components, and each signal separated by the signal separating circuit. Sample-and-hold circuits for sampling and holding data, an N-bit A / D converter, and a signal output to the A / D converter by selectively and selectively switching the outputs of the M sample-and-hold circuits A switching circuit;
M N-bit first latch circuits for latching the output signal of the / D converter in accordance with the switching timing of the signal switching circuit, and output signals of each of the M N-bit first latch circuits Multipliers for multiplying the output signals by one or more different magnifications, an N + A-bit adder for adding the output signals of the M multipliers, and an N + A latching the output signal of the adder
And a second bit latch circuit.

According to a second aspect of the present invention, in the first aspect, the input signal is M = 2 as a composite video signal having a luminance signal and a chroma signal, and a multiplier for multiplying the digital signal of the luminance signal is: The magnification was made larger than the multiplier of the multiplier for multiplying the digital signal of the chroma signal.

[0008]

According to the present invention, M signals included in an input signal are separated and digitized by one internal N-bit A / D converter, and the digital signal is converted by M latch circuits. The signal is latched by dividing it into M signals, the latch outputs are multiplied by multipliers having different magnifications, and then added by an adder, latched and output, thereby extracting an N + α-bit digital signal. By using a high-speed A / D converter as the internal A / D converter, high-speed and high-bit output can be performed without increasing the circuit scale even if the A / D converter has a low bit.

[0009]

Embodiments of the present invention will be described below. FIG. 1 shows an A / D conversion circuit according to one embodiment of the present invention. Here, N
An example in which a video composite signal of a TSC television signal is input and A / D converted will be described.

Reference numeral 1 denotes an input terminal for inputting the video composite signal, and reference numeral 2 denotes a signal separation circuit that separates a luminance signal Y and a chroma signal C from the video composite signal and adjusts the level of each signal. Reference numerals 3 and 4 denote sample / hold circuits for sampling / holding the luminance signal Y and the chroma signal C separated by the signal separation circuit 2, respectively. Sampling signal S1 input to this one sample hold circuit 3
And the sampling signal S2 input to the other sample-and-hold circuit 4 have the same frequency (the chroma signal C
(Approximately 3 to 5 times the frequency).

Reference numeral 5 denotes a signal switching circuit composed of an analog switch or the like.
Switching is performed by a switching signal S3 having the same frequency as that of S2, and the outputs of the sample and hold circuits 3 and 4 are alternately selected. Reference numeral 6 denotes an A / D converter for A / D converting a hold signal output from the signal switching circuit 5, and is an 8-bit parallel comparison type.

Reference numerals 7 and 8 denote latch circuits which latch output data of the A / D converter 6 by latch signals L1 and L2 having the same frequency as the above-mentioned sampling signals S1 and S2 and having mutually opposite phases. I do. A multiplier 9 triples the input data. Reference numeral 10 denotes an adder for adding the data output from the multiplier 9 and the data output from the latch 8 (equivalent to the one-time multiplier without the multiplier), and 11 an adder for the adder 10. A latch circuit for holding output data with a latch signal L3 (same frequency as the latch signals L1 and L2), and 12 is a digital output terminal.

In the A / D conversion circuit, the signal separation circuit 2 separates the luminance signal Y and the chroma signal C from the composite video signal, and the maximum value of these signals is set to the A / D converter 6 in the subsequent stage. These levels are adjusted so as to have a level corresponding to the input full range. The signals Y and C are alternately sampled by the sample and hold circuits 3 and 4 by the sampling signals S1 and S2 and held. The held signals Y and C are transmitted to the signal switching circuit 5.
, And is converted into an 8-bit digital signal by the A / D converter 6 at the next stage. Although the level of the chroma signal C is considerably smaller than that of the luminance signal Y, such separation is performed, and the level is adjusted in accordance with the full range of the A / D converter 6 and then A / D converted. The signals C and Y can be represented by the same resolution (8 bits).

The digital signal of the luminance signal Y is selectively latched by the latch circuit 7 and is multiplied by the multiplier 9 by three. The output digital value of this latch circuit 7 is 2 in decimal notation.
In the case of 55, if this is multiplied by three, it becomes 765 in decimal notation and can be represented by 10 bits of a binary number. In this way, the multiplier 9 outputs a luminance signal represented by a 10-bit digital signal.

On the other hand, the digital signal of the chroma signal C is selectively latched by the latch circuit 8 and is added by the adder 10 to the digital signal output from the multiplier 9.
In the adder 10, the chroma signal digital value C1 and the luminance signal digital value Y1 are added at a certain sampling time t1, and the previous chroma signal digital value C1 and the next luminance signal digital value Y2 are added at the next sampling time t2. At the next sampling time t3, the next chroma signal digital value C2 and the previous luminance signal digital value Y2 are added.

Here, the digital value of the chroma signal C is 8 bits (the maximum value is 255 in decimal), and the luminance signal Y
Digital value is 10 bits (the maximum value is 76 decimal digits)
5), and when these are added, the maximum value of the decimal number is 1020. This can be represented by 10 bits in binary (the maximum value is 1023 in decimal). In this way, a decimal digital signal is output from the adder 10 and this is latched by the latch circuit 11 and the output terminal 1
Output to 2.

Thus, from the output terminal 12, the input terminal 1
And outputs a 10-bit digital signal obtained by A / D-converting the composite video signal input to. Each of the luminance signal Y and the chroma signal C represented by this digital signal is a signal having an 8-bit resolution. Since an 8-bit parallel comparison type A / D converter 6 is used internally to obtain this digital signal, this conversion can be realized at high speed.

In the above-described embodiment, the digital value of the luminance signal is tripled by the multiplier 9 and the digital value of the chroma signal is kept as it is. Processing can also be performed. At this time, the number of bits of the digital signal obtained at the output terminal 12 is larger than 10 bits.

[0019]

As described above, according to the present invention, high-speed, high-bit output can be performed without increasing the circuit scale even if an A / D converter with low-bit output is used.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an A / D conversion circuit according to an embodiment of the present invention.

[Explanation of symbols]

1: input terminal, 2: signal separation circuit, 3, 4: sample hold circuit, 5: signal switching circuit, 6: A / D converter,
7, 8: (first) latch circuit, 9: multiplier, 10: adder, 11: (second) latch circuit, 12: output terminal.

Claims (2)

(57) [Claims] A signal separation circuit for separating each signal component from an input signal having M signal components; M sample and hold circuits for sampling and holding each signal separated by the signal separation circuit; An N-bit A / D converter; a signal switching circuit for sequentially and selectively switching the outputs of the M sample-and-hold circuits to output to the A / D converter; an output signal of the A / D converter M first latch circuits of N bits that latch in accordance with the switching timing of the signal switching circuit, and output signals of each of the M first latch circuits of N bits that are different from each other by one or more different magnifications. M multipliers, an N + α-bit adder for adding the output signals of the M multipliers, and an N + α-bit second latch circuit for latching the output signal of the adder. A / characterized by Conversion circuit. 2. The input signal is a composite video signal having a luminance signal and a chroma signal, wherein M = 2, and a multiplier for multiplying a digital signal of the luminance signal is multiplied by a digital signal of the chroma signal. 2. The A / D conversion circuit according to claim 1, wherein the magnification is larger than the multiplier.