JP3352348B2 - Code modulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for modulating original information into a code suitable for a recording medium, including a state indicated by the modulated code (modulation code), a numerical value of the original information to be modulated next, and a modulation code. The present invention relates to a code modulation circuit in a code modulation scheme for selecting a modulation code for original information to be modulated next from a plurality of modulation codes by a run restriction between a DSV value indicating a degree of a DC component to be performed and a preceding modulation code.

[0002]

2. Description of the Related Art In recent years, CDs (Compact Di
Attention has been paid to the fact that sk: a compact disc has a large recording capacity, and it is widely used as an information recording medium for a computer as a CD-ROM (Read Only Memory). A DVD (Digi) having a recording capacity of seven times or more that of a conventional CD on a disk of the same size as a CD
tal Video Disc) has been proposed. DVD is expected to be widely used not only as a recording medium for video but also as a DVD-ROM used as a storage medium for a computer, similarly to a CD-ROM, due to its large recording capacity. I have.

[0003] In the optical disc apparatus Ru with these optical discs, the signal to be recorded on the a recording medium disc,
The information is not modulated as it is in the original information, but is modulated and recorded into a code suitable for recording. By modulating and recording the original information in this way, high-density recording becomes possible.
There are advantages such as easy self-synchronization and narrowing of the signal transmission band. For this reason, code modulation is one of the indispensable technologies not only in the optical disc device but also in the information reproducing (recording) device.

For example, in the case of a CD, an EFM (Eight
A code modulation method called Fourteen Modulation) is adopted to convert 8-bit original information into a 14-channel bit code, and insert a 3-channel bit code into the code to evaluate the DC component of the modulation code. DSV (Digital
Sum Value) is made smaller. Also, if the minimum value of the run length (the length of the series of the same bit information) is large, it is advantageous in terms of the recording density and the signal band, but the smaller the maximum value of the run length is advantageous in terms of self-synchronization. Become. For this reason, the run length is limited to a minimum of 2 and a maximum of 10.

In the case of DVD, a code modulation method called 8-16 modulation is adopted. The 8-16 modulation is a code modulation method for modulating 8-bit original information into a code of 16 channel bits. If the minimum value of the run length is large, it is advantageous in terms of recording density and signal band. A smaller maximum length is advantageous in terms of self-synchronization. For this reason, the run length is limited to 2 to 10 similarly to the EFM modulation. 8-
16 modulation is performed by a main table and a sub table. When performing modulation, modulation codes (main, sub, state) corresponding to a plurality of original information are controlled by DC component suppression control so as to reduce DSV. One is selected from 1) to 4). Actually, the original information is modulated into an 8-16 modulation code according to the flowchart shown in FIG. 10 together with a Sync (synchronization) code for synchronizing at the time of reproduction.

FIG. 11 is a block diagram showing an 8-16 modulation circuit operating according to the flowchart shown in FIG.
1101, 1102 are latches, 1103 is a mixer, 1104 is a decoder, 1
105 is a comparator, 1106 is a logic circuit, 1107 is an 8-16 conversion table, 1108 is a Sync code table, 1109 is a latch, 11
10, 1111 are selectors, 1112, 1113 are NRZI converters, 1114, 111
5 is an up / down (U / D) counter, 1116 is a selector, 11
17 is a comparator.

In FIG. 1, a latch 1101 holds original information (input data) to be code-modulated, and a latch 1102 holds a next-state. The mixer 1103 is for switching between state, main and sub, and the decoder 1104 is for recognizing the state. The comparator 1105 determines whether or not the original information to be code-modulated is equal to or greater than the value of 88. According to the determination result and the output of the decoder 1104, the logic circuit 1106
A switching signal for the 10,1111,1116 and the mixer 1103 is generated.

The 8-16 conversion table 1107 has a main table and a sub-table. The original information held in the latch 1101 is converted by the main and sub-tables based on the output of the mixer 1103, and the converted data is converted. (Modulation data) is held in the latch 1109. The Sync code from the Sync code table 1108 is also held in the latch 1109. The selector 1110 is for selecting the modulation data output from the 8-16 conversion table 1107 or the modulation data held in the latch 1109. The selector 1111 is a next used for the next modulation.
This is for selecting -state.

The NRZI converters 1112 and 1113 convert the modulated parallel data into serial NRZI data. The up / down counters 1114 and 1115 check the run length and DSV from the output data of the NRZI converters 1112 and 1113, respectively.
Selector 1116 selects the DSV obtained by the up / down counters 1114 and 1115,
1117 compares the magnitudes of these DSVs and sends the comparison result to the logic circuit 1106.

Next, the operation of the 8-16 modulation circuit will be described with reference to the flowchart shown in FIG.

The Sync code is inserted between the recording data at regular intervals, and a selection is made as to whether or not to insert the Sync code (step 1001). This is controlled by a timing signal from a timing generator (not shown) in FIG.

If the Sync code is code-modulated, two types (Type 1 and Type 2) of Sync codes corresponding to the states are output from the Sync table 1108, and one of them is latched as Sync1. It is held at 1109 (step 1025). The other is output as Sync2 (step 1027). Sync1 and Sync2 are NRZI converters 1112,
After being converted into serial data in 1113, it is supplied to up / down counters 1114 and 1115, and its DSV is calculated (steps 1026 and 1028). Sync1 obtained by each of these
The DSV value DSV1 of Sync2 and the DSV value DSV2 of Sync2 are compared with the comparator 1117.
(Step 1029), and the logic circuit 1106 outputs a selection signal to the selector 1110 according to the comparison result. As a result, the smaller DSV value of Sync1 and Sync2,
The sync code is selected and output by the selector 1110 (steps 1030 to 1032).

Next, a case where input data (original information) is code-modulated and the converted original information has a value of 87 or less will be described (steps 1001 and 1002).

When the original information held in the latch 1101 is found to be 87 or less by the comparator 1105 (step 1003), the logic circuit 1106 sends a signal 8-
A control signal is output from the main table and the sub-table of the 16 conversion table 1107 so as to output modulated data corresponding to the original information. As a result, the modulation code and the next-state output from the main table correspond to the data mod1, st1, respectively.
The modulation data and the next-state output from the sub-table are output as data mod2 and st2, respectively (step 1006).

The modulation codes mod1 and mod2 are NRZI converters, respectively.
NRZI conversion is performed at 1112, 1113, and the up-down counter 1114,
According to 1115, the DSV value DSV1 of the modulation code mod1 and the modulation code mod2
Is calculated (steps 1005 and 1007). These DSVs 1 and 2 are compared by the comparator 1117 (step 100).
8), based on the comparison result, the logic circuit 1106 outputs a selection signal for selecting the modulation data, the next-state and the DSV initial value to the selectors 1106, 1110, 1111, and 1116 (steps 1009 and 1010). ).

According to the above processing, when the original information has a value of 87 or less, the modulation code having the smaller absolute value of DSV is selected by the selector 1110 from the modulation data of the main table and the sub-table and output. Similarly, the next-state having the smaller absolute value of DSV is selected by the selector 1111 and held in the latch 1102.

Next, a case where the original information has a value of 88 or more will be described.

If the original information is 88 or more (step 10
03), the processing differs depending on the state of the next-state obtained together with the modulation code of the immediately preceding input data used in converting the original information. That is, when the state is 2 or 3 (step 1011), the modulation data may be output using the conversion table corresponding to the state to calculate the DSV value (steps 1023 and 1024). However, in the case of state 1 or 4, selection is required.

That is, if the next-state held in the latch 1102 by the conversion process of the previous original information is state 1 or 4, and the original information is 88 or more, the logic circuit 1106 causes the mixer 1103 to 8-16 conversion table 1107
And outputs a control signal so as to output a modulation code corresponding to original information from states 1 and 4 of the main table. 8-16
The modulation code according to state 1 and the next-state output from the conversion table 1107 are data mod1 and st1, respectively.
The data is stored in the latch 1109 (step 1012), and the modulation code and the next-state according to the state 4 are data mod2 and st2, respectively.
(Step 1016).

The modulation codes mod1 and mod2 are respectively NRZI
After the NRZI conversion by the converters 1112 and 1113, the data is supplied to the up / down counters 1114 and 1115, and the DSV value DSV of the modulation code mod1 is supplied.
The DSV value DSV2 of 1 and the modulation code mod2 is calculated (steps 1013 and 1017). At that time, up-down counters 1114, 11
Reference numeral 15 performs a restriction check on the run length including the modulation code immediately before the modulation codes mod1 and mod2. That is, if the run lengths of the NRZI-converted modulation codes mod1 and mod2 are 3 or more and 11 or less, they satisfy the run limitation (steps 1014 and 101).
8) If the run length is 2 or less, or 12 or more,
Up-down counter 1114,1 to violate run restrictions
D with 115 run length less than 2 or 12 or more
Overflow SV value (counter value) (step
1015, 1019). Therefore, the absolute value of the DSV of the modulation code that violated the run limit becomes the maximum value. When the absolute value of the DSV is compared by the comparator 1117 (step 1020), the absolute value of the DSV is small and the run limit is satisfied. The modulation code to be used is selected (steps 1021 and 1022). As described above, the values of DSV1 and DSV2 from the up / down counters 1114 and 1115 are compared by the comparator 1117, and based on the comparison result, the logic circuit 1106 modulates the data by the selector 1110 and the next- A control signal for selecting the state and the DSV initial value in the selector 1116 is generated and output.

According to the above processing, when the original information is 88 or more and the state is 1 or 4, the modulation code of the state 1 and the state 4 satisfies the run length restriction and the modulation of the DSV having the smaller absolute value of DSV. The code is selected and output.

As described above, the modulation can be performed by such an 8-16 modulation circuit so as to minimize the absolute value of DSV.

[0023]

Next, FIG.
FIG. 12 shows processing when the operation clock is a channel bit clock in the 8-16 modulation circuit.

As shown in FIG. 12, when the operation is performed on the basis of the channel bit clock, the processing time of 16 channel bits is required to calculate the DSV for one byte. Therefore, in FIG. 11, the processing speed of DSV calculation is improved by having two processing systems.
The processing time for converting the original information of the byte into the modulation code of 16 channel bits requires one byte cycle or more.
Since the read-only DVD or DVD-ROM is used for 8-16 modulation, the processing speed of recording data modulation does not become a significant problem.

However, a DVD-RAM (Random Access Memory) capable of recording and reproducing using the same 8-16 modulation method is used.
In the case of a drive of mory (random access memory) standard, modulation processing speed is a major problem. That is, if a processing time of one byte clock or more is required to modulate one byte of information, more time is required to record a large amount of information, and data transfer is substantially performed. Speed decreases. Further, in the case where large-capacity information such as video information is continuously recorded, there arises a problem that modulation processing cannot keep up and continuous recording cannot be performed.

Therefore, in the 8-16 modulation circuit shown in FIG. 11, in order to terminate the modulation of 1-byte data during 1-byte clock, the operation clock of the processing system of this modulation circuit must be a channel bit clock. It is sufficient to use a double speed clock having a double frequency, and as shown in FIG. 13, the modulation of 1-byte data can be completed during a 1-byte clock cycle.

However, when the code modulation circuit is formed into an IC, a process change may be required in order to speed up the operation clock. In order to increase the recording speed by increasing the rotation speed of the recording medium several times in response to a demand for high-speed data recording, the operation clock needs to be twice as high as the recording operation speed. Therefore, such a code modulation circuit becomes a high-speed clock circuit,
It is susceptible to noise and expensive.

It is an object of the present invention to provide a method for controlling the next state by the state indicated by the modulation code, the numerical value of the original information to be modulated next, the DSV value of the modulation code, and the preceding modulation code, as in the above 8-16 modulation. Provided is a code modulation circuit for performing code modulation for selecting a modulation code to be modulated from among a plurality of modulation codes, wherein the code processing circuit shortens the modulation processing time and does not need to speed up the operation clock. It is in.

[0029]

To achieve the above object, the present invention provides a modulation table for outputting information such as a modulation code, a state, and a run length, and a DSV calculating means for calculating a DSV. , Run length violation detecting means for detecting violations of run length conditions, DSV comparing means for comparing magnitudes of DSV absolute values, and a DSV / run table in which information of DSV values and subsequent run lengths is tabulated. A DSV / run table address control means for outputting the address of the DSV / run table, and a modulation code having a small DSV value that satisfies the run length limitation by the outputs of the run length violation detection means and the DSV comparison means. Selection signal output means for outputting a selection signal for selection,
A modulation table address control unit for outputting a modulation table address based on a selection signal output from the selection signal output unit, a state output of the modulation table, and original information for performing modulation.

[0030]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of a code modulation circuit according to the present invention, wherein 101 and 102 are latches, 103 is a table address controller, and 104 is DSV / r.
un table, 105 is table address controller, 106
Is an 8-16 modulation / Sync code table, 107 and 108 are adder / subtracters, 109 is an adder / subtractor control circuit, 110 is a DSV comparator, 111 and 112
Is an adder, 113 and 114 are comparators, 115 is a selection logic circuit, 116
Is a selector, and 117 is a DSV register.

In FIG. 1, latches 101 and 102 hold input data (original information) for modulation. The DSV / run table 104 stores a run (ru) with a DSV table storing DSVs of modulation codes of 8-16 modulation for input data.
n) a run table storing lengths, and the table address controller 103 generates an address (DSV / run table address) for reading these. 8
-16 modulation / Sync code table 106 is 8-16 modulation table
Sync code table and 8-bit input data
A modulation code of 16 modulations, a Sync (synchronization) code, information indicating the state of the modulation code for the next input data (ie, next-state), and a code “1” included in the modulation code and the Sync code Odd / even information indicating whether the number is even or odd
The O / E, the modulation code, and the run length RL of each Sync code are stored, and an address (8-16 / Sy) for reading these is stored.
nc table address) table address controller
105 is generated.

The adder / subtractor 107 controls the output from the DSV / run table 104 according to the control of the adder / subtractor control circuit 109.
One of the DSV values DSV1 of the system is added or subtracted from the DSV value held in the DSV register 117, and the adder / subtractor 108 also controls the DSV / run table 1 according to the control of the adder / subtractor control circuit 109.
The other DSV2 of the DSV value output from 04 is added to or subtracted from the DSV value held in the DSV register 117. The outputs of these adders / subtractors 107 and 108 have their absolute values as DSV comparators 11.
Compared with 0.

The adder 111 calculates a new run length by adding the run length run1 from the DSV / run table 104 and the run length RL from the 8-16 modulation / Sync code table 106. 112 is the run length ru from the DSV / run table 104
n2 and run length RL from 8-16 modulation / Sync code table 106
To calculate a new run length. The comparators 113 and 114 detect whether or not the run lengths output from the adders 111 and 112 violate restrictions, respectively.

The selection logic circuit 115 controls the table address controller 105 to select a modulation code from the 8-16 modulation / Sync code table 106 based on the comparison result between the DSV comparator 110 and the comparators 113 and 114. Generate and output mod-sel. Also, according to this selection signal mod-sel,
The selector 116 selects the output of the adder / subtractor 107, 108 and causes the DSV register 117 to hold it.

Although not shown, this embodiment is operated by a timing signal output from a timing generator, a channel bit clock, and a byte clock. Hereinafter, the operation of this embodiment in the case where 8-bit original information (input data) is subjected to 8-16 modulation will be described with reference to a timing chart shown in FIG.

The latches 101 and 102 hold input data at the rising edge of the byte clock, respectively. Now, when the n-th data n is input and the byte clock rises, as shown in FIG.
The previous input data n-1 is transferred to and held by the latch 102, and the data 101 is held by the latch 101.

The input data n-1 output from the latch 102 is supplied to the table address controller 105, and the address of the 8-16 modulation / Sync code table 106 corresponding thereto (ie, the 8-16 / Sync table address) Is generated, and the 8-16 / Sync table address is used to generate 8-16 modulation / Sync
A modulation code mod n-1 obtained by performing code modulation (ie, 8-16 modulation) on the input data n-1 from the code table 106, and the input data n
Next-st indicating the state used when modulating
ate n−1, odd / even information O / E n−1 indicating whether the number of codes “1” included in the modulation code mod n−1 is even or odd, and the last code “1” of the modulation code mod n−1 And the run length RL n-1 indicating the number of codes "0" from "."

FIG. 3A is a diagram showing a specific example of the 8-16 / Sync table address, and FIG.
4 is a diagram illustrating a specific example of a modulation code mod output from a sync code table 105. FIG.

In FIG. 3A, an 8-16 / Sync table address is a 1-bit 8-16 / Sync bit indicating switching between 8-16 modulation of input data and a Sync code, and a main / sub table. 1-bit main / sub bit indicating switching, and 2-bit state indicating any of states 1 to 4
It consists of bits and 8-bit address data "data" that specifies the address of the 8-16 modulation table or Sync table. The Main / Sub bit and the state change according to a selection signal mod-sel from the selection logic circuit 115, and the 8-16 / Sync bit changes according to a timing signal output from a timing generator (not shown).

Here, as an example, the 8-16 / Sync bit is “0” when instructing that the input data is subjected to 8-16 modulation, and is “1” when it is a Sync code. Is "0" when indicating the main table, "1" when indicating the sub table, and the state bit is "00" for state 1, "01" for state 2, and "10" for state 3. "," 11 "in state 4.

In FIG. 3B, 8-16 modulation / Sy
The output data including the modulation code mod output from the nc code table 105 includes a 4-bit run length RL, 1-bit odd / even information O / E, 2-bit next-state, and 16-bit modulation code mod data. It consists of The odd / even information O / E is set to “0” for an even number and “1” for an odd number.

Here, a sub-table is designated as output data of the 8-16 modulation / Sync code table 106, and input data to be modulated in state 1 is "0".
Taking the case of as an example, the modulation code mod data at this time is
As shown in FIG. 3B, since the number is "0000010010000000" and there are seven "0" bits following the last "1" bit, the run length RL is "7".
Since the number of “1” bits included in mod data is 2, odd / even information O / E is even and “0”.

In FIGS. 1 and 2, next-state n-1
Indicates a state necessary for performing code modulation of the input data n. However, when the input data n has a value of 87 or less, or when the state when modulating the input data n (that is, next-state n-1) is 1 or 4, the selection of the modulation code based on the DSV value is not performed. You need to do it.

The table address controller 103 compares the input data n held in the latch 101 with the 8-16 modulation / S
The address of the DSV / run table 104 (that is, DSV / run
run table address). With the DSV / run table address, the DSV / run table 104 stores two DSV values DSV1, DSV2 and run lengths run1, r for the same modulation code.
Outputs un2.

FIG. 4A shows DSV / r for input data n.
FIG. 4 is a diagram showing a specific example of an un table address,
FIG. 3B is a diagram illustrating a specific example of output data of the DSV / run table 104.

In FIG. 4A, the DSV / run table address is a 1-bit 8-16 / Sync bit indicating switching between 8-16 modulation of input data and a Sync code, and state 1 to state 1.
A 2-bit state bit indicating any one of 4 and 8-bit address data specifying a table address.
It consists of The 8-16 / Sync bit changes according to a timing signal output from a timing generator (not shown).

Here, the 8-16 / Sync bit and the state bit are the same as the 8-16 / Sync bit and the state bit of the 8-16 / Sync table address shown in FIG.
The state bit of / run table address 104 is next-state
n−1, and the address data “data” is the input data “n” held in the latch 101 for performing the modulation.

In FIG. 4B, the DSV / run table 10
The output data of 4 is DSV value DSV of two systems of 5 bits each.
1, DSV2 and two run lengths each of 4 bits run1, run
n1.

Assuming that next-state n-1 is state 1 and the value of input data n is "0", the DSV / run table address becomes "00000000000" according to FIG. Since the case where 8-16 modulation is performed is described, 8-16 / Sync bit = "0").

On the other hand, the modulation code for the input data n according to the main table of the 8-16 modulation / Sync code table 106 is “00100000000010” as shown in FIG.
01 ". The waveform for such a modulation code is
Similarly, as shown in FIG. 4C, the waveform is such that the level is inverted when the bit changes from "0" bit to "1" bit, and when the level of each bit is "H",
The cumulative value obtained by sequentially adding them as 1, -1 when it is "L" is the DSV value. Therefore, in the waveform shown in FIG. 4C, the DSV value is +6. DSV / run table 104
In this table, such a DSV value for a modulation code according to the main table of the 8-16 modulation / Sync code table 106 is stored as DSV1 of one system.

In the same manner, 8-
The modulation code according to the sub-table of the 16 modulation / Sync code table 106 is “0000010010000000” shown in FIG. 3B, as shown in FIG. 4D. The waveform corresponding to the modulation code is also the waveform shown in FIG. 4D, and the cumulative value obtained by sequentially adding the level values of these bits, that is, the DSV value is as shown in FIG. ,
It becomes 10. The DSV / run table 104 has 8-16 modulation / Syn
Such a DSV value for the modulation code according to the sub-table of the c-code table 106 is stored as DSV2 of the other system.

The DSV in the DSV / run table 104 as described above
According to the table, for example, DSV1 having a value of +6 and DSV2 having a value of -10 are obtained for input data of "0" as described above.

In the DSV / run table 104, as described above, for input data n of 87 or less, 8
The DSV value for the modulation code according to the main table of the −16 modulation / Sync code table 106 is stored as DSV2, and the DSV value for the modulation code according to the sub-table is stored as DSV2. 1
Or, it differs between the case of 4 and the other cases. That is,
In the case of the state 1 or 4, the value of the state 1 is stored in the DSV1, and the value of the state 4 is stored in the DSV2.
V2 is stored as the same value (DSV of the modulation code indicated by the state).

In this embodiment, the DSV value stored in the DSV / run table 104 has a modulation code of a space (for example, "L" level and is added as -1 when DSV is obtained). DSV value when starting from (starting from the “H” mark with inverted level,
In the case where the level is inverted from the case where it starts with a space, the DSV value is different as is clear from comparison of FIGS. 4C and 4D.)

The DSVrun table 104 has two run lengths run.
1. Output run1. These run lengths run1 and run1 are DSV
Even if the value of the lower 8 bits (= input data n) of the / run table address (FIG. 4A) is 87 or less, or 88 or more, it is not used in the case of state 2 or 3, but is used first. Are temporarily output as the number of "0" bits up to the "1" bit. In this case, run1 is represented as the number of “0” bits up to the first “1” bit in the modulation code according to the main table of the 8-16 modulation / Sync code table 106. For example, the DSV / run table address is Is “00000000000”, the modulation code corresponding to this is shown in FIG. 4C, so the run length run1 is 2. Also, run2 is represented as the number of “0” bits up to the first “1” bit in the modulation code according to the sub-table of the 8-16 modulation / Sync code table 106. For example, the DSV / run table address is “0000
0000000 ", the modulation code for this is as shown in FIG. 4D, and the run length run1 is 5
It is.

That is, in the DSV / run table 104, when the input data has a value of 87 or less, the run 1 is set to 8-16 modulation / Sync
The run length of the modulation code according to the main table of the code table 106 is changed to the run 2 by the 8-16 modulation / Sync code table 10.
The run lengths of the modulation codes according to the sub-table 6 are stored.

When the input data n has a value of 88 or more,
There are two cases, and for state 1 or 4,
run1 has the run length of state 1 and run2 has the run length of state 4.
State 2 or 3 is stored.
In the case of, run1 and run2 have the same value sta.
The state indicating the te bit and the run length of the modulation code indicated by the data bit are stored.

In FIG. 1 and FIG. 2, the DSV / run table
DSV1 and DSV2 output from 104 are added and subtracted by 107 and 108, respectively.
Are added to or subtracted from the values held in the DSV register 117, respectively. The value held in the DSV register 117 is the sum of the DSV values up to the input data n-1 (hereinafter, referred to as the input data n-1).
The addition / subtraction unit control circuit 109 determines whether addition or subtraction is performed by the addition / subtraction units 107 and 108.
Is controlled by a control signal SigALU output from the

As shown in FIG. 5, the polarity of the DSV value is inverted depending on whether it starts with a space or a mark. Therefore, in order to calculate the correct DSV value, the start of the modulation code for DSV is marked or
You need to know in advance whether it is a space.

For example, when the modulation code X starts from a space, and when the number of “1” bits included in the modulation code X is an even number, after the modulation is completed, that is, the end of the modulation code X (the next modulation code Is the space, and when the number of “1” bits included in the modulation code X is an odd number, the end of the modulation code X becomes a mark. Similarly, when the modulation code X starts from a mark and the number of “1” bits included in the modulation code X is an even number, the end of the cono modulation code X is a mark,
When the number of “1” bits included in the modulation code X is odd, the end of the modulation code X is a space. Therefore, if the state at the start of the modulation (space or mark) is known, the state of the next modulation start is determined by checking whether the number of “1” bits included in the modulation code is even or odd. It can be known by taking the logical sum.

FIG. 6 shows an adder / subtractor control circuit 109 in FIG.
FIG. 2 is a circuit diagram showing a specific example of the present invention, wherein 120 is an exclusive OR (EOR) circuit, and 121 is a D latch.

In this example, the EOR circuit 120 and the D latch 121
It is composed of The EOR circuit 120 receives the odd / even information O / E and the output data Q of the D latch 121, and
igALU is generated, and this control signal SigALU becomes the input data D of the D latch 121.

Now, assume that the input data to be 8-16 modulated is input data n, the modulation code for the previous input data n-1 is mod data n-1, and the modulation code for the previous input data n-2 is modulation data. The sign is mod data n-2. Also, odd / even information O /
E is 8-16 modulation / Syn until 8-16 modulation of input data is completed
Output is continued from the c code table 106. The latch timing of the D latch 121 is set immediately before the start of 8-16 modulation of the next input data (end of the modulation code of this input data). Further, it is assumed that the reset (initial reset) of the D latch 121 is performed immediately before a modulation code for input data to be subjected to 8-16 modulation first.

The D latch 121 receives E by a latch pulse.
By latching the control signal SigALU output from the OR circuit 120, the modulation code for the input data n-2 immediately before is latched.
State at the end of moddata n-2 (space or mark)
Is held. The output Q indicating this state of the D latch 121 and the modulation code mod of the immediately preceding input data n-1
When the odd / even information O / E for data n-1 is supplied to the EOR circuit 120, the control signal SigALU to be output from this is the end of the modulation code mod data n-1, that is, the modulation code mod for the input signal n. whether the beginning of data n is a space,
This indicates the state of the mark.

That is, if the control signal SigALU is "0" when indicating a space and "1" when indicating a mark, the odd / even information O / E is "1" when indicating an odd number and "1" when indicating an even number. Since the control signal SigALU of “0” (that is, representing a space) is latched by the D latch 121 at the end of the modulation code mod data n−2,
Odd / even information O / E of modulation code mod data n-1 is "1" (odd number)
Then, the control signal SigALU output from the EOR circuit 120 is “1”, the state immediately before the modulation code mod data n is a mark, and the odd / even information O / E of the modulation code mod data n−1 is “0”. If “(even number)”, the control signal SigALU output from the EOR circuit 120 is “0”, and the state immediately before the modulation code mod data n is a space. Also, the modulation code mod data
Assuming that the control signal SigALU of “1” (ie, representing a mark) is latched by the D latch 121 at the end of n−2, the odd / even information O / E of the modulation code mod data n−1 is “1” (odd number). Then, the control signal SigALU output from the EOR circuit 120 is “0”, the state immediately before the modulation code mod data n is a space, and the odd / even information O / E of the modulation code mod data n−1 is “0” ( If it is even, the control signal SigALU output from the EOR circuit 120 is “1” and the modulation code mod data n
The state immediately before is a mark.

In this way, the input data n-2 before the two
From the end state of the modulation code mod data n-2 for the input data and the odd / even information O / E of the modulation code mod data n-1 for the immediately preceding input data n-1,
, The state of the modulation code mod data n can be known.

The D-latch 121 is reset by an initial reset pulse so that its output Q becomes "0" immediately before the input data to be first 8-16 modulated, that is, so as to represent a space. The above operation is performed on a series of input data.

Here, the D-latch 121 is reset so that the space immediately before the modulation code for the input data to be first 8-16 modulated is a space. In this case, the D latch 121 is reset immediately before the modulation code. Is "H" or "L". However, regardless of the level at this time, there is no problem if the level is determined to be, for example, a space, the level is recognized as a space, and the inverted level is recognized as a mark. Even if the space and mark are defined in this manner, that is, whether the level immediately before the modulation code is “H” and a space or “L” and a space, the D output from the DSV / run table 104 is output.
The only difference is whether SV1 and DSV2 are added to or subtracted from the cumulative DSV value of the DSV register 117.
The absolute values of the accumulated DSV values obtained from 7,108 are the same except for the sign of ±. Then, the absolute value of the accumulated DSV value is compared by the DSV comparator 110.

For this reason, the D latch shown in FIG.
Even if 121 is reset to “0” by the initial reset pulse, the accumulated DSV value can be obtained correctly, and there is no problem. Alternatively, it may be preset to “1”.

The DSV comparator 110 determines that the absolute value of the cumulative DSV value from the adder / subtractor 107 that adds / subtracts DSV1 is smaller than or equal to the absolute value of the cumulative DSV value from the adder / subtractor 108 that adds / subtracts DSV2. The comparator 107 outputs “0” as the comparison result, and the adder / subtractor 107 that adds / subtracts DSV1 is the absolute value of the accumulated DSV value from the adder / subtractor 108 that adds / subtracts DSV2.
If the absolute value of the accumulated DSV value is smaller than the absolute value, "1" is output as the comparison result.

The adder circuits 111 and 112 are provided with a DSV / run table 104.
Run1, run2 and 8-16 modulation / Sync code table 106
And the run length at the connection between the modulation code mod data n-1 and the option of the modulation code for the immediately preceding input data n-1 is calculated and output. Comparators 113, 114
Judge whether or not the run lengths from the adders 111 and 112 satisfy the run limit of 8-16 modulation, respectively. That is, if the calculated run length between the codes is 2 or more and 10 or less, the limit is satisfied, so that the determination signal is output as “0”. If the other run length restrictions are not satisfied, The judgment signal is output as "1".

According to the comparison result between the DSV comparator 110 and the comparators 113 and 114, the selection logic circuit 115 determines that the absolute value of the accumulated DSV value is small (the fact that the accumulated DSV value is small means that the modulation code mod This indicates that the DC component of a series of modulation code strings up to data n is small) and the modulation code that satisfies the run limit is selected from the 8-16 modulation / Sync code table 106. Generate and output sel. FIG. 7 shows a truth table of the selection signal mod-sel.

In the figure, from the above, DSV
= 0 indicates a main table of the 8-16 modulation / Sync code table 106, and DSV = 1 indicates 8-16 modulation / Sync.
It shows a sub-table of the code table. Also, run1, run2 = 0 indicates that run1 and run2 satisfy the run limit of 8-16 modulation, and run1, run2 = 1 indicates r
This indicates that un1 and run2 do not satisfy the run limit of 8-16 modulation.

When the value of the select signal mod-sel is “0”, the table address controller 105 to which the select signal mod-sel is supplied selects one of the options (8 if mod data ≦ 87).
The 16 modulation / Sync code table 106 is selected. If the value of the selection signal mod-sel is “1”, two options (mod data ≦ 87, 8-16 modulation / Sync code table 106) are selected. Sub-table).

Here, DSV = run1 = run2 = 0 and DSV =
When run1 = 0 and run2 = 1, the modulation code based on the main table of the 8-16 modulation / Sync code table 106 is more accumulated D
Since the SV value is small and run1 for this modulation code satisfies the run limit, the selection signal mod-sel is set to "0" and
The main table of the -16 modulation / Sync code table 106 is selected. DSV = run2 = 1, run1 = 0
In the case of, the accumulated DSV value is larger for the modulation code based on the main table of the 8-16 modulation / Sync code table 106,
Originally the sub-table is selected, but run2
Does not satisfy the run limit, the selection signal mod-sel is set to "0", and the main table of the 8-16 modulation / Sync code table 106 is selected.

Similarly, DSV = 1, run1 = run2 = 0
When DSV = run1 = 1 and run2 = 0, the accumulated DSV value of the modulation code based on the sub-table of the 8-16 modulation / Sync code table 106 is smaller, and run2 for this modulation code satisfies the run limit. , The selection signal mod-sel is set to “1”, and the sub-table of the 8-16 modulation / Sync code table 106 is selected. DSV = run2 =
When 0 and run1 = 1, the modulation code based on the sub-table of the 8-16 modulation / Sync code table 106 has a larger accumulated DSV value, and originally the main table is selected. Since the condition is not satisfied, the selection signal mod-sel is set to "1" to select a sub-table of the 8-16 modulation / Sync code table 106.

In FIG. 1 and FIG. 2, the selector 116
With this selection signal mod-sel, the cumulative DSV value up to the input data n from the adders / subtractors 108 and 109 is selected, and the input data n + 1
It is stored in the DSV register 117 for use in DSV value calculation.

The table address controller 105
Is the main / sub bit and the state bit of the 8-16 / Sync table address according to the selection signal mod-sel (FIG. 3 (a))
Is generated according to the flowchart shown in FIG.

As described above, the 8-16 / Sync table address of the input data n to be modulated by operating as shown in FIG. 2 is generated, and the DSV / Sync code table 106 is output by the output of the 8-16 modulation / Sync code table 106. Generate the address of the run table 104, D
From the output of the SV / run table 104, DSV calculation and run length limit violation check are performed, a modulation code of the input data n is selected, and this can be output as a modulation code.

Next, the operation for selecting the Sync code will be described.

One Sync frame is formed by 91 bytes of modulation data, and one recording sector is formed by 26 Sync frames. The Sync code is placed at the head of this Sync frame, and the state is determined by the next-state of the last modulation code of the immediately preceding Sync frame. Sy
The nc code has eight code numbers, Sync0 to Sync7,
Each code number is classified into states 1 and 2 and states 3 and 4.
Have code. Type 2 these Sync codes
The type 2 is selected, and the type having a smaller DSV value is selected as the sync code from type 1 and type 2. The code number is determined by the Sync frame number, and the Sync code number is determined by the Sync frame number. Also, Sync
The state of the modulation code following the code is always 1. Sync
Since the size of the code is 32 bits, the code is selected and output according to the flowchart shown in FIG. 9 unlike the modulation code by the 8-16 modulation.

Hereinafter, according to this flowchart, FIG.
The operation of selecting and outputting the Sync code in the embodiment shown in FIG.

First, the 90th input data 90 is latched and held by the latch 101 at the rising edge of the byte clock, and the 89th input data 89 held by the latch 101 is transferred to the latch 102 and held. . Then, as described above, the table address controller 105
To find the modulation code of the input data 89 by 8-16 / Sync
A table address is generated, which allows for 8-16 modulation /
Next-state 89 for the next input data 90 is output from the sync code table 106 together with the modulation code mod 89.

The DSV / run table address is generated by the table address controller 103 based on the next-state 89 and the input data 90, and the corresponding DSV1, 2, or ru is generated.
n1 and n2 are output from the DSV / run table 104, these are processed by the adder / subtractors 107 and 108, the adders 111 and 112, and the DSV comparator 110, and the selection logic circuit 115 modulates the next input data 90 by the selection signal mod. -sel is generated.

At the next rising edge of the byte clock,
The 0th input data 0 of the next Sync frame is stored in the latch 101.
Is held, but in this case, it is necessary to select a Sync code placed at the head of this Sync frame.

Then, the end of the immediately preceding Sync frame is notified to the table address controller 103 by the “H” timing signal Sync-SEL1 output from a timing generator (not shown). As a result, the table address controller 103 sets the DSV / ru shown in FIG.
n At the table address, the timing signal Sync-SEL
Since 1 is "H", the 8-16 / Sync bit is set to "1", and the DSV / run table 104 is used as an address for outputting the DSV of the Sync code.

At this time, the state bit in the DSV / run table address shown in FIG. 4A is output from the 8-16 modulation / Sync code table 106 together with the modulation code mod 90 of the input data 90 in the previous Sync frame. Syn before
Next- by the final modulation code mod90 of the c frame
state 90, the value of which is the timing signal Sync-S
EL1 is held during "H". Also, as shown in FIG.
The 8-bit address data data in the DSV / run table address is a Sync code number corresponding to a Sync frame number output from a timing generator (not shown).

The DSV / run table address generated from the DSV / run table 104 indicates the D of the Sync code.
SV values DSV1,2 are output. In the DSV / run table 104, for the Sync code, DSV1 has a DSV value of type 1
V2 stores the type 2 DSV values.
The V value is processed by the adder / subtractor 107, 108 as described above, and DS
The signals are compared by the V comparator 110, and the type 1 and
A selection signal mod-sel (select-Sy
nc) is generated and output.

At the next rising edge of the byte clock, the latch 101 does not hold new input data because the Sync code is output. However, the input data 0 held in the latch 101 is also latched in the latch 102. As a result, the same input data 0 is input to the latches 101 and 102.
Will be held.

At this timing, an “H” timing signal Sync-SEL 2 output from a timing generator (not shown) and the number of the preceding Sync code and the selection logic circuit 1
With the select signal mod-sel (select-Sync) from 15
The table address controller 105 generates an 8-16 / Sync table address for outputting a Sync code. As a result, the 8-16 modulation / Sync code table 106 outputs the Sync code as the modulation code mod.

Here, the modulation data for the input data n
Although the mod is 16 bits, the Sync code is a 32-bit code, which is divided into upper 16 bits and lower 16 bits and output from the 8-16 modulation / Sync code table 106. Therefore, the least significant bit of the address data data (FIG. 3 (a)) of the 8-16 / Sync table address output from the table address controller 105 indicates upper and lower bits, and the other bits of this address data data are This will be the Sync code number.

Also, 8-16 / 8-16 of the sync table address
The / Sync bit (FIG. 3A) is a timing signal Sync-S
Since EL2 is "H", it becomes "1", and instructs to select the Sync code. state bit (Figure 3
(A)) is the last input data 9 of the immediately preceding Sync frame.
This is the next-state 90 of the modulation code mod 90 of 0, and this value is held during the “H” of the timing signal Sync-SEL2. In addition, since types 1 and 2 are selected by the selection signal mod-sel (select-Sync), the main / sub bits (FIG. 3A) of the 8-16 / Sync table address are set at the time of normal code modulation (ie, , At the time of modulation of the input data n)
The selection code mod-sel is selected, and a Sync code having a small DSV value is selected to select the types 1 and 2 of the Sync code.

According to the generated 8-16 / Sync table address, first, the upper 16 bits of the Sync code are obtained.
State 1 is output from the 8-16 modulation / Sync code table 106 as Sync code data “SyncH” and next-state. At this time, the table address controller 103
Since the timing signal Sync-SEL1 is “H”, the modulation code mod9 of the final input data 90 of the immediately preceding Sync frame
Holds the next-state 90 of 0 and the same DSV / r as the previous time
Output untable address. However, DSV register 1
Because we do not add the DSV value of the Sync code to the cumulative DSV value at 17,
The calculation result of the DSV value at this time becomes the same value as the previous time, and the selection signal mod-sel output from the selection logic circuit 115 is held as it is.

At the next rising edge of the byte clock, 8-1 generated by table address controller 105
In the 6 / Sync table address, the main / sub bit (Fig. 3
The selection signal mod-sel as (a)) is the next-state of the modulation code mod90 of the last input data 90 in the immediately preceding Sync frame as the state bit (FIG. 3A).
90 are held, and only the least significant bit of the address data is changed by a control signal from a timing generator (not shown) so as to indicate the lower 16 bits of the Sync code. As a result, from the 8-16 modulation / Sync code table 106, Sync code data “SyncL” for the lower 16 bits following the upper 16 bits of the previously output Sync code is output.

At this time, the address table controller
Since the timing signal Sync-SEL1 becomes “L”, the input data 103 at the beginning of the Sync frame held in the latch 101 and the state 1 which is the next-state of the Sync code are in the state 103 in the normal code modulation. Generate address.
The DSV values DSV1,2 and the run lengths run1,2 for the input data 0 output from the DSV / run table 104 are subjected to the arithmetic processing as described above, and the selection logic circuit 115 calculates the input following the Sync code from the arithmetic result. A selection signal mod-sel (select-0) for selecting the modulation code mod0 of the data 0 is output.

At the next rising edge of the byte clock, the timing signal Sync-SEL2 becomes "L", so that the operation returns to the normal code modulation operation. The latch 101 latches the next input data 1, and the latch 102 latches the input data 0. Table address controller 105 latches
02 and the select signal mod-sel (s
elect-0), the modulation code mod of the input data 0
Generate 8-16 / Sync table address to get 0. Therefore, modulated data can be output following the Sync code.

As described above, in this embodiment, 8-16 modulation including the Sync code can be performed. In the modulation processing in this embodiment, a large part of the processing time required for selecting a modulation code (selection and generation of state bits and main / sub bits) is the time required for outputting data from the table. Usually, in the case of a ROM, the time is about 100 nsec. Therefore, even if the output delay time from the 8-16 modulation / Sync code table 106 and the DSV / run table 104 is added, the delay time due to this processing is Approximately 200 nsec. Therefore, 1 byte cycle is 544nsec
In the DVD-RAM, all the processing up to the selection of the modulation code can be completed within one byte clock cycle, and the modulation processing speed of the code modulation circuit can be equal to or higher than the byte transfer rate. .

In this embodiment, unnecessary data is recorded in the table, such as run length data in states 2 and 3 of input data having a value of 88 or more. These may be deleted, and the circuit may be changed by changing the logic selection circuit. The odd / even information O / E indicating even / odd of the code “1” included in the modulation data is provided in the 8-16 modulation / Sync code table 106, but EOR (exclusive OR) of all bits of the modulation data is provided. , The same signal can be obtained, so that the odd / even information O / E need not be provided as a table.

In this embodiment, the case of 8-16 modulation has been described. However, the present invention is also applicable to a modulation system in which the next modulation data is selected by a data modulation code similar to 8-16 modulation. Is applied, whereby it is possible to obtain a code modulation circuit that does not need to speed up the operation clock by shortening the modulation processing time.

[0101]

As described above, according to the present invention,
When obtaining a DSV value for selecting a modulation code, a processing time of 16 clocks after NRZI conversion is not necessary, and a DS
Since the DSV value can be obtained from the table in which V is stored, only the access time to the table is required and the DSV
The value can be obtained, and the processing time of the code modulation can be reduced. Therefore, a code modulation circuit can be configured without using a high-speed circuit.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a code modulation circuit according to the present invention.

FIG. 2 is a timing chart showing a code modulation operation of the embodiment shown in FIG.

FIG. 3 is a diagram showing a specific example of addresses and output data of an 8-16 / Sync code table in FIG. 1;

FIG. 4 is a diagram showing a specific example of an address and output data of a DSV / run table in FIG. 1;

FIG. 5 is a diagram illustrating a change in a DSV value according to an initial state of a modulation code.

FIG. 6 is a circuit configuration diagram showing a specific example of an adder-subtractor control circuit in FIG. 1;

FIG. 7 is a truth table showing a selection operation of a selection logic circuit in FIG. 1;

FIG. 8 is a flowchart showing a selection operation of a table address controller of the 8-16 modulation / Sync code table in FIG. 1;

FIG. 9 is a timing chart showing an operation when a Sync code is selected in the embodiment shown in FIG. 1;

FIG. 10 is a flowchart showing an 8-16 modulation processing operation of the conventional code modulation circuit.

11 is a block diagram illustrating an example of a conventional code modulation circuit that performs the processing operation illustrated in FIG.

12 is a timing chart showing a code modulation operation of the code modulation circuit shown in FIG.

13 is a timing chart showing a code modulation operation when the operation clock of the code modulation circuit shown in FIG. 11 is doubled.

[Explanation of symbols]

 101, 102 Latch 103 Table address controller 104 DSV / run table 105 Table address controller 106 8-16 modulation / Sync code table 107, 108 Adder / subtractor 109 Adder / subtractor control circuit 110 DSV comparator 111, 112 Adder 113, 114 Comparator 115 Selection logic circuit 116 Selector 117 DSV register

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuya Ikeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within the Visual Information Media Division of Hitachi, Ltd. JP-A-7-154263 (JP, A) JP-A-62-150568 (JP, A) JP-A-9-162744 (JP, A) JP-A-9 −246979 (JP, A) JP-A-8-31100 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/14

Claims (3)

(57) [Claims] 1. When the original information is code-modulated, a run limit of a state indicated by the modulated code, a numerical value of the original information to be modulated next, a DSV value indicating a degree of DC included in the modulation code, and a previous modulation code. Accordingly, in a code modulation circuit of a code modulation method of selecting from a plurality of modulation codes as a modulation code of the original information to be modulated next, a DSV value of each modulation code is stored in advance, and a plurality of codes corresponding to the input original information are stored. a DSV table for outputting DSV values for the s modulation symbols each, and the run table previously stores run length of each modulation code, and outputs the run length for each of the plurality of modulation codes each corresponding to the raw information input, DSV calculating means for calculating the DSV value of each modulation code output from the DSV table, run length calculating means for calculating the run length output from the run table, DSV calculating means and the run length calculation Performance with means The results, code modulation circuit characterized in that provided the code selecting means for selecting a smaller one of the modulation codes of the absolute value of the DSV satisfying the run conditions, selects a modulation code. 2. A code modulation circuit according to claim 1, wherein the DSV arithmetic control means for controlling the arithmetic processing of the arithmetic means, beginning <br/> Jasmine from the beginning or space from said modulation code mark A code discriminating circuit provided with state discriminating means for discriminating the state of the modulation code, wherein the arithmetic control means is controlled by the state of the modulation code determined by the state discriminating means. 3. The code modulation circuit according to claim 2, further comprising: an odd / even discrimination table in which information indicating whether the number of codes “1” included in the modulation code is even or odd is obtained and stored in advance. A code modulation circuit for controlling the arithmetic control unit by referring to an odd / even discrimination table to determine a state of a start of a modulation code of previous input original information.