JP3345894B2 - Floating point multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating-point multiplier and its multiplication method, and more particularly to a floating-point multiplier using a signed binary multiplier and its multiplication method.

[0002]

2. Description of the Related Art Floating point multiplication requires rounding and digit alignment after addition of an exponent and multiplication of a mantissa.

Conventional floating point multipliers use an array type multiplier or a Wallace type multiplier for multiplication of a mantissa. FIG. 2 shows a configuration example of the latter floating-point multiplier. In FIG. 2, the conventional floating point multiplier includes an exponent part adder 1, a Wallace type multiplier 5, and a logic circuit 6.
And a rounding digit matching device 4. The multiplier 5 includes a Wallace tree 51 and an adder 52.

Next, the operation will be described.

First, the exponent parts E1 and E2 of the floating point extracted in the preprocessing stage are added by the exponent part adder 1.
A mantissa M of n (positive integer) bits of a floating point
1 and M2 are input to a Wallace type multiplier 5 to perform multiplication.
The total OR O of the lower m (m ≦ n) bits N in the output of the multiplier 5 is obtained by the OR circuit 6. The rounding digitizer 4 is
The total OR O is used as a control signal to output the output I of the floating-point multiplier from the output A of the exponent part adder 1 and the upper n bits L of the output of the multiplier 5.

[0006] Assuming that the bit length of the mantissa part of the floating point is n, the multiplier 5 receives two binary numbers having a bit length p (p> n) and outputs a binary number having a bit length (2p-1). Is output. The output of the multiplier 5 required by the rounding digit aligner 4 is truncated to upper q (q> n) bits (2p−1).
-Q) The total logical sum S of bits, that is, a sticky bit. This total logical sum S cannot be obtained until the multiplication is completely completed. Therefore, the total delay time of the conventional floating point multiplier is as follows.

Total delay time = preprocessing + multiplication + calculation of total logical sum S + rounding digit alignment The time for obtaining the total logical sum S has been one of the maximum delay paths in the conventional floating point multiplier.

[0008]

The above-mentioned conventional floating-point multiplier and its multiplication method employ a total OR of truncated lower bits necessary for rounding and digit alignment, that is, a sticky bit in which multiplication is completely performed. Since the calculation cannot be performed until after the calculation, the operation speed of the whole floating point multiplication circuit is low.

[0009]

According to a first aspect of the present invention, there is provided a floating-point multiplier comprising: an exponent part adder which receives exponent parts of first and second floating-point numbers; A signed binary adder tree that receives as input the mantissa of n (positive integer) bits of each floating point number, a subtractor that receives as inputs two outputs of the signed binary adder tree, An OR circuit that inputs the lower m (m ≦ n) bits of two outputs of the signed binary adder tree, and two outputs of the signed binary adder tree and the exponent part adder A rounding and digit matching circuit that receives an output and an output of the OR circuit as inputs and outputs an operation result is configured.

A floating point multiplication method according to a second aspect of the present invention is to add exponent parts of the first and second floating point numbers and to add n to each of the first and second floating point numbers.
The mantissa of (positive integer) bits is multiplied by a multiplier having an adder tree to output a multiplied output. In the floating-point multiplication method for performing a matching process, the numerical value is obtained from an output of the adder tree.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a floating-point multiplier according to the present invention.

As shown in FIG. 1, the floating-point multiplier of this embodiment includes an exponent adder 1, a signed binary multiplier 2, a logic circuit 3, and a rounding digit aligner 4. It is provided with. The multiplier 2 includes a signed binary adder tree 21 and a subtractor 22.

Next, the operation of this embodiment will be described.

First, the exponent parts E1 and E2 of the floating point extracted in the preprocessing stage are added by the exponent part adder 1.
A mantissa M of n (positive integer) bits of a floating point
1 and M2 are input to a signed binary multiplier 2 for multiplication. The OR circuit 3 calculates the total OR H of the outputs D and F of the lower approximately n bits of the output B and the output of the signed binary adder tree 21, respectively. Rounding digit matching device 4
Outputs the output I of the floating-point multiplier from the output A of the exponent adder 1 and the upper bit G of the output of the multiplier 2 using the total OR H as a control signal.

As described above, the floating-point multiplier of the present invention uses the signed binary-type multiplier 2 having the same operation speed as the Wallace-type multiplier as the multiplier, so that it is constituted. The total logical sum S of the truncated bits can be obtained from the output of the signed binary adder. This allows
The delay time of the entire floating point multiplier is as follows.

Total delay time = preprocessing + multiplication + rounding digit alignment Therefore, the time required for calculating the total logical sum S can be reduced as compared with the above-described conventional example.

[0018]

As described above, the floating-point multiplier of the present invention and its multiplication method are provided with a signed binary adder tree and a subtractor having two outputs of the signed binary adder tree as inputs. And a logical sum circuit that receives the lower bits of each of the two outputs of the signed binary adder tree as inputs, so that the total logical sum of the truncated lower bits required for the rounding process and the digit alignment process, that is, Since the sticky bit can be generated even if the multiplication is not completely completed, the operation speed of the entire floating-point multiplication circuit can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a floating-point multiplier of the present invention.

FIG. 2 is a block diagram showing an example of a conventional floating-point multiplier and its multiplication method.

[Explanation of Signs] 1 Exponent part adder 2, 5 Multiplier 3, 6 Logic circuit 4 Rounding digit aligner 21 Signed binary adder tree 22 Subtractor 51 Wallace tree 52 Adder

Claims (1)

(57) [Claims] An exponent adder that receives an exponent of each of the first and second floating point numbers; and an n (positive integer) bit of each of the first and second floating point numbers. A signed binary adder tree having a mantissa as an input; a subtractor having two outputs of the signed binary adder tree as inputs; and two lower outputs of the two outputs of the signed binary adder tree. an OR circuit having m (m ≦ n) bits as input; an output of the signed binary adder tree, an output of the exponent adder, and an output of the OR circuit, and calculating an operation result. A floating point multiplier comprising a rounding and digit matching circuit for outputting.