JP3343160B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device. More specifically, the present invention relates to a structure of a thin film transistor integrated and formed as an active element.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter, referred to as TFTs) have been actively developed in recent years because they can be applied to active matrix type liquid crystal display devices and contact image sensors. In particular, polycrystalline silicon (hereinafter, referred to as poly-Si) as a thin film material is made of TFTs forming a peripheral driving circuit in addition to TFTs forming a display portion and a sensor portion.
Attention has been paid to the fact that FTs can be integrated and formed on the same substrate.

Conventionally, various structures have been proposed for a TFT used as a switching element for turning on / off a pixel of an active matrix type liquid crystal display device, particularly in order to suppress a leak current which causes a pixel bright spot defect. Has been put to practical use. For example, as disclosed in Japanese Patent Publication No. 3-38755, LDD (LightlyD
opto drain (hereinafter referred to as LDD T)
FT). This LDD TFT
Has a low concentration impurity region thinner than the drain region between the channel region and the end of the drain region. This LD
The D structure can reduce the electric field concentration at the end of the drain region and has the effect of suppressing the leakage current as in the case of the offset gate structure.

To clarify the background of the present invention, FIG.
, A conventional LDD structure will be described briefly. On the surface of the quartz substrate 1, pol
A y-Si film is formed. In the poly-Si film, a channel region 2 and a source region 3 and a drain region 5 on both sides thereof are formed. The low concentration impurity region or LDD region 6 described above is interposed at both ends of the channel region 2. Gate oxide film 7 and gate nitride film 8
The gate electrode 9 is patterned through the TF
Construct T. A first interlayer insulating film 10 is formed on the TFT. Further, a wiring electrode 11 is formed thereon by patterning, and is electrically connected to the source region 3 via a contact hole. Further, the second interlayer insulating film 12
, The pixel electrode 13 is patterned and similarly connected to the drain region 5 through the contact hole.

As another method for reducing the leak current of a TFT, a TFT having a so-called multi-gate structure provided with two or more gate electrodes has been conventionally known. For example, Japanese Patent Application Laid-Open No. 58-171860 and 58-1800
No. 63 and the like. In order to facilitate understanding of the present invention, a TFT having a multi-gate structure will be briefly described with reference to FIG. On the surface of the quartz substrate 1, a poly-Si film patterned in a predetermined shape is formed. A pair of channel regions 2 separated from each other are formed in the poly-Si film, and both are connected to each other by a connection region 4. Since the connection region 4 includes a source region belonging to one TFT and a drain region belonging to the other TFT, it may be referred to as a source / drain region 4 in the following description in some cases. A source region 3 is formed at an end of one channel region 2, and a drain region 5 is formed at an end of the other channel region 2. Further, a pair of gate electrodes 9 patterned into a predetermined shape via the gate oxide film 7 are respectively formed in the channel region 2.
Is provided in conformity with. The wiring electrode 11 is patterned through the first interlayer insulating film 10 and is electrically connected to the source region 3. Further, the second interlayer insulating film 1
The pixel electrode 13 is formed in a pattern via 2 and is also electrically connected to the drain region 5 via a contact hole. This multi-gate TFT has an equivalent circuit configuration in which a plurality of TFTs are connected in series. Since the leak current depends on the TFT having the lowest off-current value among a plurality of TFTs, the leak current can be suppressed, and is also applied to a pixel switching element of an active matrix type liquid crystal display device.

FIG. 14 is an equivalent circuit diagram showing one pixel of an active matrix type liquid crystal display device employing a multi-gate TFT. The switching element is composed of a series connection of TFT1 to TFTn, and each gate electrode is commonly connected to a gate line.
The end of the source region of TFT1 is connected to the signal line, while the end of the drain region of TFTn drives the liquid crystal via the pixel electrode. Note that an auxiliary capacitor is also connected in parallel with the liquid crystal.

[0007]

SUMMARY OF THE INVENTION Conventional LDD TFT
In the structure, the impurity dose of the LDD region is 1 × 10 ¹² to
Since it is about 1 × 10 ¹³ / cm ² , when impurity ions are implanted into the poly-Si film, the specific resistance value of the poly-Si film greatly varies due to a slight change in the dose. Therefore, the LDD resistance tends to fluctuate, and the LDD
This causes variation in the leak current of the TFT.
In a TFT having a high leak current, the leak current increases exponentially with respect to the temperature particularly when the ambient temperature is set to a high temperature (for example, 50 to 80 ° C.). There was a problem that appeared. or,
There is a problem that the threshold voltage (Vth) of the TFT varies because the activation rate of the impurity ions in the active region varies due to a slight difference in the crystallinity of the poly-Si film used as the active region of the TFT. Furthermore, since there is variation in the capacitance coupling between the gate capacitance and the auxiliary capacitance of the TFT, a thin streak-like bright line defect may appear on the screen of the active matrix type liquid crystal display device, which is a problem to be solved. I have. The bright line defect due to the capacitive coupling becomes remarkable particularly when a signal charge is written to the pixel electrode in a state where the drain voltage is relatively low.

On the other hand, in a conventional TFT having a multi-gate structure, impurities doped in a source region and a drain region have horizontal diffusion. For example, in an n-channel TFT doped with P ⁺ ions, the channel length must be 5 μm or less. There was a problem that can not be. When the channel length is shortened, the effective channel length is shortened due to horizontal diffusion of impurities, and the leakage current is extremely increased. For this reason, it is difficult to miniaturize the TFT with the conventional multi-gate structure,
This has been an obstacle to high definition of the active matrix type liquid crystal display device. In addition, high-temperature bright spot defects also occur frequently in the conventional multi-gate structure as in the LDD structure.

In addition, even if the TFT has an LDD structure, the occurrence of point defect pixels due to the leakage of the thin film transistor during the holding period of the signal charge cannot be completely suppressed. In particular, high temperature (for example, 55 ° C.) at which the leak level becomes large as a whole
In this case, many point-defective pixels leading to the blinking state occur frequently. Therefore, when the analysis was attempted, it was found that the point defect of the pixel was related to the AC driving of the liquid crystal, and that a leak current was generated between the source and the drain depending on the polarity of the applied voltage. Specifically, a high electric field is continuously applied between the gate electrode and the pixel electrode during the holding period of the positive signal charge, so that the leak current flowing through the localized level causes the negative signal charge to flow. Is much longer than the holding period, and the high potential image signal level cannot be sufficiently held during the positive holding period. As a result, the balance of the AC driving for the liquid crystal is lost, and the number of flickering point defective pixels is increased. is there.

[0010] Problems of the prior art from a further viewpoint will be briefly described. If the number of pixels increases remarkably as the size and resolution of the active matrix type liquid crystal display device increase, the decrease in yield due to pixel defects becomes a serious problem in manufacturing cost as described above. As one of the measures, a redundant configuration has been conventionally employed. The redundant configuration is generally regarded as a structure that is originally unnecessary but is unavoidably introduced for the purpose of repairing defects or improving reliability. For example, published by Nikkei BP “Flat Panel Display 199
1 "p. 105-108, p. As shown in 201 and the like, as a remedy for a pixel defect caused by a TFT used as a pixel driving switching element, a redundant configuration in which a plurality of switching elements are provided for one pixel or a spare switching element is provided is provided. Conventionally known. However, as described above, these conventional methods are unavoidably adopted in order to secure an initial manufacturing yield to some extent, and increase the number of manufacturing processes, disconnection failure of wiring, There are many secondary disadvantages associated with complicated connection processes and complicated peripheral drive circuits.

[0011]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention has a small leak current, easy control of the threshold voltage characteristic, is free from adverse effects of gate capacitance coupling, and is stable. T for active matrix type liquid crystal display device capable of miniaturization that can perform AC driving
A first object is to provide an FT structure. In order to achieve the first object, the following measures were taken. That is, the liquid crystal display device according to the present invention includes, as basic components, one substrate including pixel electrodes arranged in a matrix and a switching element for driving the pixel electrodes, and a counter electrode. And a liquid crystal layer held on both substrates. As a feature of the present invention, the switching element has a multi-gate structure in which a plurality of thin film transistors are connected in series by a connection region serving also as each source / drain region, and each gate electrode is electrically connected to each other. Further, each thin film transistor forming the multi-gate structure has an LDD structure including a low-concentration impurity region of the same conductivity type as at least the source or drain region between the source or drain region and the channel region. And the connection area
The region is the same as the source region and the drain region,
The impurity concentration is higher than the pure region.

Preferably, each thin film transistor has a low concentration impurity region between both the source region and the drain region and the channel region. Preferably, the switching element comprises a pair of thin film transistors connected in series, one having a low concentration impurity region only between the source region and the channel region, and the other having a low concentration impurity only between the drain region and the channel region. A symmetric structure having an impurity region may be employed. More preferably, each thin film transistor has a channel length of 5 μm or less.

Particularly, in order to stabilize the AC driving of the liquid crystal, at least one of the plurality of low-concentration impurity regions provided in the plurality of thin-film transistors has a length different from that of the other low-concentration impurity regions. I made it. Specifically, the low concentration impurity region closest to the pixel electrode is made longer than the other low concentration impurity regions. Alternatively, at least one of the plurality of low-concentration impurity regions provided in the plurality of thin film transistors may have a different concentration from the other low-concentration impurity regions. Specifically, the low concentration impurity region closest to the pixel electrode has a lower concentration than other low concentration impurity regions.

A second object of the present invention is to provide switching elements themselves with redundancy without using a plurality of switching elements for one pixel, resulting in complicated wiring and peripheral driving circuits. To improve manufacturing yield and reliability without any problems. In order to achieve the second object, the following measures were taken. That is, for pixels arranged in a matrix
Electrodes and a switching element for driving the electrodes.
In the display substrate described above, the switching element basically has a multi-gate structure consisting of a plurality of thin film transistors and connecting the respective gate electrodes in common. As a feature, each thin film transistor is a low concentration impurity region L
It has an LDD type leakage current suppressing structure having a DD region, and at least two thin film transistors are connected in series by a connection region also serving as a source / drain region, and the connection region is connected to a source region and a drain region. Similarly, the impurity concentration is higher than that of the low-concentration impurity region to provide redundancy against a current leak failure. In this case, L
The DD thin film transistor has an LDD region of the same conductivity type as the impurity region and a lower concentration between at least the impurity region functioning as a drain and the channel region. The LDD type thin film transistor has an impurity region functioning as a drain alternately on both sides of the channel region and an associated LDD region.

[0015]

According to the first aspect of the present invention, a gate electrode of a TFT for a pixel switching element has a multi-gate structure and an LDD structure. By combining both structures, a remarkable synergistic effect is obtained in which the advantages of each are utilized and the disadvantages are eliminated. That is, the leakage current can be suppressed low, the variation in the threshold voltage (Vth) and the coupling of the gate capacitance can be reduced, and the channel length can be shortened. In particular, in a pixel switching element TFT combining a multi-gate structure and an LDD structure,
By making the length or concentration of the low-concentration impurity region (LDD region) close to the pixel electrode different from that of the remaining low-concentration impurity regions, the concentration of the electric field in the channel region during the period during which the pixel potential is kept positive can be suppressed. The leakage current via the localized level is suppressed. Further, a high drive current or an on-state current can be obtained while keeping the leak current low, which greatly contributes to the high performance of the active matrix type liquid crystal display device. Further, since the degree of freedom in TFT design is increased, it is possible to contribute to improvement of the aperture ratio of the liquid crystal display device.

According to the second aspect of the present invention, two or more thin film transistors having a leakage current suppressing structure are connected in series to form a multi-gate structure, and the switching element itself is provided with redundancy against a current leakage failure. In other words, at least two of the plurality of thin film transistors
In the case of the TFT, the leak current is so small that the TFT alone does not cause a pixel defect. Therefore, even if one TFT suffers a current leakage failure in the manufacturing process or in actual use, the remaining TFTs act complementarily and can normally operate as the switching element itself. As described above, since the single switching element itself has redundancy, it is possible to dramatically improve the manufacturing yield and reliability as compared with the related art without causing complicated wiring and peripheral driving circuits. .

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a first embodiment of an active matrix type liquid crystal display device according to the present invention, and is a partial cross-sectional view in which the vicinity of a TFT, which is a main part, is enlarged. The illustrated TFT is an n-channel type and constitutes a pixel driving switching element of an active matrix type liquid crystal display device. On an insulating substrate such as a quartz substrate 1, a patterned polycrystalline semiconductor layer such as a poly-Si film is formed. This film has a source region 3 and a source /
A drain region (connection region) 4, a drain region 5, and a pair of channel regions 2 located between the three are formed. Between the source region 3, the source / drain region 4 and the drain region 5, and each channel region 2, a total of four low-concentration impurity regions, ie, LDD regions 6, having the same conductivity type as the source region and the drain region, respectively, are formed. I have. Above each channel region 2, a corresponding gate electrode 9 is formed via a gate insulating film. This gate insulating film has a two-layer structure, and includes a gate oxide film 7 and a gate nitride film 8. The quartz substrate 1 is covered with a first interlayer insulating film 10 made of PSG or the like. A wiring electrode 11 made of aluminum or the like is electrically connected to the source region 3 via a contact hole formed in the first interlayer insulating film 10. Similarly, a pixel electrode 13 made of a transparent conductive material such as ITO is electrically connected to the drain region 5 via a contact hole. The pixel electrode 13 is formed on the second interlayer insulating film 12 made of PSG or the like.

Still referring to FIG. 1, the functional advantages of the present invention will be described in detail. First, the leak current suppressing function will be described. In general, a poly-Si film serving as an active region of a TFT has a higher defect density than single crystal silicon, and thus tends to increase leakage current. For this reason, a hydrogen diffusion process is usually performed to reduce the defect density,
The leakage current of T is reduced. As the hydrogenation proceeds, the defect level of poly-Si decreases, and the energy barrier at the crystal grain boundary decreases, so that the LDD resistance decreases. LD
Since the D resistance greatly depends on the degree of hydrogenation, the LDD resistance of each TFT in a wafer greatly varies depending on the state of hydrogenation. As a result, an abnormal TFT with a large leak current has appeared with a conventional statistical probability. On the other hand, in the multi-gate LDD TFT of the present invention, the effective value of the leak current is determined by the TFT having the smallest off-state current among a plurality of TFTs connected in series in an equivalent circuit. For this reason, the variation in the leak current due to the difference in the degree of hydrogenation was drastically reduced.

Next, the function of stabilizing the threshold voltage will be described. The degree of hydrogenation affects not only the leak current but also the threshold voltage Vth of the TFT. If hydrogenation proceeds excessively, T
The Vth of the FT decreases, and current flows even when the gate is off. For this reason, in the conventional TFT, a pixel defect called a so-called Vth luminescent spot occurs, which has been a problem. On the other hand, in the multi-gate LDD TFT of the present invention, the value of Vth is determined by the TFT having the highest Vth among a plurality of TFTs connected in series. As a result, Vth
And the Vth luminescent spot defect was drastically reduced.

Next, a conventional single gate structure LDD TFT
As a result, the variation of the gate capacitance coupling, which has been a problem, could be improved. In the multi-gate LDD TFT of the present invention, the variation in gate capacitance among the TFT groups is smaller than the variation in gate capacitance of a single TFT, so that the degree of bright line defects is reduced as compared with the conventional single-gate LDD TFT. I was able to do it.

Further, the shortening of the channel length will be described. Conventional multi-gate structure T without LDD region
In the FT, since the impurity diffused in the source region and the drain region is largely diffused in the horizontal direction, when the poly-Si film is used as the active region, the set channel length is 5 μm.
If m is set, the effective channel length becomes 3 μm or less. For this reason, the electric field concentration at the end of the drain region increases, and the leak current increases. Therefore, it is disadvantageous for high definition and high aperture ratio of the active matrix type liquid crystal display device. In contrast, the multi-gate structure L of the present invention
In the case of the DD TFT, by providing the LDD region, the electric field concentration at the end of the drain region can be reduced, so that the set channel length can be reduced to 5 μm or less. That is, according to the present invention, it is possible to increase the definition and the aperture ratio of the active matrix type liquid crystal display device.

In order to more clearly show the advantages of the present invention described above, FIG. 9 shows a multi-gate structure LDD according to the present invention.
3 shows a gate voltage versus drain current curve of a TFT. or,
For comparison, FIG. 10 shows a gate voltage versus drain current curve of a conventional multi-gate TFT. The total channel length of the double gate TFT sample measured was 3
μm + 3 μm, and the channel width is 3 μm. or,
The source / drain voltage was set to 5V and the source / gate voltage was changed from -10 to + 15V. In the conventional multi-gate TFT without LDD, the leak current greatly increases and the TFT characteristics show a depletion type curve, whereas in the multi-gate LDD TFT of the present invention, no increase in the leak current is observed.

Next, the multi-gate structure LD shown in FIG.
A modified example of the D TFT will be described. In general, in an active matrix type liquid crystal display device, the liquid crystal layer is driven by an alternating current in order to suppress the life degradation. For this reason, since the source side and the drain side are alternately replaced, the LDD region is preferably provided symmetrically with respect to the source end and the drain end. In the example of FIG. 1 described above, two TFTs are connected in series. Of course, the number of TFTs may be three or more.
Since the source side and the drain side are alternately switched in order to drive the liquid crystal by alternating current, it is preferable that the structure and the positional relationship of the LDD are symmetric with respect to the source region and the drain region. That is, it is preferable that the source region and the drain region can be exchanged equivalently. Therefore, in the embodiment of FIG.
Four D regions are provided in contact with the end surfaces of the respective gate electrodes. However, the arrangement of the LDD regions is not limited to the embodiment shown in FIG. T for pixel switching element
In the case of FT, it suffices if the symmetry of the source / drain is maintained. Therefore, for example, as shown in FIG. 2, the LDD region 6 is provided only at the end of the source region 3 and the end of the drain region 5.
May be provided. Alternatively, as shown in FIG. 3, the LDD regions 6 may be provided only at two positions on both ends of the inner source / drain region 4. In order to facilitate understanding, the same reference numerals are given to the same parts as those of the embodiment shown in FIG. 1 in the embodiments of FIGS. 2 and 3.

The multi-gate structure LDD according to the present invention
The TFT can be used not only for a pixel switching element but also for a peripheral circuit formed simultaneously on the same substrate, for example, a horizontal drive circuit or a vertical drive circuit. This example is shown in FIG. To facilitate understanding, parts corresponding to the structure shown in FIG. 1 are denoted by corresponding reference numerals.
Generally, in the case of a TFT incorporated in a peripheral circuit, the direction on the drain side is determined in advance, unlike a switching element. Therefore, as shown in FIG. 4, only the end of the drain region 5 and the end of the source / drain region 4 on the drain side are L
The DD region 6 is provided so that no LDD region is formed at the end of the source region 3 or the end of the source / drain region 4 on the source side. As described above, by partially omitting the LDD region, the ON current of the TFT is increased and the driving capability is improved.

Next, with reference to FIGS. 5 to 8, the manufacturing process of the multi-gate LDD-TFT according to the present invention will be described in detail. First, in step A of FIG.
A poly-Si thin film 102 having a thickness of about 75 nm is formed on 01 by LPCVD. If necessary, pol by ion implantation of Si ⁺ ions.
The y-Si thin film 102 is made amorphous, and then is subjected to furnace annealing at a temperature of about 600 ° C. to increase the grain size of the polycrystalline silicon. When amorphous silicon is to be formed in advance, a plasma chemical vapor deposition (PCVD) method is used.
The film may be formed at a temperature of about 0 to 250 ° C. Next, step B
Then, the poly-Si thin film 102 is etched into a predetermined pattern. Subsequently, the poly-Si thin film 102 is oxidized to form a gate oxide film 103 on the surface thereof with a thickness of about 60 nm. Then, in step C, B ⁺ ions are implanted for adjusting the TFT threshold voltage.

In step D of FIG. 6, the gate oxide film 10
3 on the silicon nitride film (Si ₃ N) by LPCVD.
₄ ) is formed with a thickness of about 10 to 20 nm. In some cases, the surface of the silicon nitride film 104 is oxidized,
An SiO ₂ film is formed with a thickness of about 1-2 nm. The composite gate insulating film obtained in this manner is SiO ₂ / Si ₃ N ₄
It is called an ONO structure because it has a three-layer structure of / SiO ₂ . Such a structure ensures sufficient gate breakdown voltage,
This is to improve reliability. Subsequently, in step E,
After a phosphorus-doped low-resistance polycrystalline silicon film is formed on the gate insulating film to a thickness of about 350 nm, it is patterned into a predetermined shape to obtain a pair of gate electrodes 105. There are the following three methods for forming the gate electrode. The first method is to form a non-doped polycrystalline silicon thin film and diffuse phosphorus from PCO ₃ gas. The second method is PCl
Phosphorus diffusion is performed using a PSG film instead of O ₃ gas. A third method is to thermally decompose a gas mixture of SiH ₄ gas and PH ₃ gas by LPCVD doped poly-
This is for forming a Si film. Although any method may be used, the first method is employed in this embodiment. In this example, the channel length L of each TFT was set to 3 μm, and the gate electrode was patterned so that the channel width W became 3 μm.
Next, the process proceeds to a step F of forming an LDD region. In order to form an LDD region, in the case of an n-channel TFT, after forming the gate electrode 105, As ⁺ or P ⁺
The implantation is performed at a dose of 1.5 × 10 ¹³ / cm ² . In the case of a p-channel TFT, B ⁺ ions may be similarly implanted at a dose of 0.1 to 2.0 × 10 ¹³ / cm ² instead of As ⁺ or P ⁺ ions. Next, in step G, Si ₃ N
_{The four} films 104 are cut into a predetermined shape along the periphery of the gate electrode 105.

In step H of FIG. 7, the gate electrode 105
Is formed so as to leave a 1 μm range as the LDD region 106 from both sides of the resist 107. Subsequently, a source region and a drain region are formed by implanting impurity ions at a dose of 1 to 3 × 10 ¹⁵ / cm ² . In the case of an n-channel TFT, As ⁺ or P ⁺ ions are used, and a p-channel TF
In the case of T, B ⁺ ions are implanted. LDD region 106
Is not limited to 1 μm, but TFTs for pixel switching elements, for which there is a strict requirement for leakage current reduction
Then, the LDD length is desirably 0.5 μm or more. In the subsequent step I, a first interlayer insulating film 108 made of PSG is formed to a thickness of about 600 nm by LPCVD,
The source region, the drain region and the LDD region are activated by annealing in a nitrogen atmosphere at 00 ° C. for 10 minutes. Subsequently, in step J, a contact hole 109 is formed at a predetermined position of the first interlayer insulating film 108.

In step K of FIG. 8, metal aluminum serving as the wiring electrode 110 is deposited to a thickness of about 600 nm and patterned. A second interlayer insulating film 111 made of PSG is further formed thereon with a thickness of about 400 nm. Next, in step L, a silicon nitride film (P-SiN
x film) 112 is formed with a thickness of about 100 nm. This P-
Since the SiNx film 112 contains a large amount of hydrogen, the TFT can be effectively hydrogenated by annealing after the film formation. By hydrogenation, the defect density of the poly-Si film 102 can be reduced, and the leakage current of the TFT due to the defect can be suppressed. Finally, in step M, P-SiN
After the x film is entirely removed by etching and a contact hole is opened, a transparent conductive film such as ITO is formed with a thickness of about 150 nm. This ITO film is patterned into a predetermined shape to obtain the pixel electrode 113.

In the above-described embodiment, each TFT
The channel length is set to 3 μm, the channel width is set to 3 μm, and the LDD length is set to 1 μm. Of course, the dimensions of the TFT are not limited to this. or,
In the above-described embodiment, the gate electrode of the TFT is made of polycrystalline silicon, the gate insulating film has a multilayer structure, and the wiring electrode uses metal aluminum. However, the present invention is not limited to this. . The gate electrode is made of, for example, silicide, polycide, Ta, Al, Cr, Mo,
A metal such as Ni or an alloy thereof can also be used. In addition, it is needless to say that the present invention can be applied to any of a planar type, a forward stagger type, and a reverse stagger type as a TFT.

Next, with reference to FIG. 11, a description will be given of an example of the configuration of an active matrix type liquid crystal display device using the multi-gate LDD TFT according to the present invention.
This device comprises an active matrix substrate 21 and a counter substrate 2
2 is bonded by a spacer 23, and a liquid crystal layer is filled between the two substrates. On the surface of the active matrix substrate 21, a liquid crystal display section 26 including pixel electrodes 24 arranged in a matrix and a switching element 25 for driving the pixel electrodes 24;
6 and a peripheral drive circuit 27 connected to the peripheral drive circuit 27. The switching element 25 has a multi-gate structure LDD
It consists of a TFT. In some cases, the peripheral driving circuit 27
The TFT constituting this may also have this structure. On the other hand, a counter electrode is formed on the inner surface of the counter substrate 22.

Next, a description will be given of a second embodiment of the active matrix type liquid crystal display device according to the present invention. The present embodiment particularly relates to a structure for preventing an increase in leakage current of a TFT caused by AC driving. Prior to the description of the second embodiment, the current leakage phenomenon of the TFT depending on the polarity during AC driving will be briefly described with reference to FIG. In the active matrix type liquid crystal display device is generally the potential of the pixel electrode with respect to the potential V _COM of the common electrode is held with a positive polarity charge, and repeatedly holding the negative polarity charge, TFT's and the pixel electrode side input signal line side Both are sources and drains. It was found that the magnitude of the leak current between the source and the drain was different between the positive polarity holding and the negative polarity holding. Regarding the potential difference between the pixel electrode and the gate electrode of the TFT, a high signal voltage V
_{Since H} is written, a large potential difference occurs between the gate voltage V _GOFF and the OFF state throughout the holding time. On the other hand, if a negative polarity hold, because the voltage V _L of the inverted polarity near the gate voltage V _GOFF in the OFF state is written, the potential difference between the gate electrode is small. In other words, it means that a high electric field is continuously applied between the gate electrode and the pixel electrode only while the positive polarity is maintained. Further, even if the TFT is symmetrical on the pixel electrode side and the signal line side structurally, due to the manufacturing process,
The pixel electrode side of the TFT is more easily damaged than the signal line side. For this reason, the leak current flowing through the defect level in the poly-Si film is much larger in the case of the positive polarity than in the case of the negative polarity, and the written pixel potential cannot be sufficiently maintained, resulting in a bright spot defect. It appears. As a countermeasure, if the TFT is structurally asymmetric in order to further suppress the leak current on the pixel electrode side, the degree of freedom in designing the TFT for pixel switching is reduced, so that the aperture ratio of the liquid crystal pixel has to be sacrificed. There has been a problem that a sufficient ON current of the TFT cannot be secured, and insufficient writing of the pixel potential occurs. The second embodiment described below solves the above problems, and aims at simultaneously achieving a high on-current and a low leakage current of a TFT without sacrificing the degree of freedom of TFT design.

FIG. 16 shows such a second embodiment.
FIG. 2 is a partial cross-sectional view showing, in particular, an enlarged view of a periphery of a TFT serving as a main part. The illustrated TFT is an n-channel type and constitutes a pixel driving switching element of an active matrix type liquid crystal display device. On the quartz substrate 1, a patterned poly-Si film is formed. This film includes a source region 3, a source / drain region (connection region) 4,
A drain region 5 and a pair of channel regions 2 located between the three are formed. Between the source region 3, the source / drain region 4, the drain region 5, and each channel region 2, a total of four low-concentration impurity regions of the same conductivity type as the source region and the drain region, that is, LDD regions 61 to 64 are formed. Have been. Above each channel region 2, a corresponding gate electrode 9 is formed via a gate insulating film. This gate insulating film has a two-layer structure and includes a gate oxide film 7 and a gate nitride film 8. The quartz substrate 1 is covered with a first interlayer insulating film 10 made of PSG or the like. A wiring electrode 11 made of aluminum or the like is electrically connected to the source region 3 via a contact hole formed in the first interlayer insulating film 10. Similarly, a pixel electrode 13 made of ITO is electrically connected to the drain region 5 via a contact hole. This pixel electrode 13 is formed on the second interlayer insulating film 12.

A feature of this embodiment is that a plurality of TFTs
At least one of the plurality of LDD regions provided has a different length from other LDD regions. That is,
The length of each of the first and second LDD regions 61 and 62 is 1 μm.
m, the length of the third LDD region 63 was 0.5 μm, and the length of the fourth LDD region 64 was 1.5 μm. 4th LD
The length of the D region 64 is set to 1.5 μm in order to suppress the leak current on the pixel electrode side. The reason why the length of the third LDD region 63 is set to 0.5 μm is to compensate for a drop in on-current caused by making the fourth LDD region 64 longer than the other LDD regions, and to secure a sufficiently high write current. That's why. Even if the length of the third LDD region 63 is reduced to 0.5 μm, there is no fear that the leak current increases. As described above, the analysis reveals that the highest electric field is applied to the fourth LDD region 64 when the positive potential is maintained on the pixel electrode side.

FIG. 17 is a graph showing a gate voltage / drain current curve of an n-channel LDD TFT. The solid line shows the characteristic curve of the TFT according to the second embodiment described above, and the dotted line shows the characteristic curve of the conventional TFT. This conventional example is a single-gate LDD TFT having a channel length L of 5 μm and a channel width W of 3 μm, and an LDD length of 1 μm.
m, LDD concentration is 1 × 10 ¹³ cm ⁻² . In each case, the measurement was performed under the condition that the pixel electrode side was a drain. The drain voltage is 10V. As is clear from the figure, the second
It can be seen that the TFT according to the example has very excellent characteristics in which the leak current is lower by one digit and the on-current is more than twice as large as the conventional TFT.

Next, the manufacturing process of the above-described second embodiment will be described with reference to FIGS. First, quartz substrate 2
And a poly-Si film 202 is formed on LP for about 7
The film is formed with a thickness of 5 nm. If necessary, thereafter, Si ⁺ ions are ion-implanted to be amorphous, and then the furnace is annealed at a temperature of about 600 ° C. to increase the poly-Si particle size. When an amorphous silicon film is formed from the beginning, the PCVD method is used to form the amorphous silicon.
You may form at the temperature of about 0-250 degreeC. The poly-Si film having a large grain size is etched into a pattern corresponding to the TFT. Subsequently, the poly-Si film 20
2 is oxidized to form a gate oxide film 203 with a thickness of about 60 nm. S is formed on the gate oxide film 203 by LPCVD.
i ₃ N ₄ film 204 is about 10~20nm deposition. In some cases, the Si ₃ N ₄ film 204 is oxidized and the SiO ₂ film is
To 2 nm. The thus formed gate insulating film has a three-layer structure of SiO ₂ / Si ₃ N ₄ / SiO ₂ ,
It is called NO structure. Such a structure is used to ensure a sufficient gate breakdown voltage and improve reliability. Thereafter, in order to control the threshold voltage Vth of the TFT, if necessary, B ⁺ ions are implanted at a dose of about 1 to 8 × 10 ¹² cm ⁻² . On the gate insulating film, phosphorus-doped low-resistance polycrystalline silicon is formed to a thickness of about 350 nm to form a gate electrode 205.
There are three methods for forming the gate electrode. The first method is
This is a method of forming a non-doped polycrystalline silicon thin film and diffusing phosphorus from a PCO ₃ gas. The second method is PCl
This is a method of performing phosphorus diffusion using a PSG film instead of the O ₃ gas. In the third method, a mixed gas of SiH ₄ gas and PH ₃ gas is thermally decomposed by LPCVD and doped poly-S
This is a method of forming i. Although any method may be used, the first method is employed in this embodiment. In this example, the channel length L of the double gate TFT was set to 2.5 μm, and the channel width W was set to 3 μm. Then LD
The process proceeds to the step of forming the D region 206. In order to form an LDD region, in the case of an n-channel TFT, after forming the gate electrode 205, As ⁺ or P ⁺ ions are added at 0.5 to 1.5 × 10 ¹³ /
Drive in at a dose of cm ² . In the case of a p-channel TFT, B ⁺ ions are used instead of As ⁺ or P ⁺ ions in an amount of 0.1 to
It may be similarly implanted with a dose of 2.0 × 10 ¹³ / cm ² . Thereafter, Si ₃ N is formed along the periphery of the gate electrode 205.
_{4 The} film 204 is cut into a predetermined shape.

Next, the procedure moves to the step of FIG. Gate electrode 20
A resist 207 is formed so as to leave a fixed length as an LDD region from both side surfaces of No. 5. In order to form an n-channel TFT, As ⁺ or P ⁺ ions are implanted at a dose of 1 to 3 × 10 ¹⁵ / cm ² to provide a source region and a drain region. When forming a p-channel TFT, B ⁺ ions are implanted. By appropriately setting the patterning shape of the resist 207, LDD regions each having a desired length are left. As described above, the first LDD region 208 and the second LD
The length of the DD region 209 is 1 μm, and the third LDD region 210
Is 0.5 μm, and the length of the fourth LDD region 211 is 1.5 μm. Thereafter, a first PSG film 212 is formed to a thickness of about 600 nm by LPCVD, and N ₂ annealing is performed at 1000 ° C. for 10 minutes to form a source region, a drain region,
Activate the LDD region. Then contact hole 2
13 is opened in the first PSG film 212.

Finally, the process proceeds to the step shown in FIG. Wiring electrode 21
Aluminum having a thickness of 4 is formed to a thickness of about 600 nm and patterned. A second PSG film 215 is further formed thereon to a thickness of about 400 nm. Subsequently, a silicon nitride film (P-Si
An _Nx film 216 is formed to a thickness of about 100 nm. Since the P-SiN _x film contains a large amount of hydrogen, the TFT can be effectively hydrogenated by annealing after the film formation. Po by hydrogenation
The defect density of the ly-Si film is reduced, and T
The leakage current of the FT can be reduced. Finally, P-Si
After the _Nx film is removed by etching, a contact hole is opened to form an ITO thin film of about 150 nm. This ITO thin film is patterned into a predetermined shape to form a pixel electrode 217.

FIG. 21 is a schematic sectional view showing a third embodiment of the active matrix type liquid crystal display device according to the present invention. Basically, it has the same structure as that of the above-described second embodiment, and corresponding parts are denoted by corresponding reference numerals to facilitate understanding. The difference is that the first to fourth
At least one of the LDD regions 61, 62, 63, 64
The individual has a different concentration from the other LDD regions. Conversely, all LDD regions have the same length of 1.0 μm. Specifically, the fourth LDD region 64 closest to the pixel electrode 13 is connected to the other LDD regions 61, 62,
It has a lower density than 63. For example, after the gate electrode 9 is formed, As ⁺ or P ⁺
It is implanted at a dose of about × 10 ¹³ cm ⁻² , and then only the fourth LDD region 64 is covered with a resist, and then As ⁺ or P ⁺ ions are again applied to about 0.6 to 1.2 × 10 ¹³ cm ⁻² . Drive in dose. In this manner, a TFT having only a low concentration in the fourth LDD region 64 can be formed, so that the leakage current can be suppressed to a low level. In the present embodiment, the first to fourth L
The lengths of the DD regions are all 1 μm. If the ON current is insufficient, the length of the third LDD region 63 is reduced to, for example, about 0.5 μm, as in the second embodiment described above, so that a high ON current can be secured while suppressing the leak current. Can be.

Needless to say, the LDD length and LDD of the TFT
Concentrations and their combinations are not limited to those disclosed in the second and third embodiments. LDD length, LDD
This is because, if the specifications of the active matrix type liquid crystal display device using the TFT are different, the concentration and the combination thereof have properties that should be optimized according to the specification. In the second and third embodiments, the channel length of the TFT is set to 2.5 μm, the channel width is set to 3 μm, and the LDD length is set to 1 μm. However, the dimensions of the TFT are limited to this. Of course it is not. According to the above-described second and third embodiments, the degree of freedom in designing a TFT is increased, so that the degree of freedom in designing a pixel electrode pattern layout is also increased, and as a result, the pixel aperture ratio is maximized. It is also possible to design a TFT as described above. As described above, the present invention also greatly contributes to improving the aperture ratio of the liquid crystal display device.

Next, the present invention will be described in detail from another viewpoint of switching element redundancy. For example, in the first embodiment shown in FIG. 1, the switching element has a double-gate structure in which two thin-film transistors are used and the respective gate electrodes are commonly connected. In general, three or more T
This is referred to as a multi-gate structure including FT series connection. The pair of thin film transistors has a leakage current suppressing structure. Specifically, it has an LDD structure. This 2
The LDD TFTs are connected in series to ensure redundancy against a current leak failure. Hereinafter, the redundancy of the switching element having the double gate structure LDD TFT will be described by creating and evaluating various defect modes.

First, a model structure of a switching element composed of a double-gate LDD TFT which has been evaluated will be described with reference to FIG. This switching element is formed by connecting TFT1 and TFT2 in series. The open end of the TFT 1 is grounded as a source, and the open end of the TFT 2 is applied with a predetermined voltage Vds as a drain. A predetermined gate voltage Vgs is applied to the commonly connected gates. Under this condition, the leakage current flowing through the switching element is measured and evaluated. The LDD regions provided on both sides of the channel region of the TFT 1 are represented by
The LDD regions provided on both sides of the channel region are denoted by.

In the model shown in FIG.
A plurality of types of modes in which one or two of the DD regions 1 to 2 were simulated were created, and the leak current was measured. The results are shown in Table 1 below.

[Table 1]

In Table 1, the first column is a double gate LDD.
Various defect modes 1 of switching element composed of TFT
-12. Note that these modes include a defect mode relating to a single gate LDD TFT for comparison. In this model, the dimensions of the TFT are such that the channel width is set to 50 μm, the channel length is set to 2.5 μm, and the LDD length is set to 1 μm. In particular,
In order to facilitate the measurement of the leak current, the channel width was set to 16.7 times the actual switching element TFT. The second column in FIG. 1 shows the location of the LDD region where a defect has occurred in each mode. The symbols in the second column to correspond to the positions of the four LDD regions shown in FIG. For example, in the mode 1, all the LDD regions are marked with a circle. Therefore, mode 1 is a defect-free double gate LDD.
Represents a TFT. In mode 2, the LDD region is marked with a cross. Therefore, this mode 2 means that the drain side LDD region of the TFT 2 has a defect with reference to FIG. Note that this defect is artificially caused by LD
The simulation is performed by deleting the D region. Hereinafter, similarly, locations of defective LDD regions are shown for each mode. However, the mode 8 and the mode 10 are the switching elements composed of the single gate LDD TFTs for comparison, and are marked with a minus sign because there is no corresponding part in the LDD region. The third column of Table 1 shows the result of measuring the leak current for each mode. Note that this leak current is Vgs = −6V with reference to FIG.
, And Vds = + 10 V. Finally, the fourth column of Table 1 shows the judgment indicating the evaluation result for each mode. Modes 1 to 9 show that even when an LDD defect is partially included, the switching element operates normally and no pixel defect is recognized. On the other hand, Modes 10 to 12 indicate that the switching element does not operate normally and a pixel defect appears.

Based on Table 1 created under the above conditions,
Consideration will be given to the redundancy of the switching element having the double gate LDD TFT. Mode 1 has four L
This shows a case where there is no defect in the DD region to, and the leak current is naturally 7.8 pA, which is low, and no pixel defect appears. Next, mode 2 to mode 5 are four LDD areas
Is a case where any one of them is destroyed or damaged. In this case, since one of the pair of TFTs operates completely normally, the leak current is low and no pixel defect occurs. For modes 6 and 7, one TFT
Is the case where both of the LDD regions included in are damaged. Also at this time, since the remaining TFTs operate normally, the leak current is low and no pixel defects occur. On the other hand, mode 8 represents a switching element composed of a single-gate LDD TFT for comparison, so that leak current can be suppressed and pixel defects do not occur unless the LDD region is destroyed. However, as shown in mode 10, a single gate LDD
If one of the LDD regions of the TFT (the drain-side LDD region in mode 10) is damaged, the leak current increases extremely, resulting in pixel defects. Therefore, no redundancy is obtained with the single gate structure, and the destruction of the LDD region immediately leads to a pixel defect. Modes 9 and 11 show a case in which the LDD region has been damaged in each of the two TFTs by a double gate structure. In Mote 9, one T
The drain side LDD region of the FT and the source side LDD region of the other TFT are broken. Even in this case, the drain-side LDD region of the other TFT functions effectively, and the leakage current can be suppressed. On the other hand, in mode 11, the drain-side LDD region of each TFT is destroyed at the same time. Only at this time, the leak current increases and pixel defects occur. Therefore, in the double gate structure, desired redundancy can be ensured by providing the LDD region at least between the impurity region functioning as a drain and the channel region. However, when a switching element having a double gate structure is used for driving a liquid crystal pixel, the source region and the drain region are alternately replaced because they are driven by alternating current, and are equivalent to each other. Therefore, in this case, it is optimal to provide a total of four LDD regions on both sides of the pair of channel regions as in the first embodiment shown in FIG. Finally, Mode 12 shows a case where all four LDD regions are destroyed, and naturally the leak current increases and pixel defects appear. However, the probability of occurrence of mode 12 is statistically extremely low, and pixel defects having current leakage can be virtually completely eliminated.

As is apparent from the above considerations, it is understood that no pixel defect occurs when at least one of the pair of LDD TFTs constituting the double gate structure has a function of sufficiently suppressing the leak current even when used alone. Is done. The probability that one TFT is damaged in the manufacturing process to cause an increase in leakage current or the probability of having a crystal defect leading to an increase in leakage current is only one to several pixels per 100,000 pixels, and is 10 ^−5. It has been empirically confirmed that this is an order. Accordingly, the probability that a pair of TFTs connected in series is damaged at the same time or has a crystal defect that leads to an increase in the leak current at the same time and the actual pixel defect occurs is (10 ⁻⁵ ) ² = 10 ⁻¹⁰ , It is about 1/10 billion. Therefore, the pixel defect is effectively eliminated. Double-gate structure LDD according to the present invention
When an active matrix type liquid crystal display device was fabricated using a switching element composed of a TFT and inspected for about 33 million pixels, no pixel bright spot defect caused by current leakage of the switching element was found at all. ,
It is clear that the redundancy effect of the double gate LDD TFT according to the present invention is enormous.

On the other hand, when a conventional multi-gate TFT having no LDD region is used as a switching element, redundancy for a current leak defect cannot be obtained.
Because the conventional multi-gate structure TFT is one TFT
The reason for this is that it is not possible to sufficiently suppress the leak current, and the present invention does not satisfy the condition that "one TFT has a sufficiently low leak current" required for redundancy.

Also, the conventional single gate structure LDD TF
When T is used as the pixel driving switching element, it has been clarified that most of the pixel defects are caused by a current leak increase failure in the off state of the switching element. The reason why the current leakage of the TFT occupies most of the pixel defects is that the static electricity flows through the pixel electrode during the manufacturing process such as the plasma process and the rubbing process.
It is considered that the main cause is to destroy the PN junction located at the drain end. In the case of a conventional active matrix type liquid crystal display device using a single gate structure switching element, such a leak defect occurs at a rate of one to several pixels per 100,000 pixels. It was out of control and could not completely eradicate pixel defects. In addition to the electrostatic damage, an increase in leakage current due to a poly-Si crystal defect constituting a TFT element region is one of the causes of the defect, and it is difficult to cope with the improvement in the manufacturing process. Was.

In order to further improve the production yield of the active matrix type liquid crystal display device, various redundant configurations have conventionally been adopted. For example, a configuration in which a plurality of switching elements are provided for one pixel or a spare switching element is provided is conventionally known. However, these conventional methods are unavoidably adopted in order to secure an initial manufacturing yield to some extent, and the cost of the redundancy of providing a plurality of switching elements for one pixel increases the number of manufacturing steps and wiring. There have been many drawbacks, such as a disconnection failure, a complicated connection process, and a complicated peripheral drive circuit. On the other hand, in the present invention, the double gate structure LD
The adoption of the D TFT allows the single switching element itself to have redundancy, and does not have any of the above-mentioned conventional disadvantages. In other words, there is no increase in the number of manufacturing steps, there is no need to repair defective pixels, and there is no need to change the peripheral drive circuit. As described above, a double gate structure LDD TFT
The benefits of redundancy provided by this are enormous and can be quite elusive. In particular, the present invention is an extremely effective technique for an active matrix liquid crystal display device including several million pixels or more, which is developed for a next-generation high-definition television system.

In this embodiment, the double gate structure LDD
Although the redundancy of the switching element has been described using a TFT as an example, the present invention is not limited to this as can be understood from the above description. For example, the number of TFTs included in one switching element is not limited to two, but may be a multi-gate structure of three or more. Further, a series connection of MOSFETs formed on a single crystal silicon wafer may be used instead of the TFT as a component of the switching element. Further, a laser-annealed poly-Si TFT may be connected in series, or an amorphous silicon TFT may be connected in series. These transistor elements have a predetermined current leakage suppressing structure, similarly to the LDD TFT. When used as an active matrix liquid crystal display device, the size of the pixel and the size of the auxiliary capacitance are not limited to the present embodiment.

Finally, for reference, a specific configuration of each of the modes 1 to 12 shown in Table 1 will be described. First, for Mode 1, the switching element configuration shown in FIG. 23 was adopted. In this example, the switching element has a pair of n-channel TFTs connected in series, and is used, for example, for driving pixels of an active matrix liquid crystal display device. Since the liquid crystal pixel is generally driven by an alternating current, the source side and the drain side of the switching element are alternately switched. Therefore, the structure and positional relationship of the LDD TFT must be symmetric with respect to the source and drain regions. That is, the source and drain regions must be equivalent and interchangeable. Therefore, in mode 1, which is a basic configuration, L
DD regions are provided at four locations in contact with the end surfaces of the pair of gate electrodes. Hereinafter, the configuration will be specifically described. On an insulating substrate 1 made of quartz or the like, a patterned polycrystalline semiconductor layer, for example, a poly-Si film is formed. This film has a source region 3, a source / drain region 4, a drain region 5, and a pair of channel regions 2 located between the three.
Are formed. Between the source region 3, the source / drain region 4, the drain region 5, and each channel region 2, a low-concentration impurity region of the same conductivity type, that is, an LDD region 6 is formed in a total of four places. In order to correspond to the model shown in FIG. 22, the four LDD regions are denoted by reference numerals. A gate electrode 9 is formed above each channel region 2 via a gate insulating film. The insulating substrate 1 is covered with an interlayer insulating film 10. The wiring electrode 11 is electrically connected to the source region 3 via a contact hole formed in the interlayer insulating film 10. Similarly, the pixel electrode 13 is electrically connected to the drain region 5 via the contact hole.

FIG. 24 is a graph showing the drain current (Ids) / gate voltage (Vgs) characteristics of the switching element shown in FIG. As shown earlier in Table 1, when the gate voltage Vgs was set to -6 V, the leakage current was 7.8 pA. Thus, double gate structure LDD
By employing a TFT, the leakage current of the switching element can be greatly suppressed, and the pixel defect caused by an increase in the leakage current has been dramatically reduced.

FIG. 25 shows a switching element structure corresponding to mode 2. In this mode 2, one LDD
The LDD region located on the drain end side of the TFT is removed, which means that the LDD portion is damaged when considered equivalently. In other words, it is considered that the removal of the LDD region simulates electrostatic breakdown, crystal defects, and the like of the portion. Note that interlayer insulating films, wiring electrodes,
The structure of the pixel electrodes and the like is omitted since it is the same as that of the first mode shown in FIG. Hereinafter, the same applies to all modes.

FIG. 26 is a graph showing the results of measuring the drain current / gate voltage characteristics of the switching element of mode 2 shown in FIG. Although the leak current under the same conditions as in Mode 1 is as high as 27.7 pA as shown in Table 1, the leak current is sufficiently low, not so much as to cause a pixel defect. That is, the meaning of mode 2 is L
Even if the DD region is damaged, the switching element itself can operate normally and desired redundancy is obtained.

Next, mode 3 can be realized by reversing the polarity of mode 2 shown in FIG. That is, the drain current / gate voltage characteristics were measured under the condition that the polarity of the drain voltage of the switching element was inverted and the LDD region on the source end side was omitted. Referring to the structure of FIG. 23, it is considered that this mode 3 simulates a case where there is damage or a crystal defect in the junction at the source end. The result of the leak current measurement under the same conditions as in Mode 1 was 9.0 pA, and the leak current difference was within the measurement error range, indicating that damage on the source end side does not substantially affect the leak characteristics.

Next, FIG. 27 shows a model structure corresponding to mode 4, in which the LDD region is removed. That is, it simulates that a damage or a crystal defect has occurred in this portion. As shown in Table 1, the leakage current in this case is about 14.6 pA and slightly increases, but is a sufficiently low value and does not cause a pixel defect.

Next, the mode 5 is realized by inverting the polarity of the drain voltage of the TFT with respect to the switching element of the mode 4 shown in FIG. That is, by exchanging the drain side and the source side shown in FIG. 27, the LDD region is equivalently removed. When the drain current / gate voltage characteristics were measured under the condition that the polarity of the drain voltage was inverted, the leakage current under the same conditions as in Mode 1 was about 6.6 pA, and the difference was within the error range. Therefore, it is understood that even if the LDD region is substantially damaged, the leakage characteristics of the switching element are not affected.

FIG. 28 shows a model of a switching element corresponding to mode 6. That is, L on one TFT side
DD areas are both removed. In this case, the leak current is about 13.1 pA and slightly increases, but is a sufficiently low value, and does not cause a pixel defect.

Mode 7 was realized by exchanging the source side and the drain side of mode 6 shown in FIG. That is, a pair of LDD regions is equivalently removed at the same time. The leakage current in this case is 25.5 pA
Although slightly higher, this is not enough to cause a pixel defect, and the leak current is suppressed sufficiently low.

Mode 8 is created for comparison and is a switching element composed of an LDD TFT having a single gate structure. The channel width is set to 50 μm, the channel length is set to 2.5 μm, and the LDD length is 1
It is set to μm. The leak current measured under the same conditions as in Mode 1 is about 24.6 pA, and no pixel defect occurs. That is, even with a single gate structure, LDD T
The switching element operates normally only when the FT is normal. However, as a matter of course, the desired redundancy cannot be obtained with the single gate structure.

FIG. 30 shows a model of a switching element corresponding to mode 9. That is, the LDD region is removed from one TFT constituting the double gate, and the LDD region is removed from the other TFT. In this case, the leak current under the same conditions as in mode 1 is 14.7.
It is on the order of pA and slightly increases, but is a sufficiently low value, and does not cause a pixel defect. That is, a pair of LDD TFs
Even if T is simultaneously damaged, the normal operation of the switching element itself can still be ensured, and desired redundancy can be obtained. Especially in the case of mode 9, the LDD located on the drain side
A region remains, and this existence greatly contributes to the suppression of the leak current.

FIG. 31 shows a mode 1 provided as a comparative example.
The model structure of the switching element corresponding to 0 is shown. This switching element is composed of an LDD TFT having a single gate structure, and the LDD region on the drain side is removed. For comparison, similarly to the double gate structure, the channel width is set to 50 μm, the channel length is set to 2.5 μm, and the LDD length is set to 1.0 μm.

The drain current / gate voltage characteristics of Mode 10 are shown in the graph of FIG. As is clear from this graph, the leak current greatly increases, and under the same conditions as in mode 1, the leak current becomes 1 nA or more. At the same time, the threshold voltage Vth of the TFT shifts greatly to the depletion side due to the short channel, and a pixel defect occurs.

FIG. 33 shows a model structure of a switching element corresponding to mode 11. In this mode, the LDD region is removed from the drain side of one TFT,
The LDD region is also removed from the drain side of the other TFT.

FIG. 34 is a graph showing the result of measuring the drain current / gate voltage characteristics of the switching element of mode 11 shown in FIG. The leakage current has increased remarkably, and the leakage current is 34
It is about 0 pA.

Finally, FIG. 35 shows a switching element structure corresponding to mode 12 as a comparative example. This mode has a double gate structure, but all LDD regions are removed, resulting in a conventional double gate structure which does not employ the LDD structure.

FIG. 36 is a graph showing drain current / gate voltage characteristics of the switching element of mode 12 shown in FIG. As shown in the figure, the leakage current is significantly increased, and the leakage current is 488 pA under the same measurement conditions as in mode 1.
It is about.

In any of the modes 11 and 12, pixel defects can no longer be suppressed. Therefore, in order to secure redundancy for suppressing a leak defect, each of the two TFTs constituting the double gate structure is a single TFT equivalent to the TFT.
It can be seen that even when FT is used as a pixel driving switching element, it is necessary that the leak current be small enough to prevent pixel defects.

[0068]

As described above, according to one aspect of the present invention, a switching element for driving a pixel is formed of a TFT in which an LDD structure is added to a multi-gate structure. There is an effect that a state in which the variation in the TFT threshold voltage can be suppressed and the variation in the TFT threshold voltage is small can be easily realized. In addition, there is an effect that the variation of the gate capacitance coupling can be suppressed low. For this reason, an active matrix type liquid crystal display device having high definition, high resolution, and high aperture ratio can be realized, and its effect is extremely large. or,
By setting at least one of the plurality of low-concentration impurity regions to have a different length or a different concentration from the other low-concentration impurity regions, a high on-state current can be obtained while keeping the leakage current of the TFT low. It greatly contributes to higher performance of active matrix type liquid crystal display devices. Further, since the degree of freedom in TFT design is increased, it contributes to an improvement in the pixel aperture ratio.
According to another aspect of the present invention, the switching element has a multi-gate structure including a plurality of thin film transistors and connecting each gate electrode in common. Each thin film transistor has a leak current suppressing structure, and at least two thin film transistors are connected in series to provide redundancy against a current leak failure. Since the switching element itself is provided with redundancy in this way, it is possible to significantly suppress leakage current defects of the switching element without complicating wiring and peripheral driving circuits. In this case, the occurrence of pixel defects can be significantly suppressed as compared with the related art, and the yield and reliability can be significantly improved. As described above, the present invention has a great effect in improving the performance of the active matrix type liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a schematic partial sectional view showing a TFT which is a main part of a first embodiment of an active matrix type liquid crystal display device according to the present invention.

FIG. 2 is a schematic cross-sectional view showing a modification of the TFT shown in FIG.

FIG. 3 is a schematic sectional view showing another modification of the TFT shown in FIG. 1;

FIG. 4 is a schematic sectional view showing still another modified example of the TFT shown in FIG. 1;

FIG. 5 is a manufacturing process diagram of the TFT shown in FIG. 1;

FIG. 6 is a manufacturing process diagram.

FIG. 7 is a manufacturing process diagram.

FIG. 8 is a manufacturing process diagram.

FIG. 9 is an n-channel multi-gate LD according to the present invention.
4 is a graph showing gate voltage / drain current characteristics of a D TFT.

FIG. 10 is a graph showing gate voltage / drain current characteristics of a conventional n-channel multi-gate TFT.

FIG. 11 shows a multi-gate structure LDD T according to the present invention.
It is a perspective view showing an example of an active matrix type liquid crystal display constituted by using FT.

FIG. 12 is a sectional view showing a conventional LDD structure TFT.

FIG. 13 is a sectional view showing a conventional multi-gate TFT.

FIG. 14 is an equivalent circuit diagram of one pixel in an active matrix type liquid crystal display device using a conventional multi-gate TFT as a switching element.

FIG. 15 is a waveform chart showing a change in pixel potential in a conventional active matrix liquid crystal display device.

FIG. 16 is a schematic partial sectional view showing a TFT which is a main part of a second embodiment of the active matrix type liquid crystal display device according to the present invention.

FIG. 17 is an n-channel multi-gate L according to the present invention.
4 is a graph showing a gate voltage / drain current characteristic of a DD TFT.

FIG. 18 is a manufacturing process diagram of the TFT shown in FIG.

FIG. 19 is a manufacturing process drawing.

FIG. 20 is a manufacturing process drawing.

FIG. 21 is a schematic partial sectional view showing a TFT which is a main part of a third embodiment of the active matrix liquid crystal display device according to the present invention.

FIG. 22 is a schematic diagram illustrating a redundant model of a switching element according to the present invention.

FIG. 23 is a cross-sectional view for explaining the redundancy of the switching element according to the present invention.

FIG. 24 shows a drain current /
It is a gate voltage characteristic diagram.

FIG. 25 is a cross-sectional view for explaining redundancy.

FIG. 26 shows a drain current /
It is a gate voltage characteristic diagram.

FIG. 27 is a cross-sectional view for explaining redundancy.

FIG. 28 is a cross-sectional view for explaining redundancy.

FIG. 29 is a cross-sectional view for explaining redundancy.

FIG. 30 is a cross-sectional view for explaining redundancy.

FIG. 31 is a cross-sectional view for explaining redundancy.

FIG. 32 shows a drain current /
It is a gate voltage characteristic diagram.

FIG. 33 is a cross-sectional view for explaining redundancy.

FIG. 34 shows a drain current /
It is a gate voltage characteristic diagram.

FIG. 35 is a cross-sectional view for explaining redundancy.

FIG. 36 shows a drain current /
It is a gate voltage characteristic diagram.

[Explanation of symbols]

 Reference Signs List 1 quartz substrate 2 channel region 3 source region 4 source / drain region (connection region) 5 drain region 6 LDD region 7 gate oxide film 8 gate nitride film 9 gate electrode 10 first interlayer insulating film 11 wiring electrode 12 second interlayer insulating film 13 Pixel electrode

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-218070 (JP, A) JP-A-2-247619 (JP, A) JP-A-63-64363 (JP, A) JP-A-63-63 200534 (JP, A) JP-A-5-121439 (JP, A) JP-A-5-289103 (JP, A)

Claims (12)

(57) [Claims] A substrate provided with pixel electrodes arranged in a matrix and a switching element for driving the pixel electrodes; and a substrate provided with a counter electrode and disposed opposite to the one substrate. A liquid crystal display device having a liquid crystal layer held on a substrate, wherein the switching element connects a plurality of thin film transistors in series by a connection region also serving as a source / drain region, and connects the respective gate electrodes to each other. Each thin film transistor has an LDD structure including a low-concentration impurity region of the same conductivity type as at least a source region or a drain region between a source region or a drain region and a channel region. The connection region has a higher impurity concentration than the low-concentration impurity region, like the source region and the drain region. Place. 2. A low-concentration impurity region provided between at least a source region or a drain region closest to a pixel electrode and a low-concentration impurity provided between a source region or a drain region farthest from a pixel electrode and a channel region. 2. The liquid crystal display device according to claim 1, further comprising an impurity region. 3. The liquid crystal display device according to claim 1, wherein each thin film transistor has a low concentration impurity region between both the source region and the drain region and the channel region. 4. The switching element comprises a pair of thin film transistors connected in series, one having a low concentration impurity region only between a source region and a channel region, and the other having only a low concentration impurity region between a drain region and a channel region. 2. The liquid crystal display device according to claim 1, comprising a low concentration impurity region. 5. The liquid crystal display device according to claim 1, wherein each thin film transistor has a channel length of 5 μm or less. 6. The liquid crystal according to claim 1, wherein at least one of the plurality of low concentration impurity regions provided in the plurality of thin film transistors has a length different from other low concentration impurity regions. Display device. 7. One of a substrate provided with pixel electrodes arranged in a matrix and a switching element for driving the pixel electrode, and the other substrate having a counter electrode and disposed so as to face the one substrate. A switching device, wherein the switching element has a multi-gate structure in which a plurality of thin film transistors are connected in series and respective gate electrodes are electrically connected to each other. Has an LDD structure having at least a low-concentration impurity region of the same conductivity type as the source region or the drain region between the source region or the drain region and the channel region; At least one of the low-concentration impurity regions has a length different from that of the other low-concentration impurity regions, and the low-concentration impurity region closest to the pixel electrode. But the liquid crystal display device and wherein the longer than other low concentration impurity regions. 8. One of a substrate provided with pixel electrodes arranged in a matrix and a switching element for driving the pixel electrode, and the other substrate having a counter electrode and disposed opposite to the one substrate. A switching device, wherein the switching element has a multi-gate structure in which a plurality of thin film transistors are connected in series and respective gate electrodes are electrically connected to each other. Has an LDD structure having at least a low-concentration impurity region of the same conductivity type as the source region or the drain region between the source region or the drain region and the channel region; A liquid crystal display device characterized in that at least one of the high concentration impurity regions has a different concentration from other low concentration impurity regions. 9. The liquid crystal display device according to claim 8, wherein the low concentration impurity region closest to the pixel electrode has a lower concentration than other low concentration impurity regions. 10. Electrodes for pixels arranged in a matrix.
And display comprising a switching element for driving this electrode
A switching element comprising a plurality of thin film transistors, having a multi-gate structure in which gate electrodes are connected in common, and each of the thin film transistors is an LD which is a low concentration impurity region.
It has an LDD type leakage current suppression structure having a D region, and at least two of the thin film transistors are connected to respective sources /
The connection region is also connected in series by a connection region also serving as a drain region. The connection region has a higher impurity concentration than the low-concentration impurity region, like the source region and the drain region, and has a feature of providing redundancy against a current leak failure. Do
Display substrate. 11. The LDD thin film transistor
11. The display substrate according to claim 10, wherein an LDD region having the same conductivity type as the impurity region and a lower concentration is provided between at least the impurity region functioning as a drain and the channel region . 12. The display substrate according to claim 11, wherein the LDD thin film transistor has an impurity region functioning as a drain alternately on both sides of the channel region and an associated LDD region .