JP3334730B2 - Sync pulse detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous pulse detecting circuit.

[0002]

2. Description of the Related Art In a television receiver, when tuning (tuning) of a tuner circuit is controlled by a voltage synthesizer circuit, for example, it can be configured as shown in FIG.

That is, in FIG. 4, reference numeral 1 denotes a tuner circuit of an electronic tuning system. This tuner circuit 1 transmits a broadcast wave signal of a frequency (channel) corresponding to the magnitude of a tuning voltage VT supplied thereto. In addition to the selection, the frequency is converted into an intermediate frequency signal and output.
Then, the intermediate frequency signal from the tuner circuit 1 is supplied to a video detection circuit 3 through a video intermediate frequency circuit 2 to extract a color composite video signal, and this signal is supplied to a video signal processing circuit 4 for color demodulation. Is performed to extract three primary color signals, and these signals are supplied to a color display 5 such as a color LCD to display a color image.

In the clock forming circuit 11, various timing signals and clock signals are formed and supplied to each circuit, and one of the clock signals is supplied to a 14-bit counter 12 as its count input. Is done. Then, the count output D12 of the counter 12 is supplied to the D / A converter 13 to be converted from a digital value to an analog voltage, and this voltage is supplied to the tuner circuit 1 as its tuning voltage VT. Thus, in the tuner circuit 1, a channel (frequency) corresponding to the count value D12 of the counter 12 is selected.

[0005] Further, reference numeral 14 denotes a tuning control circuit constituted by standard cells. The control circuit 14 controls the count of the counter 12, thereby controlling the count value D12 to control the magnitude of the tuning voltage VT.
As a result, the receiving channel is selected.

For this reason, as shown in FIG. 5, for example, an AFT voltage V15 whose value changes in an S-shape around the normal tuning point f0 is extracted from the detection circuit 3, and this AFT voltage V15
Is supplied to the AFT signal forming circuit 15. V0: the AFT voltage V15 at the normal tuning point f0 Δf: the allowable error of the reception frequency with respect to the normal tuning point f0 ΔV: the change in the AFT voltage V15 corresponding to the allowable error Δf
Is converted into a digital signal S15 indicating which of V15> V0 + ΔV V0 + ΔV ≧ V15> V0 V0 ≧ V15> V0−ΔV V15 ≦ V0−ΔV, and this signal S15 is supplied to the control circuit 14 as an AFT signal. Is done.

An output signal of a synchronization separation circuit (not shown) of the processing circuit 4 is supplied to a synchronization pulse detection circuit 16 to form a detection signal S16 indicating the presence or absence of a synchronization pulse. 14. Further, the control circuit 14 is connected to an up key KUP and a down key KDOWN of a channel.

Then, for example, when the up key KUP is pressed,
A signal indicating permission of counting and a signal indicating up-counting are supplied from the control circuit 14 to the counter 12, and the counter 12 starts up-counting when the up key KUP is pressed. Therefore, the tuning voltage VT gradually increases in response to the up-count, and the reception frequency of the tuner circuit 1 gradually increases.
That is, scanning of the channel on which broadcasting is being performed is executed in the direction in which the channel number increases.

When a broadcast wave signal of a television broadcast is received at a certain frequency, a video signal is output from the detection circuit 3, and a synchronization pulse is obtained in the processing circuit 4. Then, the control circuit 14 is notified that the synchronization pulse is obtained by the detection signal S16 from the synchronization pulse detection circuit 16. The output signal S15 of the AFT signal forming circuit 15 also changes from the above, and the signal S15 is supplied to the control circuit 14.

As a result, the control circuit 14 outputs these signals S
15, it is determined that the broadcast wave signal has been received based on S16,
Thereafter, the control circuit 14 controls the count of the counter 12 and the direction of the count (up-count or down-count) so that the above or the above state is maintained. That is, the AFT operation starts.

When the up key KUP is depressed, scanning is performed in the direction in which the channel number increases. When a channel on which broadcasting is being performed is received, scanning stops on that channel. Is continued.

Similarly, when the down key KDOWN is pressed, the counter 12 counts down, scanning is performed in the direction in which the channel number decreases, and when a channel on which broadcasting is being performed is received, Scanning stops at that channel, and the reception state of that channel is continued thereafter.

Therefore, an arbitrary channel can be selected by pressing the keys KUP and KDOWN.

When an arbitrary channel is being received and a scan is being performed, the counter 1
The count value D12 of 2 corresponds to the reception channel (reception frequency) at that time.

The count value D of the counter 12 is
Channel display is performed using 12. This channel is displayed on the display 5 as shown in FIG.
A vertical bar 5B is displayed on the screen, and the horizontal position of the bar 5B changes according to the reception channel.

In order to realize such a channel display, the count output D12 of the counter 12 is supplied to a bar display signal forming circuit 17, for example, as shown in FIG. A pulse P17 whose phase θ with respect to the horizontal synchronizing pulse PH changes in accordance with the count value D12 of the counter 12 is formed. However, this pulse P17 is formed only for one second, for example, when the scanning of the reception frequency is being performed and after the scanning is stopped.

Note that such a pulse P17 is, for example,
The upper 7 bits of the count output D12 are compared with the count output of a 7-bit counter that repeats the count from the minimum value to the maximum value every horizontal period, and a coincidence output of the comparison is taken out only for a period necessary for display. Can be obtained by

The pulse P17 is supplied to the video processing circuit 4 as a control signal, and during the period when the pulse P17 rises, for example, of the video signals supplied from the processing circuit 4 to the display 5, for example, a red signal has a white level. The green signal and the blue signal are set to the black level. Further, a number indicating a channel is provided, for example, on the lower side of the screen of the display 5.

Therefore, a red bar 5B is displayed on the screen of the display 5 during the scanning and for a predetermined period after the scanning is stopped, as shown in FIG.
The display position of the bar 5B in the horizontal direction changes according to the phase θ, and the phase θ changes according to the channel (frequency) currently being received. , The channel currently being received. Further, since the bar 5B moves in the horizontal direction according to the scanning speed during the scanning, it is possible to know that the scanning is being performed.

[0020]

The synchronous pulse detecting circuit 16 can be constituted by a charge / discharge circuit and a level detecting circuit. That is, when a synchronization pulse is obtained, the capacitor is charged. When the synchronization pulse is not obtained, the capacitor is discharged, and the presence or absence of the synchronization pulse is determined by checking the terminal voltage of the capacitor.

In this case, if the charging time constant and the discharging time constant can be set independently, the synchronization pulse can be detected appropriately.

However, in practice, it is quite difficult to realize the optimum point of the charging time constant and the discharging time constant and to prevent the fluctuation from occurring.

Further, if an attempt is made to prevent a malfunction due to noise or the like, the time constant must be set longer, resulting in a slow response. That is, it is still difficult to achieve both the stability or reliability of the detection operation and the response speed.

The present invention is to solve such a problem.

[0025]

According to the present invention, for example, a composite video signal is supplied to a synchronizing separation circuit to separate a synchronizing pulse, and a television picture system in which a deflection system operates using the separated synchronizing pulse. The position of the output pulse output from the sync separation circuit is compared with the position of the pulse output from the deflection system for each horizontal blanking period, and the output pulse of the sync separation circuit is A first output circuit that outputs a pulse only when the pulse is at the position of a pulse for each ranking period, an output pulse of the first output circuit, and a pulse that is output for each horizontal blanking period are supplied; Information indicating the presence / absence of an output pulse from the first output circuit is written as a bit pattern for each pulse output for each horizontal blanking period. And comparing the content of the first storage circuit with a preset first reference bit pattern, and that the output pulse of the first output circuit is continuous for 4 to 6 cycles. A first comparison circuit that outputs a first pulse when the first pulse is detected, an output pulse of the first output circuit, and a pulse that is output every horizontal blanking period. A second storage circuit in which information indicating the presence / absence of an output pulse from the output circuit is written as a bit pattern for each pulse output in each of the horizontal blanking periods; a content of the second storage circuit; And a second comparison circuit that outputs a second pulse when it is detected that the output pulse of the first output circuit is not continuous for 10 cycles or more. The first pulse output from the first comparison circuit is set to one level state indicating that there is a synchronization pulse, and the second pulse output from the second comparison circuit And a second output circuit for outputting a signal set to the other level indicating that there is no synchronization pulse.

[0026]

When the output pulse P22 is obtained, for example, for four consecutive cycles, it is determined that a synchronization pulse is obtained. When the output pulse P22 is not obtained, for example, for ten consecutive cycles,
It is determined that a synchronization pulse cannot be obtained, and this determination result is output as a detection result of the synchronization pulse.

[0027]

In FIG. 1, a pulse forming circuit 21 is constituted by a counter or the like, and a clock signal of a predetermined frequency is supplied to the forming circuit 21. Further, as shown in FIG. 3A, for example, a horizontal blanking pulse HBLK is extracted from the video processing circuit 4 and this pulse HBLK is generated by the forming circuit 2.
1 is supplied. In this way, a pulse P21 of a predetermined phase located in the horizontal blanking period is extracted from the forming circuit 21, for example, as shown in FIG. 3B.

A comparison circuit, in this example, a sampling circuit 22, is provided. A pulse P21 is supplied to the sampling circuit 22 as its sampling control signal. PSYNC is taken out and this pulse PSYNC
Is supplied to the sampling circuit 22.

FIG. 3C shows the horizontal synchronizing pulse PH of the composite synchronizing pulse PSYNC supplied to the sampling circuit 22, and the first and third horizontal synchronizing pulses PH can be normally synchronized and separated. However, the second horizontal synchronization pulse PH indicates a state in which synchronization cannot be normally separated.

In this way, the pulse PSYNC is sampled by the pulse P21 in the sampling circuit 22, and from the sampling circuit 22, for example, as shown by a solid line in FIG.
A pulse P22 is extracted every H. Although FIG. 3E has the same contents as FIG. 3D, the time axis is compressed after FIG. 3E for the sake of convenience in the following description. Also, in FIGS. 3D and 3E, the broken lines indicate the position of the pulse P22 in the case where the synchronization was not normally separated but the synchronization was normally separated.

Therefore, the pulse P22 becomes "H" level for each pulse P21 when the horizontal synchronizing pulse PH can be normally and synchronously separated, and when the horizontal synchronizing pulse PH cannot be normally separated, the pulse P22 has an "L" level even at the time of the pulse P21. Will remain.

The pulse P22 is supplied to the decision circuit 23
At the same time, the pulse P21 is supplied to the determination circuit 23 as a timing signal, and a detection signal S16 indicating the presence or absence of a synchronization pulse is formed. The determination circuit 23 determines the presence or absence of a synchronization pulse based on the number of pulses P22 when the pulse P22 is obtained continuously and the number of pulses P22 that should have been obtained when the pulse P22 is not obtained continuously. Is determined.

FIG. 2 shows a specific example of the determination circuit 23. That is, the pulse P22 is supplied as a data input to the shift register 31 of, for example, 4-bit serial input / parallel output, and the pulse P21 is supplied to the register 31 as its shift clock. And the register 31
Is supplied to a 4-bit comparison circuit 32, and all 4 bits at the “H” level are supplied to the register 32 as reference data.

Therefore, as shown in FIGS. 3E and 3F, when the pulse P22 is obtained for four consecutive cycles, the pulse P32 is output from the register 32 at the time of the pulse P22 in the fourth cycle.

Further, a pulse P22 is supplied as a data input to a shift register 33 of 10-bit serial input / parallel output, for example, and a pulse P21 is supplied to the register 33 as a shift clock. Then, the output of the register 33 is supplied to a 10-bit comparison circuit 34, and the 10 bits of all “L” levels are supplied to the register 34 as reference data.

Therefore, as shown in FIGS. 3E and 3G, if the pulse P22 is not obtained continuously for ten cycles, the pulse P34 is output from the register 34 at the time of the pulse P22 in the tenth cycle.

Then, the pulse P32 is supplied to the set input S of the RS flip-flop circuit 35, and the pulse P34 is supplied to the reset input R of the flip-flop circuit 35. Therefore, as shown in FIG. 3H, the pulse P22 becomes "H" level when four consecutive pulses are obtained from the flip-flop circuit 35, and the pulse P22 is output.
Are output at the "L" level when 10 cycles cannot be obtained continuously.

That is, from the flip-flop circuit 35, when the horizontal synchronizing pulse PH is continuously obtained for four cycles, the level becomes "H" level. An L level signal is output. Therefore, this output signal is taken out as the detection signal S16 of the synchronization pulse.

Thus, the detection circuit 16 can detect the presence or absence of a synchronization pulse.

In the above description, when the pulse P22 continues for four cycles, it is determined that a synchronization pulse has been obtained. However, according to experiments, if the number of consecutive cycles is less than six, the problem is Did not. Similarly, the pulse P
When 22 did not continue for 10 cycles or more, there was no problem even if it was determined that the synchronization pulse was not obtained.

[0041]

According to the present invention, when the pulse P22 continues for four cycles, it is determined that the synchronization pulse has been obtained, so that the detection that the synchronization pulse has been obtained is quick. If the pulse P22 is not obtained continuously for ten cycles, it is determined that the synchronization pulse has not been obtained. For example, even if the vertical synchronization pulse includes an equalization pulse over nine horizontal periods, It does not malfunction and has excellent noise resistance. That is, the response when the synchronization pulse can be obtained is fast, and it is difficult to respond to noise.

Furthermore, since all of the processing is digital processing, it is easy to realize an optimum operating point, and there is no variation. Also, since all the processing is digitized, the circuits 11 to 11 are surrounded by a chain line in FIG.
17 can be integrated into one IC 10.

Further, since the response of detecting the synchronization pulse is fast, for example, in the television receiver shown in FIG. 4, the scanning speed can be increased.

[Brief description of the drawings]

FIG. 1 is a system diagram showing an example of the present invention.

FIG. 2 is a system diagram showing an example of a main part of the circuit of FIG.

FIG. 3 is a waveform chart for explaining the operation of the circuits of FIGS. 1 and 2;

FIG. 4 is a system diagram for explaining the circuit of FIG. 1;

FIG. 5 is a system diagram for explaining the operation of the circuit of FIG. 4;

FIG. 6 is a diagram for explaining the operation of the circuit of FIG. 4;

FIG. 7 is a waveform chart for explaining the operation of the circuit of FIG. 4;

[Explanation of symbols]

 Reference Signs List 21 pulse forming circuit 22 sampling circuit 23 judgment circuit 31, 33 shift register 32, 34 comparison circuit 35 RS flip-flop circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-162968 (JP, A) JP-A-2-195778 (JP, A) JP-A-4-165889 (JP, A) 95372 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^5/ 04-5/12

Claims (2)

(57) [Claims] 1. A television receiver in which a composite video signal is supplied to a synchronization separation circuit to separate synchronization pulses, and a television system in which a deflection system operates using the separated synchronization pulses is output from the synchronization separation circuit. The position of the output pulse,
Comparing the position of the pulse output from the deflection system for each horizontal blanking period, and outputting a pulse only when the output pulse of the synchronization separation circuit is at the position of the pulse for each horizontal blanking period. 1 output circuit, an output pulse of the first output circuit, and a pulse output every horizontal blanking period, and information indicating the presence or absence of the output pulse of the first output circuit is A first storage circuit that is written as a bit pattern for each pulse output for each horizontal blanking period, and compares the content of the first storage circuit with a first reference bit pattern set in advance. A first comparison circuit for outputting a first pulse when detecting that the output pulse of the first output circuit is continuous for 4 to 6 cycles; Are supplied, and information indicating the presence or absence of an output pulse of the first output circuit is provided for each pulse output for each horizontal blanking period. A second storage circuit written as a bit pattern; comparing the content of the second storage circuit with a preset second reference bit pattern; A second comparison circuit that outputs a second pulse when it is detected that there is no continuation, and a first pulse that is output from the first comparison circuit, indicating that there is a synchronization pulse. And the second state output from the second comparison circuit.
And a second output circuit for outputting a signal set to the other level state indicating the absence of the synchronization pulse by the above pulse. 2. The synchronization pulse detection circuit according to claim 1, wherein said first output circuit is a sampling circuit for sampling an output pulse output from said synchronization separation circuit for each horizontal blanking period. Synchronized pulse detection circuit.