JP3326619B2 - PWM circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM (pulse width modulation) for converting an analog signal into a pulse width (time width).
n; pulse width modulation) circuit.

[0002]

2. Description of the Related Art Conventionally, a PWM circuit having a configuration using a comparator is generally known, and the configuration is shown in FIG. That is, the non-inverted (+) and inverted (-) input terminals of the comparator 31 are applied with the sine wave voltage e _{i +} and the triangular wave voltage e _i- , respectively.

Here, assuming that the frequency of the triangular wave is sufficiently higher than the frequency of the sine wave, and that the amplitude of the triangular wave is larger than that of the sine wave, the output voltage e ₀ of the comparator 31 is as shown in FIG. A waveform as shown in the timing chart is obtained. That is, the period during which the waveform of the output voltage e ₀ is at the “H” level, that is, the pulse width τ of the e ₀ output is proportional to the magnitude of the sine wave voltage e _{i +} .

[0004]

However, in a conventional PWM circuit using a triangular wave, there is a limit in the accuracy of the triangular wave at the bending point and the linearity of the slope, so that the linearity of the input level-pulse width characteristic is improved. Also had limitations.

The present invention has been made in view of the above points, and has as its object to provide a PWM circuit having excellent linearity of input level-pulse width characteristics.

[0006]

SUMMARY OF THE INVENTION A PWM circuit according to the present invention comprises an A / D converter for converting an input analog signal into a digital output.
A D converter, a plurality of stages of delay gates cascade-connected to each other to sequentially delay the input clock by the same delay time, and an input clock provided between each stage of the plurality of stages of delay gates. A plurality of differential amplifiers for deriving a delayed clock obtained by delaying by the delay gate as a common output, and an operating current is selectively supplied to each of the plurality of differential amplifiers based on a digital output of the A / D converter. The configuration includes a current switch circuit and a pulse generation circuit that generates a pulse signal having a pulse width corresponding to a period from when the input clock is supplied to when the delay clock is supplied.

[0007]

The input clock is sequentially delayed by the same delay time by a plurality of stages of delay gates connected in cascade with each other, and is delayed by each delay gate by a differential amplifier provided between each stage of the delay gates. By deriving the delayed clock obtained as a common output, the relationship between the number of stages through which the input clock passes through the delay gate and the delay time is directly proportional, and a delay circuit with good linearity can be configured.

By utilizing this delay circuit and selectively supplying an operating current to each of a plurality of differential amplifiers constituting the delay circuit based on the digital output of the A / D converter, the input analog signal A delay clock delayed by a delay time corresponding to the level is obtained. Then, by generating a pulse signal having a pulse width corresponding to the delay time from when the input clock is supplied to when the delay clock is supplied, a pulse signal having a pulse width with good linearity according to the analog signal level is obtained. .

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, when the resolution is N bits, (2
^N -1) number of comparators ₁ 1, 1 _2, ... are arranged, the power supply V _TOP (e.g., 2V) a power source V
Each divided level given by the divided voltage of 2 ^N equal resistors R ₁ , R ₂ ,... Connected in series between _BOTTOM (for example, 0 V) is used as a comparator 1 as a comparison reference voltage.
_1, 1 _2, the inverting input terminal of ... (-) is applied to the analog input voltage V _IN is comparators 1 _1, 1 _2, is applied in common to each non-inverting input terminal of the ... (+).

The clock CK1 and its inverted clock are applied as sampling clocks to the comparators 1 ₁ , 1 ₂ ,.... First stage comparator 1 ₁
Becomes the two inputs of the AND gate circuit 2 and
The first input of the exclusive OR gate circuit 3 _1. The output of the comparator 1 ₂ in the second stage, the exclusive OR gate circuit 3
₁ becomes the other input and the exclusive OR gate circuit 3
_Two inputs. After the third stage comparator 1 _3, 1
Similarly, each output of ₄ ... Becomes one input of each of two adjacent exclusive OR gate circuits. Thus, the A / D converter 4 of the parallel comparison system is configured.

On the other hand, delay gates 5 ₁ , 5 ₂ ,... Of 2 ^N stages each having the same delay time are provided in cascade connection with each other. The clocks CK2 whose pulse width is sufficiently narrower than the clock CK1 and which is synchronized with the clock CK1 and their inverted clocks are input to the delay gates 5 ₁ , 5 ₂ ,. Delay gate 5 _1, 5 _2, ...
A plurality of differential amplifiers 6 ₁ , 6 ₂ ,... That derive a delay clock obtained by being delayed by each delay gate as a common output are provided between the stages of.

Each of the differential amplifiers 6 ₁ , 6 ₂ ,... Has a common emitter connected to each other and uses a clock CK2 and its inverted clock as respective base inputs.
a, Qb, and an operating current is selectively supplied by a current switch circuit 8 including switching transistors Q ₁ , Q ₂ ,... connected between a common connection point of each base and a common constant current source 7. Is done. As described above, the delay circuit 9 configured to sequentially delay the clock CK2 in units of delay time per delay gate stage is configured.

[0013] That is, in the delay circuit 9, the clock CK2 is inputted first 1-stage delay gate (G ₁₎ to 5 _1, after being delayed by a predetermined delay time by the delay gates 5 _1, 2-stage the delay gates is supplied to the (G ₂₎ 5 _2. Therefore, the clock CK2 is supplied to the second differential amplifier 6
_The timing derived from ₂ is delayed by the delay time per delay gate stage. The clock CK2 input to 2-stage delay gate 5 _2, after being further delayed by a predetermined delay time by the delay gates 5 _2, 3-stage delay gate (G ₃₎ supplied to the ₃ Is done.

In this way, each of the delay gates 5 ₁ , 5 ₂ ,
Are successively transmitted to the outside of the delay circuit 9 by the differential amplifier 6 which is in an operable state when an operating current is selectively supplied from the current switch circuit 8. You. The current switch circuit 8
Any one of the AND gate circuit 2 and the exclusive OR gate circuits 3 ₁ , 3 ₂ ,... In the A / D converter 4
An operating current is supplied to any _{one of} the differential amplifiers 6 ₁ , 6 ₂ ,.

The delayed clock derived outside the delay circuit 9 is supplied to a cascade connection circuit 10. Thereby, the differential pair transistors constituting the cascade connection circuit 10 perform on / off operations. Load resistors Ra and Rb are connected between the collectors of these differential pair transistors and the ground, respectively, and the "H" level voltage derived as the output of one of the collectors becomes the delay clock D _OUT .

This delayed clock D _OUT becomes a reset (R) input of the RS flip-flop 12 and also becomes one input of an exclusive OR gate circuit 13. The exclusive OR gate circuit 13 receives the clock CK2 as another input, and its gate output becomes the set (S) input of the RS flip-flop 12. This RS flip-flop 12
And the exclusive OR gate circuit 13 generates the clock C
A pulse generation circuit is configured to generate a pulse signal having a pulse width corresponding to a period from when K2 is supplied to when the delayed clock _DOUT is supplied.

Next, the PWM according to the present invention having the above-described configuration will be described.
The circuit operation of the circuit will be described with reference to the timing chart of FIG. In this example, the circuit operation will be specifically described with reference to the timing chart of FIG. 2 in which the input analog voltage V _IN is sampled, for example, at point a by the clock CK1 which is a sampling pulse.

When the input analog voltage V _IN is at the level of the point a, the level at the point a is, for example, a voltage division level between the resistors R ₃ and R ₄ and a voltage between the resistors R ₄ and R ₅ in FIG. When the voltage is between the divided voltage levels Vb, the comparators 1 ₁ , 1
_2, the outputs of the 1 ₃ becomes "L" level and the outputs of the comparators 1 ₄ later becomes "H" level. As a result, only the output of the exclusive OR gate circuit 3 ₃ becomes the "H" level, the digital information is to be derived as the digital output of the A / D converter 4 serving as the other outputs all "L" level .

[0019] digital output of the A / D converter 4 is supplied to the current switch circuit 8, only the switching transistor Q ₄ is turned on, the differential amplifier 6
Only ₄ is connected to the constant current source 7 to make it operable. Thus, the clock CK2 delayed by respective predetermined delay time by the delay gates 5 _1, 5 ₂ and the delay gate 5 ₃ is derived by the differential amplifier 6 _4, further cascaded circuit 10 and the output amplifier 1
1 to become the delay clock D _OUT . Here, assuming that each delay time of the delay gates 5 ₁ , 5 ₂ ,... Is τ ₀ , the delay time τ of the delay clock D _OUT with respect to the clock CK 2
_a becomes 3τ ₀ .

On the other hand, the RS flip-flop 12 is set at the rising timing of the clock CK2,
It is reset by outputting the delayed clock D _OUT . Deriving a result, a pulse signal OUT having a pulse width corresponding to the delay time tau _a to delay clock D _OUT is provided from given clock CK2 is, as the time width information in proportion to the level of the input analog voltage V _IN Will be done.

[0021]

As described above, according to the present invention,
Using an A / D converter for digitizing an input analog signal and a delay circuit having a high linearity in which the relationship between the number of stages through which the input clock passes through the delay gate and the delay time is directly proportional to the level of the input analog signal, A delay clock delayed by the delay time given by the input clock is generated, and a pulse signal having a pulse width corresponding to the delay time from when the input clock is supplied to when the delay clock is supplied is generated. A pulse signal having a pulse width with good linearity can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a PWM circuit according to the present invention.

FIG. 2 is a timing chart for explaining a circuit operation of the present invention.

FIG. 3 is a circuit diagram showing a conventional example of a PWM circuit.

FIG. 4 is a timing chart for explaining a circuit operation of a conventional example.

[Explanation of symbols]

1 _1, 1 _2, 1 ₃ ... Comparator 3 _1, 3 _{2, 3} 3 ..., 13 exclusive OR gate circuit 4 A / D converter 5 _1, 5 _2, 5 ₃ ... delay gates 6 _1, 6 ₂ , 6 ₃ ... Differential amplifier 8 Current switch circuit 9 Delay circuit 10 Cascade connection circuit 12 RS flip-flop

Claims (1)

(57) [Claims] An A / D converter for converting an input analog signal into a digital output; a plurality of delay gates provided in cascade with each other so as to sequentially delay an input clock by the same delay time; A plurality of differential amplifiers provided between the respective stages of the delay gates for deriving a delayed clock obtained by delaying the input clock by the respective delay gates as a common output; and a digital output of the A / D converter. A current switch circuit for selectively supplying an operating current to each of the plurality of differential amplifiers, and a pulse signal having a pulse width corresponding to a period from when the input clock is supplied to when the delayed clock is supplied. And a pulse generating circuit for generating the pulse signal.