JP3323544B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic and storage circuit using a double heterojunction bipolar transistor (DHBT) and a field effect transistor (FET) having different polarities. In particular, PNp-type HBTs with the same epi structure
Ultra-high-speed, ultra-low-power complementary BiFET using a two-dimensional electron gas-based heterojunction bipolar transistor with a double heterojunction structure at the base and collector, which can simultaneously realize an n-channel FET and an n-channel FET.

[0002]

2. Description of the Related Art Conventionally, devices used in integrated logic circuits and integrated storage circuits (referred to as ICs) are mainly bipolar transistors and field effect transistors. In general, bipolar transistor logic circuits are characterized by high driving capability and high speed, and field effect transistor logic circuits are highly integrated and have low power consumption. In particular, in silicon conventionally used as a semiconductor material, n-type and p-type MOS (Met
al Oxide Semiconductor) FE
CMOS using T (Complementary MO)
S (complementary MOS) logic is predominant. This CMOS
With the development of technology, due to its low power consumption, it has become possible to pack hundreds of thousands of gate-scale logic LSIs on a silicon chip to about one square centimeter. As an application of CMOS technology to memory, a 4-megabit SRAM (static random access memory) can be realized with an access time of 15 nanoseconds and a low power consumption of 1 watt or less. This is due to the fact that from the viewpoint of the device structure, a technology capable of stably forming an n-channel MOSFET and a p-channel MOSFET has been developed.

On the other hand, a silicon bipolar transistor I
In C, carriers accumulate in the saturated region, so that the high-speed logic circuit needs to operate in the non-saturated region. In principle, a direct connection logic type circuit (DCTL: Direct)
ct coupled transformer log
ic) has been studied, but since the transistor operates in a saturation region, the operation speed is low, and it is hardly practically used as an IC. For this reason, a circuit type operating in the above-described unsaturated region has been adopted. That is, in a bipolar transistor, a CML (Current) operated in a non-saturation region is used.
Mode Logic and ECL (Emitter c)
The current switching type represented by coupled logic has been mainly used. In silicon bipolar transistor integrated circuits, ECL (Emitter Coupled Logic) circuits have to be used to increase the speed of LSI, and the emitter current is always kept flowing. Large-scale integration could not be realized. For example, taking the ECL circuit as an example,
The highest integration size is 64 Kbit SRAM, power consumption 20
W, access time is about 2 nanoseconds. That is, CMOS is about 100 times better in terms of integration scale and power consumption, and the comparison is not fair because it is not the same scale of integration, but silicon bipolar is about 10 times faster in terms of speed.

[0004] However, recent high-speed systems require high-speed LSIs, and the superiority of silicon bipolar is beginning to be threatened by BiCMOS and CMOS. In the field of communications, personal communication devices that communicate information in the high frequency range of about 1-30 GHz
(PCs with wireless communication function, wireless LAN) are in demand of society. A transistor / circuit with low power consumption (power consumption of about 10 mW) capable of handling such a high-frequency region has been demanded. In addition, fundamentally, ultra-low power consumption and ultra-high-speed devices are in a phase where they are truly expected.

On the other hand, in the CMOS, the performance improvement accompanying the miniaturization of the gate length does not progress as in the conventional trend, and further, the power supply voltage is changed from 5 V to 2.0 V to 3.3 in order to ensure reliability.
There is a need to reduce the voltage to about V, and the load driving capability per unit transistor width is reduced, which is causing a reduction in the speed of the LSI.

In the 1980's, ultrahigh-speed ICs made of a compound semiconductor represented by gallium arsenide, which has a mobility about six times that of silicon and can be used for a semi-insulating substrate, have been developed for 10 years. The device at this time is GaAs MESFET or H
It was a field effect transistor (FET) such as an EMT (High Electron Mobility Transistor). As a circuit format, SCFL (S
source coupled FET Logic) and D using enhancement and depletion type FETs.
CFL (Direct Coupled FET Log)
ic) is the mainstream. GaAs FETs are similar to silicon bipolar in terms of integration scale and speed, but consume less power.
The features are that it can be reduced to about 1/3 that of silicon bipolar and low noise at high frequencies. In GaAs FET, n
There is also research on complementary circuits using channel FETs and p-channel FETs (for example, IEEE IEDM Abstract 1985
317 to 320 pages a year; NCCirillo and 5 others Compl
ementary Heterostructure Insulated Gate Field Effe
See, for example, ct Transistors (HIGFETs).
For a detailed study of its circuit performance, see S. Fujita and T. Miz
utani; IEEE Transanction ED-34 1987 pp.1889-1896
Has been made. Or, eye. E. E. E. Electron Device Letters IDL 8 Number 6 (1987) to 262. ), Has the drawback that the p-channel FET cannot be made to have high performance and the high speed, which is the life of the compound semiconductor, cannot be realized. The mobility of the two-dimensional positive gas at the AlGaAs / GaAs heterojunction is 400 cm ² / Vs at room temperature, and the performance of the FET is as follows: gate length Lg = 0.1 μm, source gate resistance
When Rsg = 1.7 Ωmm, transconductance Gm = 170 mS /
mm (e.g., Usagawa, Mishima; Analysis of device characteristics of two-dimensional electron gas (2DEG) FET; IEICE Transactions on Electronics, Vol.J70-C No.5 pp.716-723 May 1987 As shown in Fig. 1 (a), only about 1/7 performance of n-channel FET can be expected, and high speed cannot be achieved. Further, from the viewpoint of power consumption, since the gate structure is a so-called Schottky junction, at the time of circuit standby, either the n-channel or the p-channel gate electrode has a high forward bias, and the gate current is reduced from the power supply to the ground side. To spend about 80% or more of the power consumption of the circuit (S. Fujita and T. Mizutani
Paper). This loses the great feature that power is consumed only at the time of circuit switching, which is an essential feature of CMOS.

On the other hand, in a hetero bipolar transistor (HBT) using a compound semiconductor, when the same circuit (for example, an ECL circuit) as a silicon bipolar transistor is employed,
The large band gap increases the turn-on voltage of the bipolar transistor by about 1.5 times,
It had the disadvantage of twice as much power consumption.

That is, a conventional FET using a compound semiconductor,
For bipolar, in the example of a logic circuit, 10 per gate
Until now, it has not been possible to provide a device capable of simultaneously realizing an ultra-low power consumption of 10 μW or less at an ultra-high speed of psec or less.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed, low-power-consumption, highly-integrated logic and storage circuit capable of processing a high-frequency signal of a microwave or millimeter wave with a simple manufacturing process. It is to provide a novel device / circuit which can be provided with a simple circuit configuration.

[0010]

According to the present invention, the broadest concept is to make a base and a collector a heterojunction,
By using the phenomenon that the minority carriers accumulated in the collector layer can be greatly reduced when the base collector is forward-biased and that the delay effect caused by the minority carriers accumulated in the base layer is negligible, Its purpose is to open up new avenues for various circuit types of bipolar transistors that would have slowed down when used. Complementary BiFETs can also be considered as one example.

[0011] In principle, the complementary BiFET operates in the above description, but several conditions and improvements are required to obtain high performance in an actual circuit. This will be described in detail in the operation of the present invention.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some of the inventors have already reported that n-type AlGaAs / undoped Ga
As two-dimensional electron gas based heterobipolar transistor (2DEG-HBT) using a two-dimensional electron gas formed at the heterojunction interface for the base layer of the heterobipolar transistor has already been invented (for example, JP-A-62-199049) Gazette or JP-A-63-236358).

[0013] One of the inventors has analyzed the device characteristics of 2DEG-HBT in detail (IEEE Transactions on Electrode).
n Devices, Vol. 38, No. 2, 1991 pp. 222-231. ), Found the following facts. GaAs / Al
In the GaAs HBT, (1) the emitter delay time τe can be extremely reduced to about 0.1 picosecond in the PNp type.
On the other hand, in (2) Npn type, the emitter delay time τe
Will remain for about 1.0 picosecond.

The interpretation will be described below. GaAs / AlGaA
In an s-based heterojunction, when the commonly used Al composition is 0.3,
Conduction band discontinuity ΔEc is 300 meV, valence band discontinuity ΔEv
Is 50 meV and ΔEc is about 6 times larger than ΔEv. This means that electrons feel a potential barrier much larger than holes. These ΔEc and ΔEv
Role of 2DEG-HBT and normal NP
This will be described with reference to the energy band diagrams of the emitter and base portions of the n-type HBT (FIGS. 3A and 3B).

In the 2DEG-HBT, as shown in FIG. 3A, an n-type AlxG, which is a supply layer of a p-type AlyGa1-yAs36 as an emitter layer and a 2DEG38 as a base layer.
a1-xAs35 the conduction band discontinuity .DELTA.Ec ₁ and the sum of the discrete .DELTA.Ec ₂ the conduction band of the n-type AlxGa1-xAs35 and 2DEG storage layer at a high purity GaAs layer 34 is a 2DEG supply layer .DELTA.Ec
From the viewpoint of the minority carrier electrons (= ΔEc ₁ + ΔEc ₂ ), it is felt as a potential barrier for suppressing injection into the emitter layer. As analyzed in the above paper, y = 0.45,
If x = 0.30, ΔEc = 450 meV, and the average energy of the electrons at room temperature kT (24.8 m
Compared to eV), it works as a deterrent potential that is larger by one order of magnitude or more. This is section B. of page 225 of the same paper.
As discussed in detail in Frequency Performance Analysis,
This is a physical reason that the 2DEG-HBT can make the emitter delay time τe as small as 0.02 to 0.1 picoseconds, which is practically negligible. On the other hand, in a normal NPn-type HBT, FIG.
As shown in (b), the n-type AlyGa1-y which is the emitter layer
As layer 135 and p-type GaAs layer 13 serving as a p-type base layer
When the discontinuous ΔEv of the valence band of 4 is viewed from the holes of the minority carriers, it is felt as a potential barrier for suppressing the injection into the emitter layer. Even when the Al composition of the emitter layer is increased from the usual 0.3 to y = 0.45, the valence band discontinuity ΔEv
Is as small as 75 meV, which is only about three times as large as the average energy kT (24.8 meV) of the holes at room temperature. Furthermore, the low potential barrier that suppresses the injection of holes of ΔEv into the emitter layer makes the emitter delay time τe as large as 1.0 picosecond, which cannot be ignored compared to other delay times. That is the reason.

Taking this inspiration, the device characteristics of a double heterojunction 2DEG-HBT in which the base collector for increasing the band gap of the collector becomes a heterojunction were analyzed in detail. In particular, as a result of analyzing the state of minority carriers (electrons in this case) that accumulate in the collector when the base collector is forward-biased, it was found that minority carriers can be significantly reduced. Immediately, a prototype of the device was evaluated, and this effect was confirmed experimentally. Physically, electrons in the base region, which is a minority carrier, have a conduction band discontinuity ΔEc between the base and collector (300 meV at Al composition 0.3, 450 m at Al composition 0.45).
It is about eV. ), It was confirmed that it was hardly implanted into the collector area. This eliminates the problem that the charge / discharge time τcc of the minority carrier accumulated in the collector slows down the circuit speed when the bipolar transistor comes out of the saturation region in the saturation type circuit of the bipolar transistor from the viewpoint of device operation. To contribute. Further, if the problem of the saturation can be ignored by the bipolar transistor, it means that a circuit type which has not been considered conventionally can be used.

The above can be explained intuitively in the same manner as the already described effect of suppressing the injection of minority carriers into the emitter. FIG. 4 shows an energy band diagram of a collector region composed of a heterojunction of undoped GaAs34 and undoped AlGaAs33 of a double heterojunction 2DEG-HBT.
(a). ΔEc is a very large potential barrier (300 meV) for electrons, and AlGaAs
It is large enough to suppress injection on the s side. On the other hand, ΔEv is a potential barrier (50 m) large enough to suppress holes from being injected into the AlGaAs side.
eV). This is a double hetero junction type 2D
This is the physical reason that the charge / discharge time τcc of the minority carriers accumulated in the collector in the EG-HBT is very short (about 0.1 picosecond). Again, GaAs / AlGaAs
The NPn-type HBT and the PNp-type HBT have a difference in charge / discharge time τcc because the roles of the conduction band discontinuity ΔEc and the valence band discontinuity ΔEv in the heterojunction are reversed. It is. That is, in a normal NPn-type HBT, the above-mentioned τcc is from several picoseconds to several tens of picoseconds.

Next, the effect of accumulating holes in the base layer will be described. In the case of 2DEG-HBT, the time for accumulating holes in the base layer is very short due to the following structural characteristics.
That is, the 2DEG-HBT is a metallurgical, normally depleted n-type AlGaAs layer 35 having no neutral region and a pn junction between an emitter and a base in a normal bipolar transistor, unlike a normal bipolar transistor. And a 2DEG in a triangular potential formed on the collector side.
Divided into FIG. 4B shows an energy band diagram when the base and the collector are forward-biased. When the base and the collector are forward-biased, holes accumulate in the region of the GaAs layer 34 with a low doping level. However, from a state where the base and collector are forward-biased,
When the state changes to the off state, a strong collector electric field E (= built-in potential between base and collector / collector layer thickness Wc ≒ 1.8 V / 300 nm = 6 × 10 ⁴ V / cm) is immediately generated as shown in FIG. The holes accumulated in the layer 34 are extracted by the strong electric field. Also, the depletion layer n
Some holes also accumulate in the type AlGaAs layer 35,
The number is very small. This is because the thickness of the n-type AlGaAs layer 35 is as thin as about 30 nm, and the space charge is positively charged. As described above, in the 2DEG-HBT, the delay time τBB of the circuit due to the minority carriers accumulated in the so-called base layer becomes very small.

According to the present invention, the heterojunction between the base and the collector can significantly reduce the minority carriers accumulated in the collector layer when the base-collector is forward-biased. It consists of a bipolar transistor and a field-effect transistor characterized in that the collector has a wider gap than the base, with different polarities, such as CMOS, using the phenomenon that the carrier delay effect can be made negligible. By using a complementary BiFET circuit described below, a semiconductor device that is faster than a bipolar ECL circuit that cannot be realized by a conventional semiconductor electronic device and that consumes less power than CMOS and that has ultra-high-speed and ultra-low power consumption is provided. In the following detailed description of the present invention, a complementary BiFET using a GaAs / AlGaAs-based 2DEG-HBT will be described.
This will be mainly described. The reasons are: 1) GaAs provides the highest quality heterojunction and process technology is the most advanced.

2) Different polarities (pnp bipolar and n
Channel FET, npn bipolar and p-channel F
ET) is the only combination that can speed up both bipolar and FET among combinations.

3) Isolation between elements is easy, there is no parasitic transistor effect such as latch-up, and the process is simple.

And so on. In principle, 2DEG-HBT
It need not be limited to. That is, the present invention can be realized by combining an HBT that suppresses the effect of accumulating minority carriers in the collector and the base and an FET having a different polarity from the HBT as described below. Also, the material is GaAs / AlGaAs.
It need not be limited to s heterojunction systems.

Incidentally, the device sectional structure of the 2DEG-HBT
(For example, IEEE Transactions on Electron Devices, V
ol.38, No.2, 1991 pp.222-231, Fig.1, (a) and (b). As can be understood from), one is a PNp type heterojunction bipolar transistor and one is a two-dimensional electron gas FET with a junction gate, so the same process steps such as electrode formation and isolation between elements are the same. PNp bipolar transistor and n-channel FE
It has the advantage that T can be formed. Furthermore, there is no need to devise special electrical element isolation technology, such as silicon complementary MOS type FET (CMOS) and BiCMOS process technology, which is a composite technology of CMOS and bipolar transistors.
2D is a very simple structure without structural complexity
This is a feature of EG-HBT. Furthermore, parasitic pnp and npn like CMOS
Since there is no transistor, a latch-up phenomenon due to minority carrier injection does not occur. This advantage is not lost if the base and collector become heterojunction.

FIG. 1 shows the simplicity of the process steps of the 2DEG-HBT and the feature that the effect of accumulating minority carriers is greatly reduced by making the base and collector a double heterojunction.
By using a complementary (complementary) BiFET with a double heterojunction 2DEG-HBT as shown in (1), an ultra-high-speed and ultra-low-power electronic circuit is provided for the first time in a compound semiconductor. 1 (a), 1 (b), 2 (a), and 2 (b) show inverter circuits (FIG. 1 (a)) and device cross-sectional structures using AlGaAs / GaAs heterojunctions (FIG. 2 (b)) , Energy band diagram (Fig. 2
The present invention will be described with reference to (a)) and inverter characteristics (FIG. 2B).

First, the basic device structure is shown in FIG.
Will be described. The cross-sectional structure of an electrically insulated junction gate 2DEGFET and 2DEG-based PNpHBT is shown. The crystal structure is such that on a semi-insulating GaAs substrate 30, p-type GaAs 31, p-type AlGaAs 32, undoped AlGaAs 33, undoped GaAs 34,
An n-type AlGaAs 35 and a p-type AlGaAs 36 are formed. In the HBT portion, p-type AlGaAs 36 is an emitter layer, n-type AlGaAs 35 and undoped GaAs
2DEG (two-dimensional electron gas) 3 formed at the interface 34
8 is a base layer, undoped GaAs 34, undoped A
lGaAs33 is a collector layer, p-type AlGaAs32,
The p-type GaAs layer 31 is a sub-collector layer. In the FET part, p-type AlGaAs 36 is a gate layer, n-type AlG
2DEG (two-dimensional electron gas) 38 formed at the interface between aAs 35 and undoped GaAs 34 has an n-type channel layer, undoped AlGaAs 33 has an effect of suppressing a short channel effect, and p-type AlGaAs 32 and p-type Ga
The As31 layer is a p-type buffer layer, and there are several ways to apply a potential to this layer as described later. In order to reduce the source gate resistance Rsg and the base resistance rbb ',
An n-type ion implantation layer 37 that is in ohmic connection with 2DEG is formed. The electrode portions are an emitter electrode 40, a base electrode 41, a collector electrode 42, a gate electrode 45, a source electrode 43, a drain electrode 44, and a substrate bias electrode 46, respectively. The feature of the device fabrication process is that the emitter electrode and gate electrode, base electrode and source / drain electrode, and collector electrode and substrate bias electrode can be fabricated in the same process (lithography process and electrode process). There is also an advantage that it can achieve a great reduction.

It should be noted here that the 2DEG layer 38 does not necessarily have to be open when no bias is applied between the source and gate (between the base and the emitter). That is, FE
In terms of T, the threshold voltage Vth can take a positive or negative value as needed.

In the following description, a typical Vth is 0.0
The description will be made with a value of about 0.1 V from V in mind (this point will be described in detail in the operation).

FIG. 2A shows an energy band diagram in a state where the emitter base is forward-biased and 2DEG (two-dimensional electron gas) 38 is induced at the interface between the n-type AlGaAs 35 and the undoped GaAs 34. As described above, the p-type AlGaAs collector layers 33 and 32 are
Undoped GaAs 38 and p
It becomes difficult to be implanted due to a potential barrier due to a discontinuity ΔEc in the conduction band at the heterojunction interface with the type AlGaAs collector layer 33.

As shown in FIG. 1 (a), complementary B
The iFET is composed of one pnp-DHBT10 and an enhancement type n-channel FET, and electrically connects a drain portion of the FET and a bipolar collector portion.
The gate portion of the FET and the base portion of the bipolar are electrically connected. Further, the emitter of the DHBT (double hetero bipolar transistor) is the first power supply, the source of the FET is the second power supply (in this case, ground), the collector of the DHBT and the drain of the FET are the output, the base of the DHBT and F
The gate of ET is connected to the input. Further, the substrate bias electrode SB of the FET is usually connected to the source of the FET.

The basic operation of this logic circuit is silicon CMOS
Is similar to That is, when the input is at a voltage (high level) close to the first power supply (high level), the pnpDHBT is off, the nFET is on, and the output is close to the second power supply (low level). Conversely, when the input is at a voltage close to the second power supply (low level), pnpDHBT is on and nFET
Is turned off and the output is close to the first power supply (high level).

This logic circuit differs from the silicon CMOS in that one side is a pnp bipolar transistor, and therefore the following problems arise.

(1) When the DHBT is on, the transistor is in the saturation region. For this reason, the carrier accumulation effect becomes a problem as in the case of the DCTL. However, as described above, due to the fact that the base and the collector are heterojunctions and the above-mentioned characteristics of the 2DEG-HBT, the effect of the accumulation of minority carriers during saturation (in this case, the electron in the collector layer). Number and holes in the base layer) are negligibly small.

(2) The operating speed of the pnp transistor is:
It has been considered that it takes time for holes to pass through the base, and high-speed operation is impossible. However, in the case of 2DEG-HBT, the emitter (p-type AlGaAs 36 in FIG. 1 (b)) and the metallurgical base (FIG.
Heterojunction between (b) n-type AlGaAs 35 and the real base 2DEG felt heterobarrier (n-type AlGaAs 35 and undoped)
Since the conduction band discontinuity ΔEc) of GaAs 34 is large, the delay time of the emitter region is negligibly small. That is, electrons, which are minority carriers, can hardly enter the emitter region. Also, since the thickness of 2DEG is as thin as 10 nm, the base traveling time is so small that it can be ignored.

(3) Power supply voltage. The voltages of the first and second power supplies are determined in consideration of the base rise voltage of the DHBT and the gate rise voltage of the FET. Usually, these minimum values of the rising voltage are set as the voltages. In this case, DHBT and F
Even when the ET is in the ON state, the base and gate voltages of the next-stage DHBT and FET are lower than the rising voltage, so that it is not necessary to drive a large current and the power consumption is small. On the other hand, it is possible to set the voltage higher than the rising voltage, and power consumption is increased, but higher-speed operation is possible. In this case, power consumption can be reduced by inserting a resistor in series with the base or gate as needed for input clamping. Although the same effect can be obtained by inserting a resistor in series with the emitter, it is necessary to consider that the output potential changes by the voltage drop of the emitter resistor.

(4) Number of fan-outs. When the DHBT is on, the base current is supplied from the preceding FET. For this reason, the number of fan-outs is determined by the saturation drain current of the FET. Conversely, the maximum fan-out number is determined and the gate width of the FET is determined. DHBT and F from the balance of drive capacity
When the saturation current of the ET is the same, the maximum fan-out number is ideally the current amplification factor hfe of the DHBT.
It is about one third to one fourth of the hfe. DHBT
Hfe of 100 or more can be obtained, so there is practically no problem.

Next, the input / output characteristics of the single inverter shown in FIG. 2B will be described. The vertical axis is the output voltage Vout, and the horizontal axis is the input voltage Vin. Each amplitude is a second power supply
(In this case, 0V at ground) from the first power supply (in this case,
Vdd V). Complementary BiF
As easily understood from the configuration of the ET, Vin = Vg, Vout =
The relationship of Vsd always holds, and when the input voltage Vin is 0
At V, the base-emitter voltage Vbe is Vdd and Vin
Is Vdd, the base-emitter voltage Vbe is 0V.
In this figure, the case where the threshold voltage Vth of the FET is a positive value is considered. The input / output characteristics of a single inverter will be described separately for five regions [(I), (II), (III), (IV), (V)].

(I) While Vin is between 0 V and the threshold voltage Vth, the output voltage is fixed at Vdd because the n-channel FET 20 is off.

(II) Vin is between Vth and Vtc (Vtc is a gate voltage at which the value of the bipolar collector current matches the value of the drain current of the FET.) Since the n-channel FET 20 starts to turn on, the drain of the FET flows. At the beginning, the output voltage starts to drop from Vdd.

(III) When Vin is Vtc The collector current in the bipolar active region is equal to the drain current in the FET saturation region.

(IV) When Vin is between Vtc and Vdd-Vtp (V
tp is a base-emitter voltage Vbe at which the bipolar collector current Ic is turned on. The bipolar collector current starts to turn off and the output voltage becomes zero.
Start approaching V.

(V) While Vin is between Vdd-Vtp and Vdd, the bipolar turns off and the output voltage becomes 0V.

By the way, in FIG. 2 (b), a region where the base collector is at the same potential, that is, a region where Vbc is 0 V, and a region where Vbc is positive is a region where the base collector is saturated.

In the above description, a complementary logic circuit using a pnp hetero-bipolar transistor and an n-type field effect transistor has been described. However, it is obvious that a similar complementary logic circuit can be realized using an npn hetero-bipolar transistor and a p-type field effect transistor. .

As described above, the basic invention part of the complementary BiFET using the DHBT having the extremely small minority carrier accumulation effect at the time of saturation and the FET having the different polarity has been described. Next, considering the case of actually constructing a circuit, (1) the characteristics of a complementary BiFET as a device (2) the conditions imposed to bring out high performance (3) the operation analysis and problems of a connected inverter (4) ultra-high speed A detailed description will now be given of improvements and the like for making an integrated circuit suitable for high integration with very low power consumption.

First, from the viewpoint of static current-voltage characteristics using the bipolar characteristics of a common emitter and FIG. 5 (a), when the bipolar characteristics are regarded as the FET operation, the collector current Ic becomes larger than the source / drain current Ids. When the emitter-collector voltage Vce is defined as the source-drain current Vds, the emitter-base voltage Vbe is defined as the gate voltage Vg, and Vbe at which the collector current is cut off is defined as Vtp, they correspond to the threshold voltage Vth of the FET. However, strictly speaking, the bipolar I
c is controlled by the base current Ib, and Vbe
Therefore, the correspondence with the FET is only an analogy. As described above, the bipolar characteristic is changed to F
The features when considered as ET are listed below. While the emitter-base voltage Vbe changes by 200 mV from 1.5 V to 1.7 V, the collector current Ic can be changed by two digits. That is, when viewed as an FET, the threshold voltage is Vtp ≒
When viewed from a FET using a compound semiconductor of 1.5 V and a normal compound semiconductor, it is an extremely high enhancement type FET and has a logic amplitude Δ
Even though V is a small value of 200 mV, the current range can be changed by two digits, and compared to the FET of the same size,
A significant feature is that the transconductance is about two orders of magnitude higher.

The active region having the Ic-Vce characteristic shown in FIG. 5A is taken out, and the collector current Ic and the emitter-base voltage Vb are extracted.
Figure 5 (b) shows the relationship of e. The bipolar transistor is characterized in that the rising characteristic of the collector current Ic from the threshold voltage Vtp is exponential (.about.EXP (.beta.Vbe)), which means that the collector current Ic is switched largely with a small logic amplitude .DELTA.V. That's why.

[0047]

Ic = AEXP (βVbe) (Equation 1) where A is a constant depending on device dimensions and material structure, β
= Q / kT. q is unit charge, k is Boltzmann's constant, and T is absolute temperature. In the large current region, the characteristics deviate from the exponential function due to the emitter and base resistance.

In the FET, the source / drain current Idss in the saturation region is approximately a quadratic function of Vg-Vth in the large current region.

[0049]

Idss = K (Vg-Vth) ² (Equation 2)

In the vicinity of the threshold voltage, the value deviates from the quadratic function. For this reason, it is customary for Vth to plot the square root of Idss against the gate voltage Vg and determine Vth as an extrapolated value. This is shown in Fig. 5 (b). In this case, when Vth is considered positively, the residual source / drain saturation current Idssres at the gate voltage Vg = 0.0 V greatly affects the standby power of the complementary BiFET as discussed below.

When a compound semiconductor heterojunction is used,
Transistor width W = 10 μm, gate length Lg = 0.
At 1 to 0.5 μm, the maximum K value is about 5 to ²⁰ mA / V ² . On the other hand, in the case of a bipolar transistor having the same dimensions, when converted into a K value, it is about 25 to 50 mA / V ^2, which is one digit or more. Idssres depends on the device structure, Vth and the like, and can be set in a range of approximately 0.1 to 50 μA.

Normally, the logic amplitude ΔV of a 2DEG-FET is V
When operating at g-Vth = 400 mV to 800 mV, the circuit operation speed is often the fastest. At this time, the source / drain saturation current Idss is 1 to 7 mA level.

Transistor width W = 10 μm and gate length
Lg = 0.1-0.2 μm silicon n-channel M
In the OSFET, Vg-Vth = 1.5 V (power supply voltage 2 V
Source / drain saturation current Idss up to 3
mA. For a p-channel MOSFET:
It is about 5 mA. That is, when the 2DEG-HBT is considered as an FET, an n-channel MOS having a power supply voltage of about 2 V
A current approximately the same or approximately twice that of the FET can flow, and the logical amplitude in this case is 1/3 to 1/4. That is, when the GaAs-based 2DEG-HBT is viewed as an FET, the load driving capability is about the same to about twice and the speed is several times faster than the n-channel MOSFET. In the complementary BiFET, the companion of the FET is
High speed PNp bipolar with high load driving capability,
It can be at least one order of magnitude faster than a CMOS LSI.

Next, taking the single inverter shown in FIG. 1 (a) as an example, the threshold voltage V
th, the conditions imposed on the bipolar collector current cutoff voltage Vtp and the power supply voltage Vdd will be discussed. FIG. 6B shows an operation region of the FET / bipolar with respect to the input voltage Vin to the inverter. When the input potential is 0 V in a single inverter, the bipolar turns on, and the FET portion becomes Vg = 0 V,
A source / drain saturation current Idss (Vg = 0 V) flows.
The power consumption P at this time is

[0055]

## EQU3 ## P = Idss (Vg = 0V) * Vdd (Equation 3), and it is important to determine the value of Idss (Vg = 0V) according to the circuit design. For example, when Vth> 0V, Idss
Becomes Idssres,

[0056]

## EQU4 ## The power of P = Idssres * Vdd (Equation 4) is consumed. When Vth <0 V, Idss of Vg = 0 V becomes larger than Idssres, but Vg−
Since the current value at Vth can be increased with respect to the same Vg, the performance of the FET can be improved, so that the power consumption is increased but the speed is increased. In normal applications, when aiming for low power consumption at the expense of some high-speed operation,

[0057]

## EQU00005 ## It is desirable to use in the range of 0V.ltoreq.Vth.ltoreq.0.15V (expression 5) On the other hand, in the case of achieving high-speed operation at the expense of power consumption, it is desirable to use the threshold voltage Vth with a negative value.

The main term of the threshold voltage Vth of the 2DEG-HBT as an FET is approximately

[0059]

Vth ≒ Eg (AlGaAs) -ΔEc-qNDd ² (1 + ND / NA) / (2ε ₁ ) + sqr [2ε ₁ qNAA (2kT <ln (NAA / ni)> / q + VSB) + X ] / Ε ₁ -Y (Equation 6)

[0060]

X≡NAA (NAA / Nβ-1) (qNβWcd / ε ₁ ) ² / Nβ (Equation 7)

[0061]

(8) Y８ (NAA / Nβ-1) (qNβWcd / ε ₁ ) (Equation 8) Fig. 1 (b) and Fig. 2 (a)
I'm thinking of a structure to show. Where sqr is the square root, l
n is the natural logarithm, Eg (AlGaAs) is the p-type AlGaAs layer of the emitter
36 energy band gap, ΔEc is the p-type of the emitter
Undoped G with AlGaAs layer 36 and 2DEG 38 formed
It shows the jump of the conduction band with the aAs layer 34. ND and d are the doping level and thickness of the metallurgical base n-type AlGaAs layer 35. NA is the doping level of p-type AlGaAs of the emitter. ε ₁ is the dielectric constant of AlGaAs, ignoring the difference in Al composition between the emitter, base, and collector layers. Wc
Is the undoped GaAs, AlGaAs layer 3 of the undoped collector layer.
The film thickness of 4,33, NAA and ni are p-type AlGaAs layer and sub-collector layer 3.
2 are the impurity concentration and the intrinsic carrier concentration, and Nβ is the impurity concentration of the undoped GaAs and AlGaAs layers 34 and 33. Furthermore,
VSB is a substrate bias potential for controlling the potential of the p-type buried layer (p-type AlGaAs layer collector layer) 32. This role will be discussed later.

Since the threshold voltage Vth of the 2DEG-HBT FET can be approximately described by Equation 6, by designing the specific value of the epi structure, the value of Vth can be adjusted according to the intended circuit type and circuit performance. Can be set.

By the way, in the case of 2DEG-HBT, bipolar and
The epi structure of the FET is the same. Therefore, the fact that the threshold voltage Vth of the FET is positive means a normally-off bipolar transistor in terms of a bipolar transistor. In other words, a state where punch-through occurs between the emitter and the collector. That is, the punch-through collector current Icres flows even when Vbe is small. However, in a region where Vth is as small as about 0 to 0.15 V, the punch-through collector current Icres is extremely small and can usually be ignored. When Vbe is small, 2DEG induces only a small amount, so that the base resistance rbb 'increases. But,
In a region where the collector current density is sufficiently large, 2DEG can be sufficiently induced, and therefore rbb 'becomes small reflecting the high mobility of 2DEG.

This is because 2DEG is formed on the collector layer.
This is a feature of EG-HBT. FIG. 7 is an Ic-VcE characteristic diagram.

Next, FIGS. 8A to 8E show a single inverter FET.
2B shows changes in the bipolar state corresponding to (I)-(V) in FIG. That is, the input voltage Vin is initially 0
At V, a small current flows through the FET (FIG. 8).
FIG. 8 (e) shows a state in which both the FET and the bipolar are turned on (FIG. 8 (c)), and then the bipolar is turned off and the output potential becomes close to 0V as shown in FIG. 8 (e). At this time, FIG. 9A shows the inverter currents Ic and Id flowing while the input potential changes from 0 V to Vdd. The switching of the inverter is performed when the input potential is (I) in FIG.
It is divided into three types shown in (I), (III) and (VI).

(II) Vth <Vin (Vg) <Vt
c This region is in the state shown in FIG. The current flowing through the inverter is calculated using the saturation current Idss of the FET.

[0067]

Idss = K (Vin−Vth) ² (Expression 9)

(IV) Vtc <Vin (Vg) <Vdd-Vtc This region is as shown in FIG. 8D. The current flowing through the inverter is a bipolar current Ic in the active region,

[0069]

Ic = A {exp [−β (Vin−Vdd + Vtp)] − 1} (Expression 10) The region (III) is a state where the source / drain current Idss in the saturation region of the FET matches the collector current Ic in the bipolar active region.

At this time, it should be noted that when the input potential is low, the bipolar is on and the base current Ib flows,
When the input potential is high, the FET is ON and the gate current Ig flows. This is shown in FIG. 9 (b). These two currents Ig and Ib are crucially different from those of the CMOS inverter, and cause the standby power consumption of the circuit to increase.

Next, conditions under which switching is performed at high speed will be discussed. If the input logic amplitudes of the FET and bipolar in the switching process are Δf and Δb, respectively

[0072]

Δf = Vtc−Vth (Expression 11)

[0073]

Δb = (Vdd−Vtp) −Vtc (Expression 12) Δf and Δb must first be positive values. In order for the current flowing in the switching process to drive the load around the inverter sufficiently fast, it is necessary to allow sufficient current to flow through each of the FET and the bipolar. That is, Δf and Δb have appropriate value ranges.

In the GaAs / AlGaAs heterostructure,

[0075]

[Expression 13] Δf = 400-600 mV (Expression 13)

[0076]

Δb = 100-300 mV (Expression 14)

[0077]

Vtp = 1.4-1.5 V (Equation 15)

[0078]

Vth = 0-0.15 V (Equation 16)

[0079]

Vdd = 1.9−2.55 V (Equation 17) where Vdd≡Vth + Δf + Δb + Vtp.

The effective amplitude ΔV of the input potential is

[0081]

[Expression 18] When defined as ΔV≡Vth + Δf + Δb (Expression 18), Vth = 0.1V, Vtp = 1.4V, Δf = 500 mV, Δ
b = 150 mV, Vdd = 2.15 V, ΔV = about 750 mV are standard values.

The current-voltage characteristics at the time of switching shown in FIG. 9 (a) are as follows.
It can be said that the smaller the swing width from to Vdd-Vtp, the higher the performance.

K value (FET and bipolar) compared to CMOS
As discussed above, complementary BiFETs can be made larger, so they have higher speed and lower power consumption than CMOS.

Next, the bipolar base current Ib and FE
In order to investigate the effect of the gate current Ig of T on the complementary BiFET, a characteristic analysis of the three-connected inverter is performed with reference to FIG. At this time, in FIG. 10 (a), the three inverters are referred to as left, middle, and right inverters from the left. Diagram through operation analysis of multiple-connection complementary BiFET
We clarify the problems of the single inverter shown in 1 (a) and try to improve it. In FIG. 10 (a), the current path is shown by a solid line and a broken line when the leftmost inverter input is High (written as H) and the third inverter output is Low (written as L). ing. The solid line indicates a state where a large amount of current flows, and the broken line indicates a state where a small amount of current flows. The bipolar base current and collector current are denoted by Ib and Ic, respectively, and the source / drain current and gate current of the FET are denoted by Id and Ig, respectively. The subscript attached to each current indicates the location of the inverter. Here, attention should be paid to the FET characteristics of the 2DEG-HBT. The junction gate 2DEG- of FIG. 1 (b)
This is the role of the substrate bias electrode 46 of the FET. As is well known, the p-buffer layer of an n-channel FET has not only a positive effect such as suppression of a short channel effect but also a negative effect such as an increase in parasitic gate capacitance. In this case, it is rare that the potential of the p-buffer layer is set to a floating state in which the potential is not fixed, and is usually fixed to the source potential. However, the junction gate 2DEG-FET of FIG. 1B can be regarded as a bipolar transistor having two independent base electrodes. In this case, the p-buffer layer functions as a collector layer. The big question is what to do.

There are roughly three cases.

(1) Make it equal to the source potential. (2) Make it equal to the gate potential. (3) The p-buffer layer at the FET is eliminated by devising the device structure.

In particular, in the case of (1), the gate current Ig is the sum of the base current and the collector current corresponding to a so-called Gummel plot when the base and the collector are short-circuited, and is applied to the normal junction gate FET ((3)). Corresponding) gate current. In the case of (2),
This is a gate leakage current when there are two gates sandwiching the active layer.

In the following, for the purpose of extracting the problem relating to the power consumption of the complementary BiFET of the present invention shown in FIG.
A qualitative analysis of the characteristics of an isolated three-connected inverter is performed.
Here, “isolated” ignores the effect of the current Ig0 flowing into the input of the left inverter and the current Id3 flowing into the output of the right inverter of the three-connected inverter in FIG. 10A. Although there are the above three cases for the p-buffer layer potential of the FET, discussion will be made assuming the case of (1). This is the most power consuming in this case, so if we discuss this case, the other two
This is because power consumption is reduced. FIG. 10 (b) shows the input / output characteristics of the middle inverter, compared to FIG. 2 (b). Vb in the figure
If the input potential at the point where the c = 0V line (indicated by the dotted line) and the inverter input / output curve cross is defined as Vout ² ,
The state of the inverter characteristic (III) corresponds to Vout ² in FIG. 8 (c). The vertical axis in FIG. 10B is the output potential Vout, which is the source / drain voltage Vsd of the FET portion. The input potential Vin on the horizontal axis is the gate voltage Vg of the FET portion. FE
In the IV characteristic of T, if the source-drain voltage transitioning from the unsaturated region to the saturated region is defined as Vss, Vss becomes Vg-Vth
(Indicated by the dotted line in the figure), and Vg-Vth =
At 0V, Vss = 0V. If the input potential at the point where this function intersects with the inverter input / output curve is defined as Vout ³ , this is obtained in the state of the inverter characteristic (III) in FIG.
Vout ³ of FIG.

Next, the middle complementary BiFE
An analysis of the current-voltage characteristics on both sides of T is shown in FIGS. At this time, FIG. 11 (a) to FIG. 17 (a)
1 (b) -FIG. 17 (b) shows the current-voltage characteristics in the right side and the middle. The conservation law holds for the current corresponding to each state. 11 (a) and 11 (b) show the current-voltage characteristics when the input voltage is the lowest, that is, when Vin = VL. At this time, the base current Ibmax and the gate current Igmax flow as the standby current. A state diagram in which the collector current Ic2 and the source / drain current Id2 of the middle complementary BiFET match through the states of FIGS. 12, 13, and 14 as the input potential increases.
After 15 (b) (let the maximum current flowing at this time be Imax),
When the input voltage is the highest, that is, when Vin = VH, the current-voltage characteristics settle in the states shown in FIGS. 17 (a) and (b). Also at this time, the base current Ibmax and the gate current Igmax flow as the standby current. As can be seen immediately, Ibmax and Igmax also depend on the device size, but are easily reduced from several mA to several tens mA in a normal logic circuit or storage circuit. The only way to reduce this is to lower the power supply voltage Vdd.
/ The logic amplitude of the bipolar is reduced, and the speed of the circuit is reduced. In this case, the S.I. F
Ujita et al. have the same problem as the complementary GaAs FET. In order to use the complementary BiFET with low power consumption, the current Imax at the time of inverter switching is
It is necessary to improve the structure so as to reduce Ibmax and Igmax as much as possible while ensuring sufficient values.

However, what should be noted here is that the power consumption is almost the same as that of the complementary circuit of the GaAs FET, and the normal compound semiconductor GaAsFE is used.
DCFL logic using a depletion type FET of T as a load and an enhancement type FET as a driver (eg, M. Abe et al., HEMT LSI technology for high speed c
omputers, Tech.Dig.GaAs IC Symposium, p.158, 1983.
Please refer to. ), About one-tenth of the power consumption can be secured and the speed can be increased by 2 to 4 times.

However, compared to CMOS logic, the power consumption is nearly ten times larger.

The problems clarified by the above analysis are as follows: (1) In order to operate the bipolar transistor, it is indispensable to supply a base current, and reducing the base current leads to lower power consumption. Is essential.

(2) In making the 2DEG-HBT an FET,
A device structure that suppresses gate leakage current is indispensable for reducing power consumption.

(3) The input and output of the inverter are unbalanced. That is, the effective input voltage range is 0-1V
To the extent, the output is too wide, up to 0-Vdd. It is.

Next, two measures for this improved method will be described.

In order to operate the bipolar transistor, the base current cannot be reduced to zero. Therefore, Fig. 18 (a)
Devices with current-voltage characteristics as shown in (Maximum current I
o), and replaces the maximum base current Ibmax that flows when Vbe = Vdd with Io. By doing this,
The maximum current flowing through the base is Io. For example, Io
As a result, the power consumption can be suppressed by designing to 0.1-100 μA. This value of Io is an order of magnitude smaller considering that the maximum base current Ibmax is usually several mA to several tens mA. However, when the base current is Io, the high speed of the bipolar transistor cannot be maintained unless the collector current Ic0 is sufficiently large.

However, in this case, the collector current decreases as the base current decreases, and the load driving capability also decreases. Therefore, it is necessary to design the HBT so that the current amplification factor hfe has a huge hfe of about 1000 to 10000. There is. When Io = 1 μA, hfe = 1000-3000 is required. In other words, the maximum flowing collector current is

[0098]

Icmax = hfe * Io (Equation 19) The power P due to Io is

[0099]

P = Vdd * Io (Equation 20), and when the power consumption is determined according to the requirements of the system, the maximum base current Io is determined accordingly, and the Icmax is determined according to the required speed. The hfe to be realized is also determined, and the device structure is determined.

By including a device (current limiter) for limiting the base current in this way, the Gummel plot when the base collector is short-circuited is shown in FIG.
It changes as shown in. That is, since the base current is limited by Io, the collector current also saturates accordingly. Figure 18 (b), when there is no current limiter (dotted line)
(Solid line). Here, it should be noted once again that the collector current Ic is limited to Icmax = hfe * Io by the base current Io, so that the current amplification factor hfe is adjusted according to the circuit speed requirement so that the load driving capability does not decrease. It is necessary to largely decide.

On the other hand, the gate leakage current Ig can be avoided by inserting a diode in the gate in series. That is, FE
Since the voltage applied to the gate of T can be set to about 0-1 V, I
The gmax can be designed from several mA to several tens mA, for example, 0.1-100 μA. The value of the gate leakage current is a parameter that can be designed although it depends on the voltage shift amount ΔV of the diode, the power supply voltage Vdd, and the shape of the diode. At this time, it is necessary to design so that the capacity of the diode does not significantly reduce the speed of the circuit. Further, this diode is not preferable from the viewpoint of high speed in the case of a pn junction type diode in which an effect of accumulating minority carriers occurs. Since a compound semiconductor can form a favorable heterojunction, diode characteristics can be realized using the heterojunction, which will be described in detail in Examples. Here, it is represented by the word diode. The voltage shift amount ΔV is determined from 0 V to 1-2 V as intended by the designer. According to the position where the diode is inserted, there are two types of concrete inverters shown in FIGS. 19 (a) and (b). The voltage shift amount ΔV of the diode corresponding to FIG. 19A is represented by ΔVgd, and the voltage shift amount ΔV of the diode corresponding to FIG. 19B is represented by ΔVdd. In the case of FIG. 19A, the diode is directly connected to the gate of the FET. However, in this case, the input / output potential of the inverter is 0-V
Since it swings in the range of dd, the logic amplitude becomes unnecessarily large.

Therefore, as shown in FIG. 19 (b), by inserting a diode on the collector side of the bipolar, the range of the input / output potential of the inverter can be changed to 0− (Vdd−ΔVdd). The imbalance in output characteristics can be improved. The effect of this voltage shift ΔVdd on circuit performance is:
A 3-input NAND circuit and a 3-input NOR circuit described below
When three ETs and three bipolars are stacked vertically, a problem arises depending on whether the power supply voltage is sufficient. Therefore, in the above description, it is assumed that only one diode is inserted. However, the diode may be replaced with a plurality of diodes according to the value ΔV of the voltage amount to be shifted. Furthermore, FIG.
As shown in (a), the two types shown in FIGS. 19 (a) and 19 (b) may be used in combination. The method of forming the diode and the value of the voltage shift amount ΔVg will be described in detail in Examples.

The improvement of the operating characteristics of a complementary BiFET in which such a diode is inserted will be described with reference to FIGS. FIGS. 21 (a) and 21 (b) show examples of the improvement of the current-voltage characteristics of the multiplexed inverter. This is shown in Fig. 11 (a), (b)
Corresponding to Multiple-connected inverter using complementary BiFETs with diodes inserted as shown in Figures 18, 19 and 20
When the input is low and the output is high in (Fig. 10 (a)), the current-voltage characteristics of the left and middle inverters are shown in Fig. 21 (a).
As shown in FIG. 21 (a), the base current Ib1 is suppressed to Io due to the current limiter, and the source / drain current of the FET whose gate voltage is high (showing the IV characteristics by the dotted line) becomes Io. The source / drain voltage Vsd gives the low level VL of the inverter. On the other hand, the current-voltage characteristics of the right and middle inverters are shown in FIG. 21 (b). Due to the diode inserted in the collector, an offset voltage ΔVdd is generated in the bipolar Ic-Vce characteristic. On the other hand, due to the diode connected to the gate of the FET, the gate leakage current Ig2
Rises from Vfn by ΔVgd. At this time, the flowing current is Ig0. The IV characteristic when no diode is inserted is shown by the dotted line in the figure. At this time,
The high level VH of the inverter is: (1) When Vfn + ΔVgd + ΔVdd ≤ Vdd

[0104]

[Equation 21] Vfn + ΔVgd ≦ VH Vdd−ΔVdd (Equation 21) (2) When Vfn + ΔVgd + ΔVdd> Vdd

[0105]

VH２２Vdd (Expression 22)

Next, FIGS. 22 (a) and 22 (b) show examples in which the IV characteristic of the middle inverter is determined. This is
This is the state corresponding to FIGS. 8 (b) and (c). At this time, the state diagram
22 (b)

[0107]

(23) When designing in the range of Vout2−Vout3> ΔVdd (Equation 23), the speed of the circuit is increased.
At this time, the IV characteristics of the inverter itself shown in FIG. 9A basically do not change. However, in the leak current shown in FIG. 9B, Ibmax is suppressed to Io and Igmax is suppressed to Ig0.

In general, an arbitrary logic circuit is a NAND or N
It is well known that OR can be realized if it can be configured. Therefore, the present invention relates to a three-input NAND circuit (FIGS.
FIG. 27 shows a case where the present invention is applied to a three-input NOR circuit (FIGS. 27 to 30). Next, general conditions for operating these circuits at high speed will be described. Inverter characteristics, Fig. 8
(C), that is, the source-drain voltage Vss at which the single FET saturates in the region (III) and the emitter-collector voltage at which the bipolar shifts from the saturated region to the non-saturated region are Vcess.

In a NAND circuit, in order for a three-input NAND circuit to operate at high speed,

[0110]

It is necessary to satisfy 3Vss + Vcess + ΔVdd ≦ Vdd (Equation 24)

On the other hand, in a three-input NOR circuit,

[0112]

It is necessary to satisfy Vss + 3Vcess + ΔVdd ≦ Vdd (Equation 25)

To maintain the performance of the FET, ΔVgd
The smaller the better. When actually configuring a circuit, it is necessary to consider the distribution of ΔVdd and ΔVgd according to the purpose.

As described above, by inserting a current limiter and a diode, the power consumption during standby can be reduced by μW
To several tens of microwatts. Therefore, in the example of a logic circuit using a complementary BiFET, which is the basic configuration of the circuit, an ultra-high speed of about 1-10 psec per gate and 10
Ultra-low power consumption of less than μW can be realized in the same way. Next, the complementary BiFET of the present invention is added to the memory circuit.
31 and 32 show circuit configurations in the case of using. Figures 31 and 32 show SRAM (Static Random Access Memory)
An example in which the present invention is applied to the basic memory circuit shown in FIG. Here, the operation of each circuit will be individually described, but any circuit can operate at high speed with low power consumption. Regarding the device process, in the case of the 2DEG-HBT, the FET / bipolar can have the same epi structure, so that the number of times of photolithography can be reduced to about ／ and the cell area can be reduced to about ２− to ３.

Such a device cross-sectional structure forming a circuit will be described in detail in Examples.

Further, a feature of the 2DEG-HBT is that the above-described various circuits can be realized with the same epi structure and the various circuits described above can be realized by changing the mask pattern only by changing the mask pattern. . In Si (silicon) LSI, ion implantation is mainly performed on the silicon substrate,
It is characterized by making various elements and circuits. However, compound semiconductor GaAs heterojunction devices
The greatest feature in the process is that it is formed using epi technology such as E, MOCVD, and MOMBE. Therefore, the essential parts of the required elements must first be formed. At this time, the fact that more elements can be formed simultaneously with the same epi structure is useful for designing a target system.
2DEG-HBT is an element that has such a possibility.

Finally, the offset voltage will be described.
In a normal DHBT, the difference between the rising voltage of the base-emitter current and the rising voltage of the base-collector current, etc.
It is known that an offset voltage Vceoff as shown in FIG. 6A occurs in the c-Vce characteristic. like this,
The operation analysis of the complementary BiFET in the presence of the offset voltage Vceoff basically indicates that Vceof
It can be understood that f has been added. Offset voltage Vceoff
Can be determined by the epi structure of the device cross section according to the circuit performance (speed, power consumption) to be realized.

Also, in place of the current limiter, FIG.
As shown in (b), the power consumption can be reduced by inserting the resistor RB in the bipolar base region. However, time is used for charging and discharging the high resistance RB, and the speed is slightly reduced. Also, if the base current is limited by Io flowing through the current limiter, when the transistor is turned on, the rising characteristic of the current limiter is used, so that the resistance is low and the speed is low. However, when the transistor is turned off, the base current is limited by Io, so that if a large load is applied to the base portion, the speed is reduced, so that care must be taken in circuit design.

[0119]

The present invention will be described in more detail with reference to the following examples. In particular, epi structure and current limiter (Fig. 18 (a))
And diodes will be described in detail.

<Example 1> First, a specific epi structure of the element structure (FIG. 1 (b)) which is a prototype of the present invention shown in FIG. 1 will be described. P-type Ga containing 3 × 10 ¹⁹ / cm ^{3 of} Be on a semi-insulating GaAs substrate 30 by MBE (molecular beam epitaxy).
As 31 400 nm, p-type AlxGa with same doping level
1-xAs (x = 0.45) 32 to 400 nm, undoped AlyGa1-yAs (y
= 0.45) 33 for 300 nm, undoped GaAs34 for 30 nm, Si
3 × 10 ¹⁸ / cm ³ containing n-type AlzGa1-zAs (z = 0.30) 35
25 nm, p-type AluGa1-uAs containing Be at 2 × 10 ¹⁹ / cm ³ (u = 0.4
5) 200 nm of 36 was formed. Thereafter, a high heat-resistant metal made of WSi was applied to a thickness of 300 nm to form a gate electrode 45 of the junction gate 2DEG-FET and an emitter electrode 40 of 2DEG base PNpHBT. Next, to form the base, source and drain, p-type AluGa1
-uAs (u = 0.45) 36 was removed, Si was ion-implanted at an acceleration voltage of 30 keV by a dose of 1 × 10 ¹³ / cm ² , and lamp annealing was performed at 800 ° C. for 30 seconds to activate Si. An ion implantation region 37 is formed for the purpose of reducing the base resistance and the source gate resistance. Next, the source electrode 43, the drain electrode 44, and the base electrode 41 were formed using normal AuGe / Ni / Au. Next, using the emitter base region and the FET region as a mask, the semiconductor regions 35, 34, and 33 were removed by etching. Further, in order to electrically separate the elements, the FET portion and the bipolar portion were removed by etching to the substrate.

A collector electrode 42 and a substrate bias electrode 46 were formed using AuZn / Au. Next, the bipolar base electrode was connected to the gate electrode of the FET, and the bipolar collector electrode and the drain electrode of the FET were connected using the usual two-layer wiring technique. In this embodiment, after connecting the substrate bias electrode 46 of the FET and the source electrode 43 of the FET, they are grounded,
The bipolar emitter electrode was connected to a power supply voltage Vdd (in this case, 2.0 V). As the p-type impurity, besides Be, C (carbon) or Mg (magnesium), which hardly diffuses, can be used. As a crystal growth technique, MOMBE, MOCVD, etc. can be used in addition to MBE.

<Example 2> The threshold voltage Vth of the 2DEG-HBT of this prototype as a FET varied ± 0.1 V around 0.1 V in the sample having a gate length of 0.7 μm. Therefore, in order to improve the controllability of the threshold voltage Vth and reduce the source-gate resistance Rsg, the first embodiment is used.
Followed by Be containing 2 × 10 ¹⁹ / cm ³
p-type 50-nm GaAs 55 and p-type containing 2 × 10 ²⁰ / cm ³ Be
20 nm of GaAs 56 was formed. Thereafter, after processing the gate portion, as shown in FIG. 34 (a), using a selective growth by MOCVD (metal-organic thermal decomposition), a thick n-type GaAs layer (Si doping) is formed in the source gate region and the base region. Level 3
× 10 ¹⁸ / cm ³ , thickness 160 nm) 50. At this time, Rsg
Was 80 Ω at a transistor width W = 10 μm. Vg-Vth =
At 0.6 V, transconductance Gm = 350 mS, Idss =
1.05 mA. As the bipolar characteristics, when the emitter size was 2 × 3 μm ² and the collector current Ic was 3.0 mA, the current amplification factor hfe was 1500.

<Embodiment 3> FIG. 34B shows an embodiment in which the current amplification factor hfe is increased. In order to realize a huge current amplification factor hfe with a 2DEG-HBT, it is basically necessary for the base 2DEG to further suppress the injection into the p-type AluGa1-uAs (u = 0.45) 36 emitter layer. Therefore, high-purity InwGa1-wAs (w
(In composition) 234 is inserted into the GaAs layer 34 by 20 nm during crystal growth. The process technology after crystal growth is described in Example 2.
Is the same as In composition w was selected to be 0.15. At this time, the current amplification factor was 15000 with the emitter dimensions of 2 × 5 μm ² .

Further, the p-type AluGa1-uAs 36 emitter layer Al
The composition u can be increased from 0.45 to a larger value. In such a strained heterojunction, the In composition is increased or the InwG
When the film thickness of a1-wAs (w is In composition) 234 is increased, the crystallinity deteriorates. For example, when the In composition w is 0.3, the film thickness is 10 n
m. The In composition can be graded and used instead of the GaAs layer 34.

<Embodiment 4> Another embodiment in which the current amplification factor hfe is increased is shown in FIG. Semi-insulating In
250 nm undoped AlInAs by MBE on P substrate 230
When 40 nm of undoped AlInAs-GaInAs superlattices 31 'after forming, p-type Al ₀ to 4 × 10 ¹⁹ / cm ³ containing _{Be. 48 In 0. 52 As} 32'
The 400 nm, further, an undoped _{Al 0. 48 In 0. 52} 400 a As 33 '
nm, an undoped Ga _{0. 47} In _{0. 53} a As 34 'grows 40 nm.
Next, n-type Al ₀ to 10 ¹⁹ / cm ³ containing _{Si. 48 In 0. 52 As} 35 ' 1
5 nm, p-type Al ₀ to ³ containing 4 × 10 ¹⁹ / cm to _{Be. 48 In 0. 52 As} 3
6 'to 200 nm, p-type Ga ₀ of the same impurity concentration. ₄₇ In _{0. 53} As55'
The 40 nm, further, p-type Ga ₀ to 10 ²⁰ / cm ³ containing Be. ₄₇ In _0.
53 As56 'was formed to a thickness of 20 nm. Thereafter, the emitter electrode 40 and the gate electrode 45 are processed, and after the p-type layer is removed by etching,
0 ¹⁹ / cm ³ n-type Ga ₀ containing. ₄₇ In _{0. 53} As50 'to 160 nm, MOCVD
It was formed using a method. After that, electrode formation, isolation between elements, and the like were performed using an AlInAs / GaInAs heterojunction process. At this time, the emitter size is 1 × 2 μm ² and the current amplification rate is 5
000. In the third and fourth embodiments, since InGaAs is used for the active layer of the FET, there is an advantage that the FET performance can be about 1.5 to 2 times that of GaAs.

The IEEE Transanctions on Electron Dev
ices, Vol. 38, No. 2, 1991 pp. 222-231
In the bipolar characteristics of DEG-HBT, the speed is determined by the hole collector transit time and the base collector parasitic capacitance charging time. When the emitter dimensions are 1 μm × 10 μm, the base collector parasitic area is 10 μm × 10 μm, and the undoped collector layer thickness is 150 nm, when the cut-off frequency is the highest, the base-collector parasitic capacitance charging time is the shortest.
There is also 0.75 psec. Two embodiments for reducing such a parasitic capacitance are shown in FIGS. 35 (b) and 36 (a).

<Embodiment 5> First, FIG.
The improvement will be described. p-type AlxGa1-xAs (x = 0.45) 32
After crystal growth, oxygen (O) is ion-implanted into the base collector region and the FET region, and annealing is performed to recover the crystallinity. Subsequently, the crystal growth of Example 2 is undoped with AlyGa1-
yAs (y = 0.45) Start from 33. However, since the p-buffer layer has disappeared, the Vth of the FET shifts to the negative side.
It is necessary to reduce the Si doping level of n-type AlzGa1-zAs (z = 0.30) 35 to 2 × 10 ¹⁸ / cm ³ . In this case 2DEG-HBT
Bipolar 2DEG turns on at Vbe = 0.5V, but the punch-through collector current is at a negligible level. The subsequent steps are the same as in Example 2. The conditions for ion implantation are, for example, a dose amount of 10 ¹³ / acceleration voltage of 150 keV.
It was cm ^2. At this time, the base collector capacitance is reduced by 45%, and the maximum value of the cutoff frequency is
At 250 nm, it was 120 GHz.

<Embodiment 6> Next, FIG.
The improvement will be described. In place of n + GaAs regrowth layer 50, graded layer 5 replacing GaAs with GaAs through InGaAs
After forming source, drain, and base electrodes using a non-alloy metal (for example, a high heat-resistant metal such as WSi), the junction area is reduced by setting the width of these electrodes to 0.5 to 2.0 μm. At this time, the base capacitance was reduced by 30%, and the maximum cutoff frequency was 90 GHz when the undoped collector film thickness was 250 nm.

The description of the present invention has been described assuming that a complementary BiFET is formed using 2DEG-HBT. Next, two methods for implementing a complementary BiFET with a similar device structure will be described.

<Embodiment 7> First, FIG.
Complementary B using EMT (high mobility transistor)
1 shows an embodiment of an iFET. In FET operation of 2DEG-HBT, if the pn junction gate structure is changed to the Schottky junction gate structure
Since the HEMT has a p-buffer layer, a description will be given of how to make a complementary BiFET with reference to Example 2. In the case of a Schottky junction gate structure
The main term of Vth must have a Schottky junction height Φbn instead of Eg (AlGaAs), so that the threshold voltage is about 0.5V deeper. Therefore, n-type AlzGa1-zAs (z
= 0.30) The doping level of 35 Si needs to be reduced to 2 × 10 ¹⁸ / cm ³ . In this case 2DEG-HBT bipolar 2D
EG turns on at Vbe = 0.5V, but the punch-through collector current is at a negligible level. After that, the process is FE
Remove the p-type AluGa1-uAs (u = 0.45) 36 from the T gate electrode,
Gate electrode 45 is formed of high heat-resistant metal, and n + GaAs layer is MOCV
Regrow with D. To reduce the gate resistance, a T-shaped structure may be used. At that time, the upper part of the T-shape is Mo / Au 4
Use 5 '. Other parts are the same as in the second embodiment. Alternatively, the film thickness of n-type AlzGa1-zAs (z = 0.30) 35 may be removed by etching only in the FET portion without changing the doping level.

<Eighth Embodiment> Next, FIG. 37 shows an example in which a Doped Channel is used in place of 2DEG. In Example 2, 10 nm of undoped GaAs (y = 0.45) 34, and 3 × 10 ¹⁸ / cm
³ Containing n-type GaAs338 at 10 nm, undoped AlzGa1-zAs
(z = 0.30) After forming 25 nm of 335, the emitter layers are stacked in the same manner as in Example 2. The subsequent process is the same as in the second embodiment. InuGa1-uAs instead of n-type GaAs 338
To increase FET performance and increase hFE. The reason that undoped AlzGa1-zAs (z = 0.30) 335 is inserted between the n-type GaAs 338 which is the base layer and the emitter layer 36 is that when Vbe is larger than Vtp, the accumulation layer of 2DEG is
Due to the individual heterobarriers formed, a huge current gain can be realized. However, in this case, the bipolar performance is lower than the 2DEG base. The reason is that an extra degree-delay time is generated because the base layer is doped.

Next, how to make a current limiter will be described. One way is to short-circuit the source and the gate of the FET, the saturation source / drain current Idss (Vg = 0V) when the gate voltage Vg = 0V becomes the current limiter current Io
become. When applied to the complementary BiFET, the power consumption Po during standby is determined. (1) Io needs to be suppressed to about 0.1-50 μA. If the power consumption during switching is Ps, the power consumption during standby Po
Must be smaller than Ps. Circuit power consumption P
Is Po + Ps, and it is necessary to reduce P as a design principle in order to reduce power consumption. To increase the speed, it is unavoidable to increase Ps to some extent (relationship between speed and trade-off). On the other hand, (2) the process is simple
Want to form a current limiter without losing the advantages of DEG-HBT. A method for satisfying both will be described in the next embodiment.

<Embodiment 9> An embodiment in which the FET operation of 2DEG-HBT is used will be described with reference to FIGS. This will be described using a third embodiment. Insert a current limiter between the emitter and base. The current limiter basically connects the source and gate of the FET. Fig. 6
As shown in (a), even if the Vth of the FET is positive, the source drain current of the FET flows when the Vth is approximately 0 to 0.15 V, so that this can be used as a current limiter. Io can also be adjusted by adjusting the width of the current limiter. Therefore, Figure 3
8, As shown in Fig. 39, if the gate part 140 of the current limiter is inserted between the base part and the emitter part, basically, the epi structure of 2DEG-HBT is used as it is, and there is no major change in the process. In addition, a current limiter can be formed. The current limiter is a so-called HEM shown in Fig. 36 (b).
It may be formed using T. Fig. 38
(a) or two positions in FIG. Further, the gate electrode and the base electrode of the current limiter may be formed of the same electrode as shown in FIG.

Next, a method for forming a diode will be described. One of the features of the GaAs / AlGaAs heterojunction not found in the Si process is that a good and controllable heterojunction can be formed. The 2DEG-HBT can be said to be a device that uses that point. By using Iso-Heterojunction as a unique use of heterojunction, it is possible to form a diode without the accumulation effect of minority carriers.

Here, the Iso-Hetero junction is an n-type Ga
As / undoped AlGaAs (or AlAs) / n-type GaAs or p-type GaAs / undoped AlGaAs (or AlAs) / p-type GaAs
Etc. InuGa1-uAs may be used instead of GaAs. Let L be the thickness of the undoped layer sandwiched in the middle. n
Fig. 42 shows the conduction band diagram when voltage is applied to both ends of n-type GaAs / undoped AlGaAs (or AlAs) / n-type GaAs.
It is shown in (b). Dotted lines indicate Fermi Revel. The current-voltage characteristics at this time are shown in FIG. The rise voltage Vfe (ISO) can be controlled by the Al composition, the film thickness L, the temperature used, and the like. The same applies to the p-type Iso-Heterojunction. Vfe (ISO) can be designed in the range of approximately 0-1V.

<Embodiment 10> FIGS. 40 and 41 (a) and (b) show the Iso-Hete
Examples of rojunction will be described. Figure 41 (a) shows the p-type Iso-
The case of Heterojunction will be described. 2 x 10 C (carbon)
Undoped GaAs on p-type GaAs 255 50 nm containing ²⁰ / cm ³
256 at 10 nm, and undoped AlxGa1-xAs (x = 0.45) 2
57 for 70 nm, undoped GaAs 258 for 10 nm, and
40 p-type GaAs 259 containing 2 × 10 ²⁰ / cm ^{3 of} C (carbon)
nm, formed by MOMBE. The diode electrode 2
45, 246 were formed. Vfe (ISO) was 0.3 V.

Next, the case of the n-type Iso-Hetero junction will be described with reference to FIG. N containing 3 × 10 ¹⁸ / cm ^{3 of} Si (silicon)
Type GaAs 50 10 nm undoped GaAs 51 on 160 nm,
Further, undoped AlxGa1-xAs (x = 0.45) 52 is 100 nm, undoped GaAs 53 is 10 nm, and Si (silicon) is 3 nm.
× 10 ¹⁸ / cm ³ containing n-type GaAs / InGaAs graded / InAs layer
54 was formed by MBE. The diode electrode 4
7, 44 were formed. For 47, a non-alloy metal can be selected. In this case, Vfe (ISO) was 0.45 V.
Such a diode of Iso-Heterojunction is represented by a square inclined at 45 degrees, the n-type case is outlined and the p-type case is painted in black.
Represent. When used as a diode in a complementary BiFET There are two cases shown in FIGS. 40 (a) and (b).

Next, the design of the diode voltage shift ΔV will be described. In particular, the application range of complementary BiFETs (desktop workstations and desktop personal computers that require both speed and low power consumption from logic circuits and SRAMs that prioritize speed for high-speed computers, digital / analog ICs for optical communication, , Portable telephones, portable personal computers, portable videophones, etc., which require ultra-low power consumption, the power consumption must be controlled in a wide range. Accordingly, it is necessary that the voltage shift ΔV can be designed to some extent freely from about 0 V to about 1.5 V. A method for making these will be described in Example 11. In this case, too, we want to form a diode without losing the advantage of 2DEG-HBT in that the process is simple.

ΔVgd + ΔVdd = 0.75 V, Vdd = 2.15 V, V
The case where fn = about 1.4 V will be described below.

<Embodiment 11> There are roughly three ways to insert a diode on the collector side of a bipolar. (1) Insert a p-type Schottky diode into the p-type layer of the collector layer. (2) Form an n-type layer at the drain of the FET and insert a Schottky diode. (3) Insert a p-type Iso-Heterojunction diode into the p-type layer of the collector layer. On the other hand, there are roughly three ways to put a diode in the gate of an FET.

(4) An n-type Iso-Het is formed on the p-type gate (emitter) layer.
Insert erojunction diode. (5) Insert an n-type Schottky diode on the p-type gate (emitter) layer.
(6) An n-type Schottky diode is inserted into a region other than the FET during the selected epi.

First, FIG. 43 (a) shows that a p-type Iso-Heter
An example of an element cross section when an ojunction diode is inserted and an n-type Schottky diode is also inserted at the gate of the FET is shown. The basics of the epi structure are the same as in the second embodiment. Here, only the differences will be mentioned. First, semi-insulating Ga
P-type GaAs 70 containing 3 × 10 ¹⁹ / cm ³ Be on As substrate 30
200 nm, undoped GaAs 71 30 nm, undoped Al
200 nm of yGa1-yAs (y = 0.45) 72 is formed, and as in Example 2, crystal growth is performed from p-type GaAs 31 containing 3 × 10 ¹⁹ / cm ^{3 of} Be. Si on the p-type GaAs layer 56 is 4 × 10 ¹⁸ / cm ³
Contain n-type GaAs 154 at 50 nm and Si at 4 × 10 ¹⁷ / cm ³
The contained n-type GaAs 155 is grown by 90 nm crystal. In the bipolar portion, after removing the n-type GaAs 154 and 155, a process of forming a diode is added in addition to the process of the second embodiment. That is, a p-type Iso-Heterojunction diode is formed through the collector electrode 42 and the ohmic electrode 49 to the p-type GaAs 70. Electrode 49 is connected to the drain part, and
It becomes the output terminal of iFET. The gate portion of the FET and the n-type Schottky junction are formed in a self-aligned manner by using the high heat-resistant gate electrode 45 that makes a Schottky junction with the n-type GaAs 155. p-type Ga
The As layer 56 and the n-type GaAs 154 have a tunnel junction.

Next, a p-type Schottky diode is inserted into the collector in FIG. 43 (b), and a p-type
An example of an element cross section when a Heterojunction diode is inserted is shown. The basics of the epi structure are the same as in the second embodiment.
Here, only the differences will be mentioned. First, after forming a GaAs buffer layer on a semi-insulating GaAs substrate 30, Be is applied at 3 × 10 ¹⁷ / cm ³
A 300 nm thick p-type GaAs 170 is formed, and a crystal is grown from a p-type GaAs 31 containing 3 × 10 ¹⁹ / cm ^{3 of} Be as in the second embodiment. Undoped GaAs 57 on p-type GaAs layer 56
30 nm, undoped AlyGa1-yAs (y = 0.45) 58 to 200
A p-type GaAs 59 containing nm and Be at 10 ²⁰ / cm ³ is formed. After removing the semiconductor layers 57, 58 and 59 in the emitter part,
The process proceeds as follows. Using the Schottky electrode 48 for the p-type GaAs 170, a p-type Schottky diode is formed between the Schottky electrode and the collector electrode. Schottky electrode
48 is connected to the drain electrode, and the complementary BiFET
Output terminal.

Next, FIG. 44A shows that the n-type Iso-H
An example of an element cross section when an eterojunction diode is inserted and a p-type Iso-Heterojunction diode is inserted in the gate of the FET is shown. The basics of the epi structure are the same as in the second embodiment. The method for forming the FET gate region and the bipolar emitter region is the same as in FIG. 43 (b). The difference is n-type GaA
After selectively growing the s layer 50 by MOCVD, undoped GaAs 51
10 nm, undoped AlyGa1-yAs (y = 0.45) 52 to 200 n
m, 10 nm of undoped GaAs 53 and 200 nm of n-type GaAs 54 containing 4 × 10 ¹⁸ / cm ^{3 of} Si were formed by MOCVD. n-type Iso-H
To form an eterojunction diode, a diode electrode 47 was alloyed using AuGe / Ni / Au. The diode electrode 47 is connected to the collector electrode 42 and serves as an output terminal.

Finally, an n-type Schottky diode is inserted in the drain portion in FIG.
An example of a cross section of an element when a Schottky diode is inserted is shown. The basics of the epi structure are the same as in the second embodiment.
The formation of the FET gate and emitter regions is the same as in FIG. 43 (a). The difference is that after selectively growing the n-type GaAs layer 50 by MOCVD, an n-type GaAs 151 containing 4 × 10 ¹⁷ / cm ^{3 of} Si is grown to a crystal thickness of 300 nm. Using the n-type GaAs 151, a metal 147 that forms an n-type Schottky junction is formed at the drain portion, and a diode is inserted. The Schottky electrode 147 is connected to the collector electrode 42 and serves as an output terminal of the complementary BiFET.

[0146] Using Embodiments 3, 9, 10, and 11, FIG.
3- When the 3-input NAND circuit shown in Fig. 26 is implemented, it is possible to achieve a high speed of 3-10 psec and a power consumption of 2μW-300μW per unit logic gate.

In the above embodiments, a compound semiconductor was used.
The case of the combination of n-channel FET and PNpHBT is specified.
The present invention can be practiced with a structure in which the conductivity type of the carrier is reversed. Also, the present invention can be implemented using a combination with an n-channel MOSFET even with a double heterojunction 2DEG-HBT using SiGe. In particular, SiGe has a smaller band gap than Si, and thus corresponds to a GaAs layer, and Si corresponds to an AlGaAs layer. However, Si is used for the substrate. Since a MOS-FET is used for the n-channel FET, a current limiter is required, but there is no need to insert a diode.

Embodiment 12 FIG. 33 shows an embodiment of a double heterojunction 2DEG-HBT using SiGe / Si.

The n-type Si substrate 530 is formed on the n-type Si substrate
531, p-type Si 532, undoped Si 533, undoped SixGe1
-x (x = 0.2) 534, n-type Si 535, p-type Si 536, and FET
In the portion, the layer above the SiGe layer 534 is etched away, and the undoped Si 533 is thermally oxidized to form a MOSFET. I was sorry. Arsenic is ion-implanted to form a source / drain region 537. Channel layer formed under SiO ₂ 555
538 is a so-called electron inversion layer.

[0150]

According to the present invention, the heterojunction between the base and the collector causes (1) the number of minority carriers accumulated in the collector to be extremely reduced, and the delay time when the transistor comes out of the saturation region is extremely reduced. And in 2DEG-HBT,
Due to the feature that 2DEG (two-dimensional electron gas) formed by selective doping heterostructure is used for the base layer and the base is formed in a high-purity collector layer, (2) it accumulates in the base region when the transistor is saturated Minority carriers are extracted very quickly when exiting the saturation region.

By utilizing the characteristics of such a double heterojunction 2DEG-HBT, it is possible to form a pn junction FET with the same epi structure, which is an original feature of the 2DEG-HBT. Connect the collector to the output, connect the gate of the FET region to the bipolar base and use it as the input,
By setting the emitter to a high potential and the source to a low potential, a complementary BiFET can be formed.

Further, by inserting a current limiter into the base, or inserting a diode into the collector or gate, power consumption can be reduced.
By using the FET structure, in the case of a logic gate, it is possible to provide a logic gate that operates at an ultra-high speed with a delay time per gate of 10 psec or less and an ultra-low power consumption of 10 μW or less.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic structure and operating characteristics of a complementary BiFET of the present invention.

FIG. 2 is an explanatory diagram of a basic structure and operating characteristics of a complementary BiFET of the present invention.

FIG. 3 is an energy band diagram and an explanatory diagram of a double heterojunction 2DEG-HBT realizing the present invention.

FIG. 4 is an energy band diagram and an explanatory diagram of a double heterojunction 2DEG-HBT realizing the present invention.

FIG. 5 is an auxiliary diagram for explaining the operation characteristics of the complementary BiFET of the present invention.

FIG. 6 is an auxiliary diagram for explaining the operation characteristics of the complementary BiFET of the present invention.

FIG. 7 is an auxiliary diagram for explaining the operation characteristics of the complementary BiFET of the present invention.

FIG. 8 is an explanatory diagram of operation characteristics of the complementary BiFET of the present invention.

FIG. 9 is an explanatory diagram of operation characteristics of the complementary BiFET of the present invention.

FIG. 10 is an explanatory diagram of the operation characteristics of the multiple-connection complementary BiFET of the present invention.

FIG. 11 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 12 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 13 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 14 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 15 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 16 is an explanatory diagram of the operation characteristics of the multiple connection complementary BiFET of the present invention.

FIG. 17 is an explanatory diagram of the operation characteristics of the multiple-connection complementary BiFET of the present invention.

FIG. 18 is a conceptual diagram showing a reduction in power consumption of a complementary BiFET of the present invention.

FIG. 19 is a conceptual diagram showing low power consumption of the complementary BiFET of the present invention.

FIG. 20 is a conceptual diagram showing a reduction in power consumption of a complementary BiFET of the present invention.

FIG. 21: Complementary BiFET with reduced power consumption
FIG. 4 is an explanatory diagram of the operation characteristics of FIG.

FIG. 22: Complementary BiFET with reduced power consumption
FIG. 4 is an explanatory diagram of the operation characteristics of FIG.

FIG. 23 is an explanatory diagram of a three-input NAND circuit using the complementary BiFET of the present invention.

FIG. 24 is an explanatory diagram of a three-input NAND circuit using the complementary BiFET of the present invention.

FIG. 25 is an explanatory diagram of a three-input NAND circuit using a complementary BiFET of the present invention.

FIG. 26 is an explanatory diagram of a three-input NAND circuit using the complementary BiFET of the present invention.

FIG. 27 is an explanatory diagram of a three-input NOR circuit using a complementary BiFET of the present invention.

FIG. 28 is an explanatory diagram of a three-input NOR circuit using a complementary BiFET of the present invention.

FIG. 29 is an explanatory diagram of a three-input NOR circuit using a complementary BiFET of the present invention.

FIG. 30 is an explanatory diagram of a three-input NOR circuit using a complementary BiFET of the present invention.

FIG. 31 shows an SRA using the complementary BiFET of the present invention.
FIG. 2 is an explanatory diagram of an M (static random access memory) memory cell.

FIG. 32 shows an SRA using the complementary BiFET of the present invention.
FIG. 2 is an explanatory diagram of an M (static random access memory) memory cell.

FIG. 33 is a cross-sectional view of an element when the complementary BiFET of the present invention is realized by a SiGe / Si heterojunction.

FIG. 34 is an element cross-sectional view of an embodiment of a complementary BiFET of the present invention.

FIG. 35 is a sectional view of a complementary BiFET according to an embodiment of the present invention.

FIG. 36 is a device sectional view of an embodiment of a complementary BiFET of the present invention.

FIG. 37 is an element sectional view of an embodiment of a complementary BiFET of the present invention.

FIG. 38 is a device cross-sectional view of an embodiment of a low power consumption complementary BiFET having a current limiter.

FIG. 39 is a device cross-sectional view of an embodiment of a low power consumption complementary BiFET having a current limiter.

FIG. 40 is an explanatory diagram of a diode using Iso-Heterojunction.

FIG. 41 is an explanatory diagram of a diode using Iso-Heterojunction.

FIG. 42 is an explanatory diagram of a diode using Iso-Heterojunction.

FIG. 43 is a sectional view of an element of an embodiment of a low power consumption complementary BiFET having a diode.

FIG. 44 is a device cross-sectional view of an embodiment of a low power consumption complementary BiFET having a diode.

[Explanation of symbols]

10… PNp DHBT, 20… n-channel FET, 30… Semi-insulating GaAs
s substrate, 31 ... p-type GaAs, 32 ... p-type AlGaAs, 33 ... undoped, AlGaAs, 34 ... undoped GaAs, 35 ... n-type AlGaAs, 36
... p-type AlGaAs, 37 ... n-type high concentration region, 38 ... 2DEG, 40 ... emitter electrode, 41 ... base electrode, 42 ... collector electrode, 43 ... source electrode, 44 ... drain electrode, 45, 45 '... gate electrode, Four
6 ... Substrate bias electrode, 134 ... p-type GaAs, 135 ... n-type AlGaA
s, 50: n-type GaAs, 55, 56: p-type GaAs, 38 ': 2DEG, 60: sidewall insulating film, 234: undoped InGaAs, 300: oxygen ion implanted layer, 50 ": GaAs / InGaAs / InAs, 335 ... Undoped AlGaA
s, 338: n-type GaAs or InGaAs, 40 ": current limiter gate electrode, 59, 70, 170, 255, 259, p-type GaAs, 51, 53, 57, 71,
256,258… undoped GaAs, 52,58,72,257… undoped A
lGaAs, 54,154,151,155 ... n-type GaAs, 47 ... diode electrode, 147 ... Schottky electrode, 245,246 ... diode electrode, 530 ... n-type Si substrate, 531 ... n-type Si, 532 ... p-type Si, 533 ...
Undoped Si, 534 ... Undoped SiGe, 535 ... n-type Si, 536
... p-type Si, 555 ... SiO ₂ , 537 ... n-type ion implantation area, 230 ... I
nP substrate, 31 '... undoped AlInAs / GaInAs superlattice, 32' ... p
Type AlInAs, 33 '... undoped AlInAs, 34' ... undoped Ga
InAs, 35 '… n-type AlInAs, 36'… p-type, AlInAs, 55 '… p-type Ga
InAs, 50 '… n-type GaInAs.

────────────────────────────────────────────────── ⁷ Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/737 29/778 29/812 (56) References JP-A-55-1134 (JP, A) JP-A-62-199049 (JP, A) JP-A-3-28037 (JP, A) JP-A-63-5552 (JP, A) JP-A-63-236358 (JP, A) SHUICHI FUJITA, et. al. , "Characterization of Heterostrature Completionary MISFET Circuits Employing, the New Gate Current Model", IEEE TRANSACTION 1987, ELECTRON CONNECTION, 1987. ED-34, NO. 9, pp. 1889-1896 Patrick D. Rabinzo hn, et. al. , "The Two Two-Dimensional Electron Gas Base HBT (2DEG-HBT) :, Two-Dimensional Numerical Simulation", IEEE TRANSACTIONS, 1991. 38, NO. 2, pp. 222-231 (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/337-21/338 H01L 21/8222-21 / 8228 H01L 21/8232 H01L 27/06-27/06 101 H01L 27/08-27/08 101 H01L 27/082 H01L 29/00-29/267 H01L 29/30-29/38 H01L 29/778 H01L 29 / 80-29/812

Claims (6)

(57) [Claims] 1. A heterojunction between an emitter and a base, a heterojunction between a base and a collector, and the heterojunction is
A double heterojunction bipolar transistor (hereinafter, referred to as DHBT) having an epi structure and a field-effect transistor (hereinafter, referred to as FET) having a different polarity from the DHBT are provided. The base of the DHBT is connected to the gate of the FET. The collector of the DHBT and the drain of the FET are connected to form an output terminal, the emitter of the DHBT is connected to a first power supply, and the source of the FET is connected to a second power supply. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein said DHBT is formed by a multilayer epi-structure, and a layer corresponding to said base constitutes an active layer of said FET. 3. The semiconductor device according to claim 1, wherein a constant current limiter or a resistor is inserted into a base of said DHBT. 4. The semiconductor device according to claim 1, wherein a diode is inserted into a collector or a gate of said DHBT. 5. The semiconductor device according to claim 1, wherein said DHBT is a two-dimensional electron gas-based heterobipolar transistor. 6. The semiconductor device according to claim 1, wherein said FET is of an enhancement type.