JP3322057B2 - EDTV2 signal processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly, to an aspect ratio of a screen.
The present invention relates to an identification control signal processing device in a 16: 9 second-generation EDTV2-compatible television receiver.

[0002]

2. Description of the Related Art The development of the EDTV2 broadcasting system is currently in progress in Japan. An object is to transmit a wide image having an aspect ratio of 16: 9 with high image quality while maintaining compatibility with the current NTSC broadcasting system.

First, an identification control signal multiplexed on scanning line numbers 22 (22H) and 285 (285H) in the EDTV2 broadcasting system will be described with reference to FIG. FIG. 7 shows a waveform diagram of the EDTV2 identification control signal. In FIG. 7, 27 bits of information from B1 to B27 are multiplexed in one horizontal scanning period, as indicated by the numbers attached to the waveform diagram. Each bit is equivalent to 7 cycles of the color subcarrier (about 2 μs
c) width. The main waveforms in FIG. 7 will be described.

For example, B3 is EDTV 2 at 40 IRE.
Broadcast, and 0IRE is NTSC broadcast. B6
From B23 to B23, chrominance subcarriers are multiplexed with an amplitude of ± 20 IRE, and the phase is defined as 1 when the phase is 0 phase and as 0 when the phase is π phase (the same phase as the color burst). B8, B9,
By B10, it is possible to identify whether the VT signal (vertical temporal high-frequency augmentation signal), VH signal (vertical high-frequency augmentation signal), and HH signal (horizontal high-frequency augmentation signal) are multiplexed.
The EDTV2 identification control signal includes a signal called a confirmation signal of B25 to B27 in addition to the identification information as described above, and information for determining whether the EDTV2 is used and phase information of the blow-out carrier that modulates the HH signal are multiplexed. In addition, three division points (B1 to B9, B10
To 18 and B19 to 27) are information indicating the positions of the three division points of the VT signal / VH signal multiplexed in the upper and lower non-image portions.

Hereinafter, a conventional EDTV2 receiver will be described with reference to FIGS. FIG. 5 shows a conventional EDTV
2 is a circuit block diagram of a receiver.

In FIG. 5, 101 is an antenna for receiving a broadcast, 102 is a tuner circuit for receiving and selecting a broadcast, detecting a video and outputting a composite video signal, and 103 is converting a composite video signal output from the tuner circuit 102 into a digital signal. An A / D converter 104 is an identification control signal detection / demodulation circuit connected to the output terminal of the A / D converter 103, and is the 22nd and 285th of the 525 NTSC signals / frame horizontal scanning period. EDTV multiplexed during horizontal scanning
2 is a circuit for detecting and demodulating the identification control signal.

FIG. 6 shows the configuration of the identification control signal detection / demodulation circuit 104. 6, reference numeral 131 denotes an identification control signal input terminal; 132, a circuit for demodulating each bit of the identification control signal into binary data; 133, an identification control signal demodulation circuit 13;
An identification control signal code discrimination circuit for reading and discriminating the output of each bit for each bit and outputting the discrimination signal for each bit is a terminal for outputting the discrimination control signal demodulated by the discrimination control signal code discrimination circuit 133.

Reference numeral 105 denotes a three-dimensional Y / C separation circuit connected to the output terminal of the A / D converter 103, which separates and extracts a luminance signal and a chrominance signal by motion adaptive processing. Reference numeral 106 denotes an HH reproducing circuit which modulates the color signal extracted by the three-dimensional Y / C separation circuit 105 by further taking a field difference.
The signal is separated into a signal and a color signal, and the HH signal is reproduced by multiplying the blow-out carrier extracted by the identification control signal detection / demodulation circuit 104 by the modulated HH signal. Reference numeral 107 denotes a 4.2 of the luminance signal output from the three-dimensional Y / C separation circuit 105.
H that adds the component of the HH signal output from the HH reproduction circuit 106 to the component of the 4.2 to 6 MHz band, which is lower than the MHz component.
An H synthesizer 108 is a color demodulation circuit that demodulates the color signal extracted by the HH reproduction circuit 106, time-division multiplexes two color signals, and outputs the result. Reference numeral 109 denotes a delay circuit for a luminance signal output from the HH combiner 107. The main image main line video signal is provided for 90 scanning lines so that the phase is matched with the vertical reinforcement signal multiplexed in the non-image part. Delay.

Reference numeral 110 denotes a color demodulation circuit 108 and a delay circuit 10
9 is a D / D converter having a storage element (line memory) that uses a clock signal synchronized with the color subcarrier (fsc) when writing the output and uses a clock signal synchronized with the horizontal synchronization signal when reading the output. Reference numeral 111 denotes a motion adaptive scanning line interpolation circuit for generating a sequential scanning signal from an interlaced scanning signal used in a clear vision receiver or the like.
A luminance signal and a chrominance signal output from the converter 110 are input, and four signals of a luminance current line signal 112, a luminance interpolation line signal 113, a color difference current line signal 114, and a color difference interpolation line signal 115 are output. I do. 116 is D /
The VT / VH reproducing circuit connected to the output terminal of the D converter 110 separates and reproduces the VT signal and the VH signal multiplexed in the upper and lower non-image area using the frame difference. Reference numeral 117 denotes a high frequency component of the luminance interpolation line signal 113 output from the motion adaptive scanning line interpolation circuit 111 and a VT / VH reproduction circuit 116.
Is a VT combiner that adds the low frequency components of the VT signal output from the VT.

Reference numeral 118 denotes a scanning line number conversion circuit composed of a field memory and a vertical filter, and the number of scanning lines is multiplied by 4/3 for 360 main image portions to synthesize 480 scanning lines.
Four kinds of signals are output: a luminance current line signal 119, a luminance interpolation line signal 120, a color difference current line signal 121, and a color difference interpolation line signal 122. VH synthesizers 123 and 124 add the VH signal output from the VT / VH reproduction circuit 116 to each of the luminance current line signal 119 and the luminance interpolation line signal 120 output from the scanning line number conversion circuit 118. Reference numeral 125 denotes a double speed modulation circuit constituted by a line memory, which sequentially creates a scanning luminance signal from a luminance current line signal output from the VH synthesizer 123 and a luminance interpolation line signal output from the VH synthesizer 124, and Color difference current line signal 121 output from number conversion circuit 118
Then, a scanning color difference signal is created sequentially from the color difference interpolation line signal 122 and. Reference numeral 126 denotes a D / A converter connected to the output of the double-speed conversion circuit 125.
Output two color difference signals. 127 is a D / A converter 126
An RGB processing circuit for synthesizing RGB signals from the signals output from the RGB processing circuit by a matrix operation. A display 128 displays the output of the RGB processing circuit 127.

The operation of the conventional identification control signal detection / demodulation circuit configured as described above will be described below.

First, the identification control signal detection and demodulation circuit 104 detects and demodulates the identification control signal multiplexed on the scanning line numbers 22 and 285 of the composite video signal from the tuner circuit 102, and B3 and B4 are 1, ie, letter box. When a video is multiplexed and some conditions are satisfied, such as a sine wave for confirmation being multiplexed on B25 to B27, this composite video signal is recognized as EDTV2.
When the identification control signal B10 is 1 (HH signal is present), the HH reproduction circuit 106 can output the HH signal, and the identification control signals B8 and B9 are 1 (VT / VH).
Signal is present), the VT / VH reproduction circuit 116 outputs the VT / VH
It is possible to output a VH signal. At this time, HH
• The VT / VH presence determination signal is output directly to each block. If the identification control signal detection / demodulation circuit 104 determines that the composite video signal from the tuner circuit 102 is not an EDTV2 signal, the HH reproduction circuit 106 or the VT / VH
The value of each output of the reproduction circuit 116 is 0. That is, HH
The combiner 107, the VT combiner 117, and the VH combiners 123 and 124 are in a state of passing main-line signals, and have a configuration of a conventional clear vision receiver. However, if the scanning line number conversion circuit 118 is separately controlled, it is possible to operate as a zoom function without a vertical reinforcement signal.

[0013]

The identification control signals B6 to B23 which are modulated and transmitted to the chrominance subcarrier are synchronized with the color burst which is the phase reference of the chrominance subcarrier, so that they are synchronized with the horizontal synchronization signal. When demodulating with a clock that is running, problems such as code errors occur.

Further, when each bit data is output, there is a problem that the number of output terminals increases because the data is sent directly to each block.

In view of the above problems, according to the present invention, when demodulating the signals B3 to B23, only the position reference B1 is output without demodulation, and the signals B3 to B23 are demodulated and superimposed on binary data for transmission. The present invention provides an EDTV2 receiver that performs stable image reproduction by including a circuit for performing the above operation.

[0016]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a video signal input terminal and a first control signal for identifying an EDTV2 signal input from the video signal input terminal.
B1 for detecting the falling position of the bit (B1)
A position reference is detected based on the output of the falling detection circuit and the output of the B1 falling detection circuit, and the third bit (B3) is detected.
The first control pulse indicating the position of the 23rd bit (B23) from the second and the second indicating the position where B3 to B23 are superimposed
And a control circuit that outputs the control pulses of the first and second control pulses, and the first control pulse output of the control circuit outputs the identification control signals B3 to B23.
B3 to B23 demodulation circuits for demodulating the data up to binary data;
A switching circuit for switching between the discrimination control signal and the outputs of the B3 to B23 demodulation circuits according to a second control pulse output of the control circuit; and a clock synchronized with a color subcarrier (fsc) when writing the output of the switching circuit. It has a D / D converter having storage means for using a clock signal synchronized with a horizontal synchronizing signal when reading out a signal, and a terminal for outputting an output signal of the D / D converter.

[0017]

According to the present invention, the demodulation of the part except for B1 of the identification control signal is performed by the clock synchronized with the color sub-carrier by the above-mentioned configuration. Since the fsc modulation section, which has been considered difficult to perform, can be transmitted as binary data in a superimposed manner, in line lock, as long as a circuit for detecting the position of B1 is provided, each bit information is synchronized with a clock synchronized with the horizontal synchronization signal. It is possible to read and reduce errors in code discrimination, and it is possible to reduce the number of output terminals because the data is superimposed and sent. As a result, in the line lock system, all information of the identification control signal can be obtained as long as only the falling position of B1 can be detected.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A video signal processing circuit according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a video signal processing circuit according to one embodiment of the present invention. In FIG. 2, reference numeral 21 denotes an antenna for receiving a broadcast, reference numeral 22 denotes a tuner circuit for selecting and receiving a broadcast, detecting a video, and outputting a composite video signal, and reference numeral 23 denotes an A for converting the composite video signal output from the tuner circuit 22 to a digital signal. A / D converter 24 is an identification control signal detection / demodulation circuit connected to the output terminal of the A / D converter 23, and is the 22nd and 285th horizontal scans in the 525 NTSC signal / frame horizontal scan period. EDTV2 multiplexed in the period
This circuit detects and demodulates the identification control signal. 25 is A /
A three-dimensional Y / C separation circuit connected to the output terminal of the D converter 23 separates and extracts a luminance signal and a chrominance signal by motion adaptive processing. Reference numeral 26 denotes an HH reproduction circuit, which separates the color signal extracted by the three-dimensional Y / C separation circuit 25 into a modulated HH signal and a color signal by taking a field difference, and converts the HH signal into an identification control signal detection / demodulation circuit. Reproduction is performed by multiplying the blown-out carrier extracted at 24 and the modulated HH signal. An HH combiner 27 adds a 4.2 MHz or less component of the luminance signal output from the three-dimensional Y / C separation circuit 25 and a 4.2 to 6 MHz band component of the HH signal output from the HH reproduction circuit 26. And 28 are color demodulation circuits for demodulating the color signals extracted by the HH reproducing circuit 26, time-division multiplexing the two color signals, and outputting the resulting signals.

Reference numeral 29 denotes a delay circuit for the luminance signal output from the HH combiner 27. The delay circuit 29 converts the main picture main line video signal into a 90-line picture so that the vertical reinforcement signal multiplexed in the non-picture section is in phase with the picture when synthesized. Delay by this amount. Reference numeral 30 denotes a D / D having storage means (line memory) using a clock signal synchronized with the color subcarrier (fsc) when writing the output of the color demodulation circuit 28 and using a clock signal synchronized with the horizontal synchronization signal when reading the output. It is a converter. Reference numeral 31 denotes a motion adaptive scanning line interpolation circuit for generating a sequential scanning signal from an interlaced scanning signal used in a clear vision receiver or the like, and a luminance output from the identification control signal detection / demodulation circuit 24 and the D / D converter 30. A signal and a chrominance signal are input, and four signals of 32 luminance current line signals, 33 luminance interpolation line signals, 34 chrominance current line signals, and 35 chrominance interpolation line signals are output. Reference numeral 37 denotes a VT / VH reproduction circuit connected to the output terminal of the discrimination control signal detection / demodulation circuit 24, which separates and reproduces the VT signal and the VH signal multiplexed in the upper and lower non-image area using the frame difference.

Reference numeral 36 denotes a high frequency component of the luminance interpolation line signal 33 output from the motion adaptive scanning line interpolation circuit 31 and VT / V
This is a VT combiner that adds the low frequency component of the VT signal output from the H reproduction circuit 37. Numeral 38 denotes a scanning line number conversion circuit composed of a field memory and a vertical filter. The number of scanning lines is multiplied by 4/3 for 360 main image portions to synthesize 480 scanning lines. Four kinds of signals are output: 40 luminance interpolation line signals, 41 color difference current line signals, and 42 color difference interpolation line signals. Reference numerals 43 and 44 denote VH synthesizers, which apply a VH signal to each of the luminance current line signal 39 and the luminance interpolation line signal 40 output from the scanning line number conversion circuit 38.
The VH signal output from the T / VH reproduction circuit 37 is added. Reference numeral 45 denotes a B1 falling amplitude / phase detection circuit connected to the output of the identification control signal detection / demodulation circuit 24, which detects the falling position of B1 of the identification control signal and outputs the B9 of the identification control signal demodulated into binary data. , B10 are represented by V
Output to the T / VH reproduction circuit 37.

Reference numeral 46 denotes a double-speed modulation circuit constituted by a line memory, which sequentially generates a scanning luminance signal from the luminance current line signal output from the VH synthesizer 43 and the luminance interpolation line signal output from the VH synthesizer 44. A color difference signal is sequentially generated from the color difference current line signal 41 and the color difference interpolation line signal 42 output from the scanning line number conversion circuit 38. 4
Reference numeral 7 denotes a D / A converter connected to the output of the double-speed conversion circuit 48, which outputs a luminance signal for sequential scanning and two color difference signals. Reference numeral 48 denotes an RGB processing circuit for synthesizing RGB signals by matrix operation from the signal output from the D / A converter 47, and 49 denotes a display for displaying the output of the RGB processing circuit 48. The aspect ratio of the screen is 16: 9.

The operation of the identification control signal processing circuit of the present invention having the above-described configuration will be described below.

First, the operation of the identification control signal detection / demodulation circuit section enclosed by a dotted line in FIG. 2 will be described with reference to FIG.

In FIG. 1, reference numeral 11 denotes an input terminal of an output signal of the delay circuit 29, reference numeral 12 denotes an input terminal of an output signal of the A / D converter 23, and reference numeral 13 denotes a 22nd and a 285th input from the input terminal 11. Circuit for detecting the falling position of B1 of the identification control signal multiplexed during the horizontal scanning period
Reference numeral 4 denotes a control circuit for detecting a position reference based on the output from the B1 fall detection circuit 13 and outputting a control pulse indicating the position of B3 to B23. Reference numeral 15 denotes an input terminal 22 for an output signal of the A / D converter 23. B3 to B2 for demodulating the B3 to 23 flags of the input discrimination control signal into binary data
The demodulation circuit 16 is connected to the delay circuit 29 input from the input terminal 11 by the output of the control circuit 4 and B3 to B3.
23 is a switching circuit for switching the output of the demodulation circuit 15, and 17 uses a clock signal synchronized with the color subcarrier (fsc) when writing the output of the switching circuit 16 and a clock signal synchronized with the horizontal synchronization signal when reading the output. A D / D converter having a line memory, 18 is the D / D converter 17
Is a video signal output terminal for outputting the output signal.

The operation of the video signal processing circuit of FIG. 1 configured as described above will be described below.

The signal input to the output signal input terminal 11 of the delay circuit 29 is input to the switching circuit 16. The signal input to the output signal input terminal 12 of the A / D converter 23 is
B1 falling detection circuit 13 and B3 to B23 demodulation circuit 1
5 is input. The B1 falling detection circuit 13 detects the falling position of the first bit (B1), which is the position reference of the identification control signal in the input video signal, and determines the position of each bit accordingly. The output of the B1 falling detection circuit 13 is input to the control circuit 14. The control circuit 14 outputs a control pulse indicating positions of B3 to B23 and a control pulse indicating positions of B6 to B23 of the identification control signal. The output of the control circuit 14 is input to the B3 to B23 demodulation circuit 15 and the switching circuit 16.

Here, the B3 to B23 demodulation circuit 15 is shown in FIG.
This will be described with reference to FIG. In FIG. 3, reference numeral 61 denotes an output signal input terminal of the A / D converter 23, and reference numeral 62 denotes an NRZ demodulation circuit, which is provided with a certain threshold value, compares the threshold value with the threshold value, and demodulates the data into binary data according to the magnitude. I do. Reference numeral 63 denotes an fsc demodulation circuit, which is a B6 of the fsc-modulated identification control signal.
B23 are subjected to fsc demodulation. Reference numeral 64 denotes an input terminal of a control signal from the control circuit shown in FIG. 3, and reference numeral 65 denotes a switching circuit, which switches a signal to be output according to the control signal input from the control signal input terminal 64 and outputs it from an output terminal 66. The output signal is input to the switching circuit 16 of FIG.

FIG. 4 shows a timing chart of the circuit of FIG. 3, and the operation of FIG. 3 will be described. The control signal output from the control circuit 14 outputs two control signal signals, a control pulse indicating the position of the part B6 to B23 and a control pulse indicating the position of the part B3 to B23. The former signal is input to the control signal input terminal 64. If the signal is 0, the output of the NRZ demodulation circuit 62 is selected. If the signal is 1, the output of the fsc demodulation circuit is selected.

In the switching circuit 16, B of the output of the control circuit
In the case of the discrimination control signal in accordance with the control pulse indicating the positions of 3 to B23, the output of the B3 to B23 demodulation circuit is selected, and otherwise, the signal input from the input terminal 11 is selected. The output of the switching circuit 16 is input to the D / D converter 17. D /
In the D converter 17, when writing, the color subcarrier (fsc)
A line memory that uses a clock signal synchronized with the horizontal synchronization signal when reading the clock signal,
It is possible to transmit digital binary values to a system operating with a clock synchronized with the horizontal synchronizing signal, and all information of the identification control signal can be obtained as long as the falling position of B1 can be detected. The output of the D / D converter 17 is output from a video output terminal 18.

The identification control signal multiplexed on the scanning line numbers 22 and 285 of the composite video signal from the tuner circuit 22 is detected and demodulated by the identification control signal detection / demodulation circuit 24 operating as described above, and B3 and B4 become 1 That is, the letterbox video is multiplexed, and B25 to B27
When some conditions are satisfied, such as when a sine wave for confirmation is multiplexed, the composite video signal is recognized as EDTV2. When the identification control signal B10 is 1 (HH signal present), the HH signal can be output from the HH reproduction circuit 26, and the identification control signals B8 and B9 are 1 (VH).
In the case of a T / VH signal, the VT / VH reproduction circuit 37 can output a VT / VH signal. When the identification control signal detection / demodulation circuit 24 determines that the composite video signal from the tuner circuit 22 is not an EDTV2 signal, the value of each output of the HH reproduction circuit 26 and the VT / VH reproduction circuit 37 becomes zero. In other words, the HH combiner 27, the VT combiner 36, and the VH combiners 43 and 44 are in a state of passing the signal of the main line system, and have the configuration of the conventional clear vision receiver. However, if the scanning line number conversion circuit 38 is separately controlled, it is possible to operate as a zoom function without a vertical reinforcement signal.

[0032]

As described above, according to the present invention, a video signal input terminal and an ED input from the video signal input terminal are provided.
First bit (B1) of identification control signal of TV2 signal
B1 falling detection circuit for detecting the falling position of the first bit, and a position reference based on the output of the B1 falling detection circuit for detecting the position of the third bit (B3) to the 23rd bit (B23). A control circuit that outputs a second control pulse indicating a position where B1 to B23 are superimposed on one control pulse, and B3 to B23 of the identification control signal are converted into binary data by the first control pulse output of the control circuit. A B3 to B23 demodulation circuit for demodulating, and a second
, The identification control signal and the signals B3 to
A switching circuit for switching the output of the B23 demodulation circuit, and storage means for using a clock signal synchronized with the color subcarrier (fsc) when writing the output of the switching circuit and using a clock signal synchronized with the horizontal synchronization signal when reading the output. D / D to have
A line lock system by providing a converter and a terminal for outputting an output signal of the D / D converter, by performing demodulation of a portion of the discrimination control signal except for B1 with a clock synchronized with a color subcarrier. In this case, the fsc (color subcarrier) modulator, which has been difficult to demodulate, can be transmitted as the minimum necessary binary data, and by superimposing, it is possible to realize a code discrimination error and a reduction in output terminals.

[0033]

[Brief description of the drawings]

FIG. 1 is a block diagram of an EDTV2 signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of the EDTV2 receiver of the present invention.

FIG. 3 is a block diagram of a B3 to B23 demodulation circuit of the present invention.

FIG. 4 is a timing chart of the B3 to B23 demodulation circuit of the present invention.

FIG. 5 is a block diagram of a conventional EDTV2 receiver.

FIG. 6 is a block diagram of a conventional identification control signal processing device.

FIG. 7 is a waveform chart showing an identification control signal in EDTV2 broadcasting.

[Explanation of symbols]

 Reference Signs List 11 video signal input terminal 12 identification signal input terminal 13 B1 falling detection circuit 14 control circuit 15 B3 to 27 demodulation circuit 16 switching circuit 17 D / D converter 18 video signal output terminal 21 reception antenna 22 tuner circuit 23 A / D conversion Device 24 identification control signal detection demodulation circuit 25 three-dimensional Y / C separation circuit 26 HH reproduction circuit 27 HH synthesizer 28 color demodulation circuit 29 delay circuit 30 color difference signal D / D converter 31 motion adaptive scanning line interpolation circuit 36 VT signal synthesis Device 37 VT / VH reproduction circuit 38 scanning line number conversion circuit 43 VH signal current line synthesizer 43 VH signal interpolation line synthesizer 45 B1 falling amplitude / phase detection circuit 46 double speed conversion circuit 47 D / A converter 48 RGB processing circuit 49 Display 61 Identification control signal input terminal 62 NRZ demodulation circuit 63 fsc recovery Circuit 64 Switching circuit 65 Identification control signal output terminal after demodulation 101 Receiving antenna 102 Tuner circuit 103 A / D converter 104 Identification control signal detection / demodulation circuit 105 Three-dimensional Y / C separation circuit 106 HH reproduction circuit 107 HH synthesizer 108 Color Demodulation circuit 109 Delay circuit 110 D / D converter 111 Motion adaptive scan line interpolation circuit 116 VT / VH reproduction circuit 117 VT signal synthesizer 118 Scanning line number conversion circuit 123 VH signal current line synthesizer 124 VH signal interpolation line synthesizer 125 Double speed conversion circuit 126 D / A converter 127 RGB processing circuit 128 Display 130 Identification control signal input terminal 131 B1 falling detection circuit 132 Identification control signal demodulation circuit 133 Output terminal after demodulation

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Hiroshi Nio 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Kenichiro Hayashi 1006 Kadoma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (58) Investigated field (Int.Cl. ⁷ , DB name) H04N 7/015

Claims (1)

(57) [Claims] 1. A video signal input terminal, and B for detecting a falling position of a first bit (B1) of an identification control signal of an EDTV2 signal input from the video signal input terminal.
The position reference is detected by the output of the B1 fall detection circuit and the B1 fall detection circuit, and the third bit (B
3) a control circuit for outputting a first control pulse indicating the position of the 23rd bit (B23) and a second control pulse indicating the position where B3 to B23 are superimposed, and a first control of the control circuit B3 to B of the discrimination control signal by pulse output
B3 to B23 demodulation circuit for demodulating the data up to 23 into binary data, a switching circuit for switching between the identification control signal and the output of the B3 to B23 demodulation circuit by a second control pulse output of the control circuit, A D / D converter having storage means using a clock signal synchronized with a color subcarrier (fsc) when writing an output, and using a clock signal synchronized with a horizontal synchronization signal when reading an output; A terminal for outputting an output signal;
23. An EDTV2 signal processing device, wherein the period in which the output of the demodulation circuit is superimposed by the switching circuit is at least one of the 22nd and 285th scanning line numbers or one horizontal scanning period of the vertical retrace period.