JP3321937B2 - Scramble playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scramble reproducing apparatus for reproducing an audio signal or the like in order to prevent illegal copying.

[0002]

2. Description of the Related Art As this type of scrambler, for example, as shown in Japanese Patent Application Laid-Open No. 4-285773, a first and a second analog audio signal are alternately switched at a predetermined cycle to use a first audio carrier. There is known a method of frequency-multiplex recording an FM-modulated signal and a signal FM-modulated by a second audio carrier on a recording medium. Further, in order to realize this scrambling method, a circuit for alternately switching the first and second analog audio signals at a predetermined cycle is used. In the digital scramble method, the first and second
A method is also conceivable in which the audio signal is periodically switched in frame units.

[0003]

However, in the above-described conventional scrambling method, since only two audio signals are periodically switched, the degree of scrambling is not flexible, and therefore, the clarity of the reproduced signal (reader ) Cannot be freely changed. In addition, there is a problem that the descrambling is easy and therefore practically insufficient, and a special circuit for periodically switching is required.

[0004] In view of the above-mentioned conventional problems, an object of the present invention is to provide a scramble reproducing apparatus which can freely change the clarity during reproduction without providing a special circuit.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method for calculating a syndrome of reproduced data of data error-corrected by Reed-Solomon code.
Drome calculation means, scramble mode and non-scramble
Means for setting a scramble mode, and the scramble mode
In such a case, the syndrome is changed and output so that error correction decoding cannot be performed normally, and the non-scramble mode is output.
A scrambling means for outputting the syndrome without changing it, and an scrambling means for outputting the syndrome based on an output of the scrambling means.
Decoding means for performing error correction; and
Time between the playback of video and the playback in the non-scramble mode
Control means for setting the combination at a predetermined ratio .

[0006]

According to the present invention, scrambling can be performed by changing the syndrome at the time of reproduction. For example, by clearing the syndrome or the modified syndrome, or by making the reversal cycle variable, the clearness at the time of reproduction can be obtained without providing a special circuit. The degree can be changed freely.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an error correction decoding unit which is a main part of an embodiment of the scramble reproduction device according to the present invention. FIG. 2 is a block diagram showing an outline of the scramble reproduction device having the error correction decoding unit of FIG. FIG. 3 is a block diagram showing an example of a scramble circuit in the arithmetic circuit of FIG. 1,
FIG. 4 is a block diagram showing another example of the scramble circuit in the arithmetic circuit of FIG. 1, and FIG. 5 is a diagram for explaining the operation of the error correction decoding unit of FIG. 1 for correcting the error of the C1 sequence of the double Reed-Solomon code. FIG. 6 is a flowchart for explaining the operation of the error correction decoding unit in FIG. 1 for performing error correction on the C2 sequence of the double Reed-Solomon code.

First, an outline of the scramble reproducing apparatus of the embodiment will be described with reference to FIG. The signal input to the input terminal 11 is, for example, DCC (digital compact cassette).
This input signal has a PCM signal and P and Q parity codes for error correction encoded in a predetermined format. When this input signal is input to the input terminal 11, first, the decoder 12
The signal is decoded into a CM signal and P and Q codes, and is applied to an error correction decoding unit 13 shown in detail in FIG.

The error correction decoding unit 13 performs error correction using, for example, a double Reed-Solomon code of the C1 sequence and the C2 sequence. In particular, when the scramble mode is not released by the function key 14, the control signal K will be used later. Thus, the syndrome Si and the modified syndromes A, B, C, P1, P2, and P3 are changed and error correction is performed to perform scramble reproduction. The signal corrected in error by the error correction decoding unit 13 or the signal subjected to scramble reproduction is output to the output terminal 16 via the output buffer 15. The scramble mode is set or canceled by, for example, inputting a password in advance from the function key 14.

Next, the error correction decoder 13 shown in FIG. 1 will be described in detail. First, if the receiving syndromes for errors of three or more words are S1, S2, S3, S4, and S5, and the error values are e1, e2, and e3, the following equation holds (the following addition is modulo 2 addition (exclusive OR). )).

[0011]

[Number 1] S0 = e1 + e2 + e3 S1 = x1 * e1 + x2 * e2 + x3 * e3 S2 = x1 2 * e1 + x2 2 * e2 + x3 2 * e3 S3 = x1 3 * e1 + x2 3 * e2 + x3 3 * e3 S4 = x1 4 * e1 + x2 4 * ^{e2 + x3 4 * e3 S5 =} x1 5 * e1 + x2 5 * e2 + x3 5 * e3

Here, x1, x2 and x3 indicate error locations (error locations). When a three-word error occurs, the following equation is obtained by modifying the above-described syndrome equation assuming the error position x1.

[0013]

[Number 2] T0 = S1 + x1 * S0 = (x1 + x2) * e2 + (x1 + x3) * e3 T1 = S2 + x1 * S1 = x2 * (x1 + x2) * e2 + x3 * (x1 + x3) * e3 T2 = S3 + x1 * S2 = x2 2 * (x1 + x2 ) * E2 + x3 ² * (x1 + x3) * e3 T3 = S4 + x1 * S3 = x2 ³ * (x1 + x2) * e2 + x3 ³ * (x1 + x3) * e3 T4 = S5 + x1 * S4 = x2 ⁴ * (x1 + x2) * e2 + x3 * ³ * E3 Next, this expression is further transformed to

[0014]

Assuming that T1 ² + T0 * T2 = P1 T2 ² + T1 * T3 = P2 T3 ² + T4 * T2 = P3

[0015]

[Number 4] P1 = (x1 + x2) * (x2 + x3) 2 * (x1 + x3) * e2 * e3 P2 = x2 * x3 * (x1 + x2) * (x2 + x3) 2 * (x1 + x3) * e2 * e3 P3 = x2 2 * x3 ³ * (x1 + x2) * (x2 + x3) ² * (x1 + x3) * e2 * e3 Here, in order to delete the error position x1 from each of the equations (Equation 4) that gives P1, P2, and P3,

[0016]

Assuming that A = P2 / P1 = x2 * x3 B = P3 / P2 = x2 * x3, if the value of the position xi is correct, then A = B (1) holds, and is transformed into A + B = D. I do.

In this embodiment, the above-mentioned D is calculated by the arithmetic circuit 4 assuming the value of the error position xi, and the value of the position xi where D becomes "0" is obtained by the PC control section 6.
In this case, the value of the position xi normally changes sequentially from “1” to n (n is the number of codewords), and there are three values of the position xi where the value of D becomes “0” at this time. Then, the three values are stored in the operation register 5. Here, since the values of the position xi stored in the operation register 5 are x1, x2, and x3, x1, x2, and x3 are known thereafter, and the values x1, x2, and x3 are used as follows. , Error values e1, e2 and e3 are obtained.

[0018]

Calculating E = S2 + (x1 + x2) * S1 + x1 * x2 * S0, E = (x1 + x3) * (x2 + x3) * e3 Therefore, E / (x1 + x3) * (x2 + x3) = e3

First, the value e3 is obtained, and then the syndrome is corrected by the value e3 as follows.

[0020]

Equation 7] S0m = S0 + e3 = e1 + e2 S1m = S1 + x3 * e3 = x1 * e1 + x2 * e2 S2m = S2 + x3 3 * e3 = x1 2 * e1 + x2 2 * e2 Subsequently,

[0021]

F = S1m + x1 * S0m = (x1 + x2) * e2） F / (x1 + x2) = e2, and finally, S0m + e2 = e1

By calculating the above, the positions x1, x2, x3 of all the errors and the values e1, e2, e3 are obtained.
Therefore, a three-word error is required. The error correction decoding unit 13 according to the present embodiment will be described with reference to FIG.
This control program is read by a program counter (PC) 7 under the control of a program counter (PC) control unit 6 and decoded by a decoder 9 to be checked by a syndrome check unit 1, a syndrome register 2, an input selector 3 and the arithmetic circuit 4.

As an example, the syndrome check unit 1 in the case where the number of parities is six is composed of adders of six parallel stages, registers, and multipliers of coefficients α to α ⁵ . At each stage, the syndromes S0 to S5 are obtained by the following operation on the input data Wi (i = 0 to 5), and the syndromes S0 to S5 are stored in the syndrome register 2 shown in FIG.

[0024]

S0 = ΣWi S1 = Σα ⁱ Wi S2 = Σα ²ⁱ Wi S3 = Σα ³ⁱ Wi S4 = Σα ⁴ⁱ Wi S5 = Σα ⁵ⁱ Wi

The syndrome Si read from the syndrome register 2, the current error position xi,
Intermediate operation results xi and ei of the error position and value stored in the operation register 5 are selected by the input selector 3 based on a selection signal from the decoder 9, and the operation circuit 4 performs a product-sum operation. The selection of data necessary for the following operation and branching based on a condition determination are performed based on the syndrome Si stored in the syndrome register 2 and the D (= A + B) stored in the operation register 5.
It is controlled by the control unit 6.

The operation of the present embodiment will be described in detail. First, the value of the syndrome Si is checked by the arithmetic circuit 4, and the correction operation mode is determined based on the value. 1. When all values of the syndrome Si are “0” In this case, it is determined that there is no error. This operation is S
j is determined by the result of sequentially adding the values of i, that is, ΣSi
If = 0, the error flag is set to "0" and the process ends. 2. When the addition result 加 算 Si of the syndrome Si is not “0” First, it is assumed that the number of errors is one.

[0027]

S0 = x1 * e1 S1 = x1 ² * e1 S2 = x1 ³ * e1 S3 = x1 ⁴ * e1

## EQU1 ## Therefore, the minimum condition for one error is:

[0029]

A = S1 ² + S0 * S2 B = S2 ² + S1 * S3 C = S0 * S3 + S1 * S2, A = B = C = 0

If S1 / S0 = x1, the variable x1 is obtained, and the data value at the position of the variable x1 is expressed as w1.
Since w1e = w1 + e1 as 1e, the correct data value w1 becomes w1 = w1e + e1, and the error flag process is performed by replacing the data value w1e of the variable x1 with the correct value w1 to complete the correction.

3. If A = B = C = 0 is not established in the above 2, the number of errors is assumed to be two or more. Here, the input data of the arithmetic circuit 4 is S0 to S5. First, a value x1 that does not actually exist is substituted for an error position xi to obtain Ti and Pi as follows.

[0032]

Equation 12] T0 = S1 + x1 * S0 T1 = S2 + x1 * S1 T2 = S3 + x1 * S2 T3 = S4 + x1 * S3 T4 = S5 + x1 * S4 P1 = T1 2 + T0 * T2 P2 = T2 2 + T1 * T3 P3 = T3 3 + T2 * T4

Next, when x1 is sequentially changed from 1 to n, 3-1. When P1 = P2 = P3 = 0 holds, it can be determined that the number of errors is two. At this time

[0034]

A = T1 / T0 B = T3 / T2

The value of xi at which A + B = D becomes "0" is sequentially stored in the arithmetic register 5. In this operation, it is also possible to omit the parity part from the codeword in order to reduce the processing time. By the above operation,
When the number of errors is two, the value of the variable xi becomes x1, x2, and the value of D becomes "0" twice, so that the values of x1 and x2 are obtained. The error values e1 and e2 are

[0036]

E2 = T0 / (x1 + x2) e1 = S0 + e2

The values w1 and w2 are respectively calculated as w1 + e1,
The error flag processing is performed as w2 + e2, and the correction is completed. 3-2. In the case where P1, P2, and P3 do not simultaneously become "0" In this embodiment, in order to correct a three-word error, the error position x1 is deleted from each of the equations (Equation 4) that gives P1, P2, and P3 described above. Is used.

[0038]

A = P2 / P1 B = P3 / P2

If x1 is correct, then A = B holds, so the value of xi that satisfies A + B = D = 0 is sequentially stored in the register 5. Here, when the number of errors is 3, D
Becomes "0" three times, so that the error positions x1, x2,
x3 is determined, and then these error locations x1, x2, x3
To obtain error values e1, e2 and e3. First,

[0040]

Calculating E = x2 * T0 + T1, E = (x1 + x3) * (x2 + x3) * e3 Therefore, E / (x1 + x3) * (x2 + x3) = e3

Is calculated to obtain e3, and using this e3, the syndrome is corrected as follows.

[0042]

Equation 17] S0m = S0 + e3 = e1 + e2 S1m = S1 + x3 * e3 = x1 * e1 + x2 * e2 S2m = S2 + x3 2 * e3 = x1 2 * e1 + x2 2 * e2 Subsequently, by calculating the F = S1m + x1 * S0m F = (X1 + x2) * e2∴F / (x1 + x2) = e2

By calculating S0m + e2 = e1, finally, all the error positions x1 to x3 and the value e are obtained.
1 to e3 are required. 3-3. When there is no xi where D = 0 In this case, since the number of errors is considered to be four or more, only the error flag process is performed and no correction is performed.

Next, processing for scrambling using such error correction processing will be described. As described above, in the normal error correction, the syndrome S
The value of i, the signals A, B, and C shown in Expression 11 and the signals P1, P2, and P3 shown in Expression 12 are checked, and the correction operation mode is determined based on this value as follows. 1. 1. When all values of syndrome Si are “0”: no error If the addition result ΣSi of the syndrome Si is not “0”, (1) the number of errors is one: A = B = C = 0 holds. (2) The number of errors is two: A = B = C = 0 does not hold, and P1 = P2 = P3 = 0 holds. (3) The number of errors is 3 or more: A = B = C = 0 is not established, and P1 = P2 = P3 = 0 is not established.

Therefore, in each of the above error correction processing modes, the error can be corrected normally. Therefore, by scrambling the data stream by artificially changing each error correction processing mode, the clarity of the reproduced signal is improved. (Readability) can be changed.

An example of the scramble circuit will be described with reference to FIG. The syndrome Si is supplied to the input terminal 17A of the arithmetic circuit 4 from the input selector 3, and the syndrome Si is output to the output terminal 19 through the inversion buffer 18A or the non-inversion buffer 18B. The inverting buffer 18A is controlled by a control signal Z applied to a control terminal 17B, and the non-inverting buffer 18B is controlled by a control signal Z obtained by inverting the control signal Z by an inverter 18C.

[0047] Thus, in the normal error correction Figure 1
The PC control unit 6 shown in FIG.
Is applied to the control terminal 17B , the inversion buffer 18A turns off and the non-inversion buffer 18B turns on, so that the input syndrome Si passes through the non-inversion buffer 18B as it is.

[0048] On the other hand, the control signal K by inverting buffer 1 8A is on a PC control unit 6 sets the scramble mode signal Z of a high level when the scramble mode is set from the function key 4, a non-inverting buffer 1 8B Turns off, so the input syndrome S
i is inverted by inverting buffer 1 8A. As a result,
In the scramble mode, the above-mentioned condition 1 is changed to condition 2, and correct data is error-corrected to incorrect data and partially scrambled.

FIG. 4 shows another example of the scramble circuit.
In this example, scrambling is performed by changing the signals A, B, and C shown in Expression 11. In the circuit shown in FIG. 4, three circuits shown in FIG. 3 are provided for each of the signals A, B, and C, and each circuit is controlled by control signals Z _A , Z _B , and Z _C from the PC control unit 6, respectively. You. For example, the condition 1 is changed to the condition 2 (1), 2 (2) or 2 by changing only the signal A and not changing the signals B and C.
It can be changed to (3) and therefore scrambled. Similarly, the signal P shown in Expression 12
By changing P1, P2 and P3, condition 2 (1), 2
Since (2) or 2 (3) can be changed, scrambling can be performed.

Next, referring to FIG. 5 and FIG.
The process of correcting the C1 and C2 sequences of the double Reed-Solomon code will be described. First, the C1 correction processing will be described with reference to FIG. When the C1 correction process starts (step 101), first, the syndromes S0 to S3 are checked by the expression [C1] shown in the upper part of the following expression (expression 18) (step 102), and then the expression is expressed by the following expression (expression 19). The syndromes S0 to S3 are converted into exponents (α → i) (step 103).

[0051]

[C1] S0 = W0 + W1 + W2 +... + W23 S1 = α ²³ W0 + α ²² W1 + α ²¹ W2 +... + W23 S2 = α ⁴⁶ W0 + α ⁴⁴ W1 + α ⁴² W2 +... + W23 S3 = ^{α 69 W0 + α 66 W1 +} α 63 W2 + ····· + W23 [C2] S0 = W0 + W1 + W2 + ····· + W31 S1 = α 31 W0 + α 30 W1 + α 29 W2 + ····· + W31 S2 = α 62 W0 + α 60 W1 + α 58 + W31 S3 = α ⁹³ W0 + α ⁹⁰ W1 + α ⁸⁷ W2 +... + W31 S4 = α ¹²⁴ W0 + α ¹²⁰ W1 + α ¹¹⁶ W2 +... + W31 S5 = α ¹⁵⁵ W0 + α ¹⁵⁰ W1 + α ¹⁴⁵ W2 +.・ + W31

[0052]

C1: S0 S1 S2 S3 C2: S0 S1 S2 S3 S4 S5

Next, it is determined whether or not all the syndromes S0 to S3 are "0" (step 104). If YES, the C1 error flags F0, F1, and F2 are both set to "0".
Is written (step 105), the block address is incremented by one (step 106), and the above processing is repeated until all blocks are completed (step 10).
7).

On the other hand, if all of the syndromes S0 to S3 are not "0" at step 104, first, modified syndromes σ1 to σ3 for detecting a one-word error are calculated based on the following equation (Equation 20). Next, it is determined whether or not there is a one-word error according to the following equation (Equation 21) (step 109).

[0055]

Σ1 = S1 + S0 * S2 σ2 = S2 + S1 * S3 σ3 = S1 * S2 + S0 * S3

[0056]

Σ1 + σ2 + σ3 = 0 One word error σ1 + σ2 + σ3 ≠ 0 One word error or more

In the case of a one-word error, one-word correction is performed based on the following equation (Equation 22) to write corrected data Wi (step 110). Then, based on Table 1, "1" is set in the C1 error flag F0. "1" is written (step 111). Next, the block address is incremented by one (step 112), and the process proceeds to step 107.

[0058]

(1 word correction) Error location: Xi = S1 / S0 Error value: Ei = S0 Correction: Wi = S0 + Di (Di: error data)

[0059]

[Table 1]

On the other hand, if it is not a one-word error in step 109, X1, X2, ψ1 to ψ3 for detecting a two-word error are calculated by the following equation (Equation 23), and then the following equation (Equation 24) is obtained. It is determined whether or not there is a two-word error (step 114).

[0061]

(Equation 23)

[0062]

２４1 + ψ2 + ψ3 = 0 Two-word error ψ1 + ψ2 + ψ3 ≠ 0 Two-word error or more

In the case of a two-word error, two-word correction is performed based on the following equation (Equation 25) (step 115), and the corrected data Wi,
Wj is written (step 116), and then "1" is written to the C1 error flags F0 and F1 as shown in Table 1 (step 117). Next, the block address is incremented by one (step 118), and step 107 is performed.
Proceed to.

[0064]

(Equation 25)

[0065]

[Equation 26] [Correction of Wi and Wj] S0 = Ei + Ej S1 = Xi * Ei + Xj * Ej Xj * S0 + S1 = (Xi + Xj) * Ei Ei = (Xj * S0 + S1) / C1 Ej = S0 + Ei Wi = Ei + DiWj

If a two-word error is not detected in step 114, "1" is written into each of the C1 error flags F0, F1, and F2 as shown in Table 1 (step 1).
19) Then, the block address is incremented by one (step 120), and the process proceeds to step 107.

Next, the C2 correction processing will be described with reference to FIG. The C2 correction processing is started after the C1 correction processing is completed (step 121), and first, the above equation (Equation 18) is obtained.
The syndromes S0 to S5 are checked by the lower stage [C2] (step 122), and then the syndromes S0 to S5 shown in the lower stage of the above equation (Equation 19) are converted into exponents (α →
i) is performed (step 123). Next, the C1 error flag is read, and the number N (E) of error flags and the error position Xi are detected by the following equation (Equation 27) (step 12).
4).

[0068]

[C1 Flag Calculate] Read: C1 Flag Location Count: C1 Flag Number Resister: C1 Flag Location X1, X2, X3
X4, X5, X6

Then, it is determined whether or not the number of errors is "0" by determining whether or not all of the syndromes S0 to S5 are "0" (step 126).
2 "0" is written to the error flags F0 and F1 (step 127), and then the block address is incremented by one (step 128). If all the blocks have not been completed, the process returns to step 122.
The two correction processing ends (step 129).

On the other hand, if all the syndromes S0 to S5 are not “0” in step 126, the above equation (Equation 2) is obtained.
0) to determine whether there is a one-word error (step 132). Then, in the case of a one-word error, one-word correction is performed based on the above equation (Equation 21) to correct the corrected data Wi.
Is written (step 133), and then "0" is written to the C2 error flags F0 and F1 (step 134).
Next, the block address is incremented by one (step 135), and the process proceeds to step 129.

[0071] When the present invention is not a one word error at step 132, step if the number of errors ERR for each frame, it is determined whether or not it exceeds the set value N _p (step 136), it does not exceed 136
The process proceeds to the following, and if exceeded, proceeds to the erasure routine.

In step 137, whether or not there is a two-word error is determined by the above equation (Equation 24), and in the case of a two-word error, two words are corrected based on the above equation (Equation 25) (Step 138). The corrected data W is calculated by the equation (Equation 26).
i and Wj are written (step 139), and then "0" is written to the C2 error flags F0 and F1 (step 14).
0). Next, the block address is incremented by one (step 141), and the process proceeds to step 129. Also,
If there is no two-word error in step 137, the process proceeds to the erasure routine. In the erasure routine, the syndrome is corrected as follows according to the number N of the error flags.

[0073]

Equation 28] [6Erasure, Y6] T5 = S5 + E1 * S4 + E2 * S3 + E3 * S2 + E4 * S1 + E5 * S0 Y6 = T5 / I6 [syndrome correcting] S0 + Y6 → S0 S1 + Y6 * X6 → S1 S2 + Y6 * X6 2 → S2 S3 + Y6 * X6 3 → S3 S4 + Y6 * X6 ⁴ → S4

[0074]

[5Erasure, Y5] T4 = S4 + D1 * S3 + D2 * S2 + D1 * S1 + D
4 * S0 Y5 = T4 / I5 [Syndrome correction] S0 + Y5 → S0 S1 + Y5 * X5 → S1 S2 + Y5 * X5 ² → S2 S3 + Y5 * X5 ³ → S3

[0075]

[4Erasure, Y4] T3 = S3 + C1 * S2 + C2 * S1 + C3 * S0 Y4 = T3 / I4 [Correction of syndrome] S0 + Y4 → S0 S1 + Y4 * X4 → S1 S2 + Y4 * X4 ² → S2

[0076]

[3Erasure, Y3] T2 = S2 + B1 * S1 + B2 * S0 Y3 = T2 / I3 [Correction of syndrome] S0 + Y3 → S0 S1 + Y3 * X3 → S1

[0077]

[2Erasure, Y2] [1Erasure, Y1] T1 = S1 + X1 * S0 Y2 = T1 / I2 Y1 = S0 + Y2

Next, another embodiment of the scramble reproducing apparatus will be described. By the way, 2 (1) of the above condition 2
, The number of rewritable data when the number of errors is 1 is 1 out of 24 for CD, 1 out of 32 for DCC,
When the number of errors is 2 in 2 (2), the number of rewritable data is 2 out of 24 for CD, 2 out of 32 for DCC, and 3 for 2 (3). The number of rewritable data is 3/24 for CD and 3/32 for DCC, which is an appropriate number.

Therefore, in this embodiment, one scramble circuit is used as shown in FIG.
By inverting the Q and intentionally causing an error, the clarity at the time of reproduction can be changed and scrambled.
If an error is intentionally generated by inverting the codes P and Q in the above cycle, noise is generated. Therefore, the following processing can prevent generation of noise.

FIGS. 7 and 8 show silence processing when error correcting the C1 and C2 sequences of the double Reed-Solomon code, respectively, and correspond to FIGS. 5 and 6 described above. In the C1 correction, in the case of a one-word error, one-word correction is performed in the same manner as in FIG. 5 (step S110). In this embodiment, when the original data WSi is “0”, the corrected data Wi is not written (step S110). (S111A → S111C), and if the original data WSi is not “0”, the correction data Wi is written (steps S111A → S111B). Step S
In 111C, "1" is set in the error flag F0, and F1 and F
“0” is written in 2.

In the case of a two-word error, two-word correction is performed (step 115). However, when the original data WSi or WSj is "0", the corrected data Wi and Wj are not written (steps S116A → S117). If the original data WSi or WSj is not "0", the correction data Wi and Wj are written (steps S116A → S116).
B)

Similarly, in the C2 correction shown in FIG. 8, the correction data Wi and Wj are written only when the original data WSi or WSj is not "0" (steps S134A to S134A).
S134C, S139A, 139B). Thus, when the original data WSi or WSj is "0", the corrected data W
By not writing i and Wj, silence data can be output silently, so that generation of noise can be prevented.

Further, according to this embodiment, as shown in FIG.
In synchronism with the cycle of the signal A (or P1), for example, the signal B (or P2) has a cycle of 1/2 of the syndrome Si, and the signal B (or P2) has a cycle of 1/2 of the syndrome Si.
In 3), scrambling can be performed by changing the period in the eighth cycle of the syndrome Si.

In this case, the syndrome Si and the signal A
(Or P1), B (or P2), and C (or P3) are changed from condition 1 to conditions 2 (1), 2 (2), and 2 (3), so that the number of partially rewritten data is And thus the clarity of the reproduced signal can be changed. Also. Similarly, in this case, the original data is “0”.
In this case, by not writing the correction data Wi and Wj, it is possible to output silently when there is no sound, so that generation of noise can be prevented.

[0085]

As described above, according to the present invention, scrambling can be performed by changing the syndrome at the time of reproduction. For example, by reversing the syndrome or the modified syndrome, or making the reversal cycle variable, The clarity at the time of reproduction can be freely changed without providing a circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an error correction decoding unit which is a main part of an embodiment of a scramble reproducing apparatus according to the present invention.

FIG. 2 is a block diagram schematically illustrating a scramble reproducing apparatus having the error correction decoding unit of FIG. 1;

FIG. 3 is a block diagram illustrating an example of a scramble circuit in the arithmetic circuit in FIG. 1;

FIG. 4 is a block diagram showing another example of the scramble circuit in the arithmetic circuit of FIG. 1;

FIG. 5 is a flowchart for explaining an operation in which the error correction decoding unit in FIG. 1 performs error correction on a C1 sequence of a double Reed-Solomon code.

FIG. 6 is a flowchart illustrating an operation in which the error correction decoding unit in FIG. 1 performs error correction on a C2 sequence of a double Reed-Solomon code.

FIG. 7 is a flowchart for explaining silence processing when performing error correction on a C1 sequence of a double Reed-Solomon code in another embodiment of the present invention.

FIG. 8 is a flowchart for explaining silence processing when performing error correction on a C2 sequence of a double Reed-Solomon code in another embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Syndrome check part 2 Syndrome register 3 Input selector 4 Arithmetic circuit (comprising a scrambler with the PC control part 6 and the function key 14) 5 Arithmetic register 6 PC (program counter) control part 7 Program counter (PC) 8 ROM 9, 12 Decoder 13 Error correction decoding unit (decoding means) 14, 40 Function key 18A Non-inverting buffer 18B Inverting buffer 18C Inverter 20 Encoder 30 Error correction encoding unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20 / 18,20 / 10 H03M 13/00

Claims (1)

(57) [Claims] 1. A system for calculating a syndrome of reproduced data of data that has been error-corrected by Reed-Solomon code.
To set a Ndoromu calculating means, the scramble mode and non-scrambled mode
And means, by changing the syndrome so that it can not be error correction decoding properly when the scramble mode outputs, wherein
Change the syndrome in non-scramble mode
And scrambling means for outputting a no, the row error correction based on the output of the scramble means
Decoding means, reproduction in the scramble mode and non-scramble
System that sets the time ratio of playback in mode at a predetermined ratio
And a control unit .