JP3320562B2 - Computer with cache memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer having a cache memory.

[0002]

2. Description of the Related Art A multiplexing computer employs a checkpoint restart method in which the progress of a program execution (checkpoint) is stored in a main memory, and when a failure occurs, the checkpoint is restarted from the checkpoint. Then, there is a configuration in which a system down is avoided.

The checkpoint restart method is disclosed in, for example, US Pat. No. 4,819,154, US Pat.
54,819, JP-A-59-160899, and a paper Philip A. Bernstein, "Sequoia: A Fault-Tolerant
Tightly Coupled Multiprocessor for Transaction Pro
cessing, "IEEE Computer, Feb. 1988, pp. 37-45.

FIG. 6 shows an example of a system configuration of a multiplexing computer adopting a checkpoint restart method. The multiplexing computer shown in FIG. 6 includes two processor elements (PE1) 10a, (PE2) 10b, and 1
Two memory elements (ME1) 12 are connected to each other via a system bus 14. The respective processor elements (PE1) 10a, (PE
2) 10b operates independently. Each processor element (PE1) 10a, (PE2) 10b has an MP
U16a, 16b, cache memories 18a, 18b,
And cache controllers 19a and 19b. Management of data in the cache memories 18a and 18b is performed by cache controllers 19a and 19b, which are dedicated hardware. Also, M
PUs 16a and 16b have a plurality of registers, which are indicated by R1,..., Rn in the figure.

FIG. 7 shows a flow of processing when a failure occurs in the checkpoint method.
The operation of the multiplexing computer shown in FIG. 6 will be described below according to the flow shown in FIG.

Time t for performing checkpoint processing
(N), the processor element (PE1) 10
The MPU 18a of "a" suspends the temporary processing and stores the contents R1,..., Rn of all the registers in the memory element (ME1).
The data is directly written to the twelve fixed areas C1. Then, the updated data DB1,..., DBk of the cache is written back to the memory element (ME1) 12 (P0 in FIG. 7).

When the checkpoint processing is completed, the interrupted processing is resumed. Thereafter, when the failure X occurs in the processor element (PE1) 10a, the processor element (PE1) 10a is disconnected from the system configuration, and the processor element (PE2) 10b
The processing performed by the processor element (PE1) 10a is taken over.

At this time, the processor element (PE2)
12b restarts the processing from the state of the program stored in the memory element (ME1) 12 at the check point t (n).

[0009] Processor element (PE2) 10b
Restarts the processing performed by the processor element (PE1) 10a from the point of time P0, so that the processing results performed by the processor element PE1 from P0 to X shown in FIG. 7 must be invalidated.

This is realized by preventing the updated data of the cache block CB from being written back to the memory element (ME1) 12 except at the checkpoint. For this reason, in order to prevent the checkpoint process from being performed frequently, the cache system generally uses, for example, an n-way set associative system and provides a large-capacity cache of several MB.

In this type of cache system, when data in a cache block needs to be written back to a memory element, an interrupt is issued to the MPU. The MPU outputs a process of writing data back to the memory element, that is, a flash special instruction FC for executing a flash operation to the cache controller.

The cache controller starts a flush operation, and a cache tag (valid bit V indicating that data is valid and data are rewritten) for managing data stored in the cache memory in units of cache blocks. (Including a dirty bit D indicating that the data has been deleted). Where the rewritten data,
That is, if there is a block whose dirty bit D is "1" (indicating that the block has been rewritten), the block is written back to the memory element. This operation is performed for all areas of the cache.

Conventionally, when an access request is received from the MPU while the above-described flash operation is being performed, the MPU must wait until the flash operation is completed. That is, if data in the cache memory is changed in response to an access request from the MPU during the flash operation, consistency with data written back to the memory element may be lost. .

[0014]

As described above, in the conventional multiplexing computer, in order to maintain data consistency during the flash operation, it is necessary to keep the MPU on standby even if there is a processing request from the MPU. was there. Although the flush mechanism is implemented by hardware, it takes a very long time since the tags of all blocks in the cache must be searched. Therefore, the MPU requesting the processing during the flash operation may be kept on standby for a very long time.

The present invention has been made in view of the above circumstances, and provides a computer capable of executing a processing request from an MPU generated during a flash operation of writing back cache block data to a main memory. The purpose is to provide.

[0016]

SUMMARY OF THE INVENTION The present invention provides processing means for performing arithmetic processing, cache memory divided into a plurality of cache blocks used by the processing means, and cache control means for controlling the cache memory. In a computer connected via a system bus to a memory element that stores instructions and data handled by the processing means, the processor element having the following features: the cache control means, as a status for managing the cache memory, The management is performed using a valid bit V indicating that valid data is present in the cache block and a dirty bit D indicating that data stored in the cache block has been updated. According to the prescribed order ,
Checking the cache status of all cache blocks, executing a cache flush for writing data of the updated cache block to the memory element, and performing a flush execution notification indicating that a cache flush is being performed; and Flash means for giving a flash interruption notification indicating that the cache flush is interrupted by an access request from the means, wherein the flash means, when the flash execution notification indicates that the flash is being executed, an access request by the processing means. If there is, the cache flush is suspended and a flush suspension notification is issued, so that the access processing by the processing means can be executed.

Thus, even during the execution of the flush, the access request from the processing unit (MPU) can be executed with priority, and the waiting state of the processing unit can be avoided.

Further, the cache control means includes a flush completion bit F indicating that the updated data of the new cache block has been written back to the memory element.
Is provided as the status to manage the cache memory, and when there is a write access request from the processing unit, a write process for executing a write process on the cache block targeted for the write access request If the processing unit and the cache block to be subjected to the write processing by the write processing unit are dirty blocks and are not blocks in which cache flushing has been completed before the flushing by the flushing unit is interrupted, the data of the cache block is deleted. the write back to the memory element, a write-back means for setting a flash completion bit F of the status corresponding to the cache block flushed, further comprising a said flash unit is off by the write back means
If the rush completion bit F is set to be flushed, writing back to the memory element is not performed.

Thus, the target block of the access request when the cache flush is interrupted is managed so as not to cause data inconsistency depending on whether or not the flush has been completed before the flush is interrupted.

Further, the cache control means is newly provided.
The updated data in the cache block is
Flush completion bit F indicating that the
And the status is further provided as the status.
A memory is managed, and when an access request is issued from the processing unit during execution of a cache flush by the flush unit and a cache allocate is performed on the cache memory, the block is not valid based on the status and the block is not dirty. If a block is preferentially evicted and there is no block to be evicted, the cache block whose access target by the processing unit is other than the block whose flush has been completed and whose flush completion bit F is not set to flushed Write back to memory element
It is characterized by further comprising writing back means .

Thus, when a cache overflow occurs, by referring to the flush completion bit F, a block that needs to be rewritten is expelled.
Data consistency is maintained regardless of flush interruption.

Further, in the above-mentioned electronic computer, wherein the memory element is duplicated, the flash means, when performing a cache flush for the first memory element, receives all write access requests from the processing means. On the other hand, the flush completion bit F is set to flushed, and cache flush for the second memory element is performed based on the status including the flush completion bit F.

Thus, even in a system in which memory elements are duplicated, even when cache flush for each memory element is interrupted, an access request of the processing unit (MPU) is executed while maintaining data consistency. be able to.

[0024]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining a detailed configuration of the cache controller in the multiplexing computer according to the present embodiment. It is assumed that the schematic configuration of the multiplexing computer is the same as that of FIG. 6 used in the description of the related art. FIG. 1 shows only one processor element (PE1) 10a and memory element (ME1) 12.

The processor element 10a includes an MPU
16a, a cache memory (CM) 18a, and a cache controller 51 are provided. It is assumed that a cache controller having the same configuration as the cache controller 51 is provided in the other processor element (PE2) 10b.

In this embodiment, the cache memory (C
M) 18a has 32K lines, 4 blocks / line, 3
It is assumed that the configuration is 2 bytes / block. MPU16
It is assumed that the MPU address MA output by a is 32 bits as shown in FIG. Cache memory 1
8a has an MPU address M
A is addressed by bits 18 to 5 of A (block address BA), and each byte in the cache block CB is
It is addressed by bits 4 to 0 of the PU address MA.
Bits 31 to 19 (address tag TA) of the MPU address MA are used to determine a cache hit / miss by a cache tag described later.

The cache controller 51 is dedicated hardware for managing data in the cache memory 18a (details will be described later). In this embodiment, it is assumed that a 4-way set associative system is used.

As shown in FIG. 1, the cache controller 51 includes a tag (TAG) block 52, a processor interface (PIF) block 53, a read operation (ROP) block 54, a write operation (WOP) block 55, and a cache allocate (C).
A) Block 56, copy back (WB) block 5
7. Flash operation (FOP) block 5
8. System bus interface (SIF) block 5
9 and a multiplexer (MUX) 60.

The TAG block 52 stores a cache tag for managing data in the cache memory 18a. The structure of the cache tag is shown in FIG.
Shown in The cache tag is addressed by the block address BA of the MPU address MA, and blocks (4 blocks) for one line are read at a time. The cache tags of each block in one line are TAG0, TAG1,
TAG2 and TAG3 are distinguished. The cache tag includes an address tag TA and a cache status STA.
It is composed of T. The bits 31 to 19 of the MPU address MA are stored in the address tag TA, and are used to determine whether the data to be accessed exists in the cache memory 18a (cache hit / miss). The cache status STAT includes a valid bit V indicating that the block is valid (V = 1 indicates valid), a dirty bit D indicating that the block is updated (D = 1 indicates dirty), A flash bit F (F = 1 indicates completion of flushing) indicating that flushing of data in the cache memory 18a has been completed. In the following description, TAG, TA,
When it is represented as STAT, it indicates a block that has hit the cache. When expressed as TAGi, TAi, or STATi, it indicates the tags of all the lines (i = 0, 1, 2, 3).

The PIF block 53 manages an interface with the MPU 16a, and receives an MPU address MA, various instructions (read access request RD, write access request WD, flash special instruction FC, etc.), and exchanges data. The PIF block 53 includes the MPU 16a
When a read access request (RD) is received from the MPU 16a, the ROP block 54 is started, and a write access request (WR) and a WOP block 55 are started from the MPU 16a. When the flash special instruction FC is issued from the MPU 16a,
The PIF block 53 activates the FOP block 58 to execute the flash processing. Also, the MPU 16a
MP that indicates this when there is an access request from
The FOP block 58 is notified of a U access signal DP (DP = 1 indicating that an access request is made). That is, MP
The U access signal DP interrupts the flush operation by the FOP block 58 so that the access request can be processed.

The ROP block 54 is a PIF block 5
3 and reads data from the cache memory 18a based on the tag (TA, STAT) obtained from the TAG block 52 upon a cache hit (notification of Hit = 1 from the TAG block 52).
When a cache miss occurs, the CA block 56 is activated,
Reading of data from the memory element 12 is executed.

The WOP block 55 is a PIF block 5
3 is activated by a TAG block 5 upon a cache hit (a notification of Hit = 1 from the TAG block 52).
Based on the tag (TA, STAT) obtained from Step No. 2, writing to the cache memory 18a is performed. At the time of a cache miss, the CA block 56 is activated to read data from the memory element 12.

The CA block 56 is a ROP block 5
4 and activated from the WOP block 55, upon a cache miss, valid data is read from the memory element 12 via the SIF block 59 and written into the cache memory 18a.

The WB block 57 is composed of the FOP block 5
8, which is started from the WOP block 55 or the CA block 57, and writes back the data to be written back in the cache memory 18a (the cache status STAT (D) is "1") to the memory element 12 via the SIF block 59 (copy back). ).

The FOP block 58 controls the flash processing. Based on the tag stored in the TAG block 52, the FOP block 58 uses the WB block 57 to store data to be written back in the cache memory 18a in the memory element 1
Flash to 2. FOP block 58
Is activated by the PIF block 53 when the flash special instruction FC is output from the MPU 16a (FC
Notification), TAG block 5 according to MPU address MA
2 to the cache tag TAGi (i = 0, 1, 2, 3)
To check the tag address TA and the cache status STAT (valid bit V, dirty bit D, flash bit F). FOP block 5
Reference numeral 8 denotes a flush execution signal DF (DF = 1 indicating that flushing is being performed) when the flush operation is started in response to the FC notification, and an access request (MPU access signal DP = 1) from the MPU 16a during the flush operation. ), The flash interrupt signal AF (AF = 1 indicates flash interrupt) is output to the PIF.
Output to the ROP 54 or the WOP block 55 via the block 53. The FOP block 58 includes TA
A search address counter (SA) 58a indicating the position (line) of the G block 52 to be searched is provided.

The system bus interface (SIF) block 59 manages an interface with the memory element 12, and is connected to the ROP block 54, the WOP block 55, the CA block 56, and the WB block 57.

The multiplexer (MUX) 60 has an MPU
MPU address MA from 16a (block address B
A) and MPU address M from FOP block 58
A is input and supplied to the TAG block 52 alternatively. Normally, the MPU address MA from the MPU 16a is selected, and the FOP block 58
And supplies the selected MPU address MA.

Next, the operation of the computer system in this embodiment will be described. First, the flash operation will be described. First, the cache special command FC from the MPU 16a is sent to the cache controller 51 by the PIF.
Received by block 53. PIF block 53
Starts the FOP block 58 (FC notification) and starts the flash operation. On the other hand, the bus transaction is completed for the MPU 16a.

When activated, the FOP block 58 clears a search address counter (SA) 58a to "0",
The flash execution signal DF is set to "1". The flash execution signal DF is kept at “1” until the flash operation is completed.

Next, the FOP block 58 reads the cache tag TAGi (i = 0, 1, 2, 3) indicated by the search address counter (SA) 58a from the TAG block 52, and reads the valid bit STATi of the cache status.
(V) (i = 0, 1, 2, 3) and dirty bit S
Check TATi (D) (i = 0, 1, 2, 3) and flash bit STATi (F) (i = 0, 1, 2, 3).

Here, the flash bit F of each block is
Is “0”, the valid bit V is “1”, and the dirty bit D is “1”, the cache block CB has been updated (dirty block), and the FOP 58
Starts the WB block 57. WB block 57
Stores the data of the corresponding block in the cache memory 18 in accordance with the corresponding TAGi (i = 0, 1, 2, 3).
a, and is written back to the memory element 12 via the SIF block 59 (copy back).

When copy-back is completed for each block in one line, the FOP block 58 counts up (+1) a search address counter (SA) 58a. When the dirty bits D of all the blocks in one line are "0", the FOP block 58 counts up the search address (SA) 58a (+1) because there is no data to be written back to the memory element 12. Just move the search target to the next line.

At this time, if the flush completion bit STATi (F) of the cache status STAT is "1", since the block has already been copied back to the memory element, even if the dirty bit D = 1, the copy back is performed. , The flash completion bit ST
ATi (F) is cleared to "0".

The above processing is performed by searching all the cache areas, that is, all the cache tags of the TAG block 52.
This is performed for each cache block. By the way, when an access request is received from the MPU 16a during the execution of the above-described flush operation, when a certain transaction is completed and the cutoff is good, for example, the FOP block 58
Counts up the search address (SA) 58a (+
After 1), the flash interrupt signal AF is set to "1" to interrupt the flash operation.

Thereafter, when the processing for the access request from the MPU 16a is completed (DP = 0), the flash suspension signal AF is cleared to "0" and the flash operation is restarted. That is, in the system of the present invention, when there is an access request (read access request RD, write access request WD) from the MPU 16a even during the flash operation, the MPU 16a does not wait until the flash operation is completed. Then, the flash operation is interrupted so that the access request can be executed with priority.

When there is an access request from the MPU 16a,
The PIF block 53 sets the MPU access signal DP to “1”. At this time, the flash is being executed (DF
= 1), the CPU waits for the flash operation to be interrupted (AF = 1), and starts the requested processing.

When the flash is interrupted (AF = 1),
The MPU 16a accesses. The operations performed when there is a read access request RD and a write access request WD will be described later.

When the access to the MPU 16a is completed, the MP
The U16a access signal DP is cleared to "0", and the flash operation is restarted. Next, a case where a read access request RD is received from the MPU 16a will be described.

Read access request RD from MPU 16a
If there is, the PIF block 53 sets the MPU access signal DP to “1” and cancels the flash operation by FO.
Request to P block 58.

When the interruption of the flash operation is requested by the MPU access signal DP, if the flash is being executed,
The FOP block 58 executes the above-described processing for flash suspension, and executes the flash suspension signal AF.
Is set to “1”.

When the flush operation is interrupted or completed (AF = 1 or DF = 0), the FOP 58 reads the cache tag TAGi indicated by the search address counter (SA) 58a from the TAG block 52.

Here, when the cache hits (H
it = 1), the ROP 54 returns the hit TAG (TA,
STAT), and reads data from the cache memory 18a and transmits the data to the MPU 16a. Then, the ROP 54 sets the MPU access signal DP to “0” (notifies the FOP block 58 via the PIF block 53) so that the flash operation can be resumed. Further, the FOP 58 sets the flash suspension signal AF to “0”.

On the other hand, if the cache misses (Hit = 0), the ROP 54
, The CA block 56 is activated for cache allocation, and data is read from the memory element 12 via the SIF block 59.

The CA block 56 has valid bits STATi (V) (i = 0, i = 0,...) Of all blocks in the line designated by the block address BA of the tag block 53.
1,2,3) and dirty bit STATi (D) (i
= 0, 1, 2, 3).

Effective bit STATi (V) in one line
If there is a block for which is not set to "1", cache allocation is performed on the block because the data of the block is unnecessary.

When the valid bits STATi (V) of all the blocks in one line are set to "1", it is necessary to evict one of the blocks from the cache.
Normally, a flush operation is performed by notifying the MPU 16a of a cache overflow. However, in the case of processing for an access request during a flush operation, any block is evicted from the cache as follows.

Generally, which block is evicted is determined based on, for example, a random method or an LRU (Least Recently Used) method. In the cache evicting method of the present invention, the dirty bit STATi is further determined.
A block in which (D) is not set to "1" (there is no need to write data back to the memory element 12) is preferentially evicted to perform cache allocation.

There is no corresponding block (all dirty bits STATi (D) are "1"), and the search address (SA) 58a is smaller than the block address BA (S
A <BA), that is, as shown in FIG. 4A, if the flash of the target block has not been completed and there is a block whose flash bit STATi (F) is “0”, the WB block 57 Then, the data of the block is written back to the memory element 12 (copy back). Then, cache allocation is performed on the cache block.

On the other hand, as shown in FIG.
If the search address SA is greater than or equal to the block address BA (SA
≧ BA) dirty bits S of all blocks in one line
When TATi (D) is "1" or when search address SA
Is smaller than the block address BA (SA <BA, flash has not been completed), the flash bit STATi (F) of all blocks in one line is “1”, and the dirty bit STATi (D) is “1”. , The cache allocation fails.

In this case, the cache overflow is notified to the MPU 16a, and all processes of the MPU 16a are kept waiting until the current flush operation is completed. When the current flash operation is completed, the flash instruction needs to be executed again.

If the cache allocation succeeds, RO
The P block 54 reads the data requested by the MPU 16a from the cache memory 18a and transmits the data. next,
A case where a write access request WD is received from the MPU 16a will be described.

Write access request WR from MPU 16a
If there is, the PIF block 53 sets the MPU access signal DP to “1” and cancels the flash operation by FO.
Request to P block 58.

When an interruption of the flash operation is requested by the MPU access signal DP, if the flash is being executed,
The FOP block 58 executes the above-described processing for flash suspension, and the flash suspension signal A
F is set to "1".

When the flush operation is interrupted or completed (AF = 1 or DF = 0), the FOP 58 reads from the TAG block 52 the cache tag TAGi indicated by the search address counter (SA) 58a.

Here, when the cache hits (H
it = 1) and the flash bit STAT (F) of the cache status is “1”, the WOP 55
Performs writing to the cache memory 18a.
Block (S
The write operation for (A ≧ BA) succeeds.

When the cache hits (Hit =
1) and the flash bit STAT of the block
When (F) is “0” and the dirty bit STAT (D) is “1”, the search address SA is the block address BA
If smaller (SA <BA), the block has not been flushed to the main memory, so the data of the block is written back to the memory element (ME1) 12 (copy back), and the flash bit STAT (F) is set to "1". Set to.

On the other hand, if there is a cache miss (Hit = 0), the WOP 55 activates the CA block 56 and reads data from the memory element 12 via the SIF block 59 to perform cache allocation.

The CA block 56 misses the cache in response to the read access request RD (H
cache allocation is performed as in the case of (it = 0).

If the cache allocation succeeds, CA
The block 56 performs writing from the MPU 16a,
If the dirty bit D and the search address SA are smaller than the block address BA (SA <BA), the flash bit F of the cache status STAT is also set to “1”.

When the write access from the MPU 16a is completed, the PIF block 53 outputs the MPU access signal D
P is set to "0" to restart the flash operation.
At the same time, the FOP 58 reads the cache tag from the TAG block 52 again, and
Inspect T.

The search address SA is the block address BA
Smaller (SA <BA), the valid bit STATi (V) and dirty bit STATi (D) of all the cache blocks in one line, and the flush completion bit STA
When Ti (F) is all "1", or search address SA
Is the block address BA or higher (SA ≧ BA) and the valid bit STATi of the cache block of all one line
(V) and dirty bit STATi (D) are all "1"
In this case, a cache overflow interrupt is generated for the MPU 16a.

In this way, when the cache controller 51 receives the flush special instruction FC from the MPU 16a, the cache controller 51 checks the cache status STAT of the cache tag by the FOP block 58, and writes the block whose data has been updated to the memory element. return. At this time, the read access request RD from the MPU 16a
Alternatively, when there is a write access request WD, the cache flash operation is interrupted, a flash interrupt signal AF is sent to notify, and the access request is made executable.
As a result, the flash operation is interrupted and the MPU 16
The access request a can be executed with priority.

When the flush operation by the cache controller 51 is interrupted, the MPU 16a executes a read access or a write access. When performing a write access, if the block to be cached is already dirty (D = 1) and the flush has not been completed before the flush operation is interrupted (SA <BA), the cache element is written back to the memory element 18a, and the cache status is changed. The flash completion bit F is set to "1". When the flash operation is restarted, data consistency can be maintained irrespective of flash interruption by not writing back to the memory element 18a for the block whose flash completion bit F is "1".

When a cache overflow occurs during execution of a cache allocation due to an access request from the MPU 16a during a flash operation, a block to be evicted is basically determined by a random method or LR.
It is determined on the basis of the U method or the like, but more ineffective blocks (V = 0) and non-dirty blocks (D = 0) are preferentially expelled. If these blocks do not exist (V = 1, D = 1 If the flash operation has not been completed in the flash operation before the flash operation was interrupted and the flash completion bit F has not been set to "1", that is, the block which needs to be rewritten originally is stored in the memory element 1
Write back to 2 and perform cache allocation. Thus, data consistency can be maintained irrespective of flash interruption.

In the above-described embodiment, as shown in FIG. 6, a description has been given of a configuration in which one memory element (ME1) is provided. However, as shown in FIG. In the case of a redundant configuration, it is necessary to perform the cache flush operation twice (flash operation for each memory).

If there is an MPU access during the first flush operation, the MPU 16a will write only when the cache status is dirty (STATi (D) = 1) and the flash bit STAT (F) is 1, Waited. In other cases, the MPU 16a can execute the read access request and the write access request by interrupting the flush operation of the cache controller.

In this case, the search address SA and MPU1
Regardless of the magnitude of the block address BA of the access from 6a (regardless of whether or not the write-back has been completed before the interruption of the cache operation), the cache flash bit STAT (F) is set to "1" for the write operation. Set to.

During the first flash operation, the flash bit STATi (F) is not cleared. Therefore, at the time of the second flash operation, write-back is not executed for the block in which the flash bit STATi (F) is set to "1". The second flash operation is similar to the above-described operation.

As described above, in a system in which memory elements are duplicated, it is necessary to perform a flash operation on each memory element.
When the flash operation is interrupted due to an access request from the MPU 16a during the flash operation for the first memory element and the write access is performed, the flash completion bits F of all the target blocks are set to "1". As a result, the result of the write access with the interruption of the flash operation to the first memory element becomes 2
It can be prevented from being reflected in the second memory element. Writing to the first memory element is not affected if the flash is completed before the flash operation is interrupted (SA> BA), and the block is not completely flashed before the flash operation is interrupted (SA). Even if ≦ BA), it is not written back by setting the flash completion bit F to “1”. The contents of the block written by the MPU write access are as follows:
The data is written back to the memory element by the next flash operation. In this way, even in a system in which the memory elements are duplicated, the flash operation is interrupted and M
The access request of the PU can be executed.

[0080]

As described above in detail, according to the present invention, when an access request is issued from the MPU during a flash operation, the flash operation is interrupted and the MPU access is executed with priority. At that time, copy-back and cache allocation are performed so that data consistency is maintained before and after the interruption of the flash operation.
U can proceed without waiting.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a detailed configuration of a cache controller in a multiplexing computer according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining an MPU address MA in the embodiment.

FIG. 3 is a diagram illustrating a cache tag according to the embodiment.

FIG. 4 is a diagram for explaining block eviction in the embodiment.

FIG. 5 is a block diagram showing another configuration of the multiplexing computer according to the embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a configuration of a multiplexing computer.

FIG. 7 is a system configuration diagram for explaining checkpoint processing.

[Explanation of symbols]

10a: Processor element (PE1), 12: Memory element (ME1), 16a: MPU, 18a: Cache memory (CM), 52: Tag (TAG) block, 53: Processor interface (PIF) block, 54: Read operation ( ROP) block,
55: Write operation (WOP) block, 56
... Cache allocate (CA) block, 57 ... copy back (WB) block, 58 ... flash operation (FOP) block, 59 ... system bus interface (SIF) block.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 11/14

Claims (8)

(57) [Claims] 1. A processor element comprising: processing means for performing arithmetic processing; cache memory divided into a plurality of cache blocks used by the processing means; and cache control means for controlling the cache memory. In a computer connected via a system bus to a memory element for storing instructions and data handled by the means, the cache control means determines that there is valid data in a cache block as a status for managing the cache memory. And a dirty bit D indicating that the data stored in the cache block has been updated. In response to a predetermined instruction from the processing means, all cache blocks are managed. Said cash stay A cache flush which writes back the data of the cache block whose data has been updated to the memory element, executes a flush execution notification indicating that the cache is being flushed, and an access request from the processing means. A flash unit for performing a flash suspension notification indicating that the cache flush is suspended, wherein the flash unit is configured to perform a cache operation when the processing unit receives an access request when the flash execution notification indicates that the flash is being executed. An electronic computer, wherein a flash is interrupted and a flash interrupt notification is issued to enable execution of access processing by the processing means. 2. The cache control means according to claim 1, further comprising: providing a flush completion bit F indicating that the updated data of the cache block is newly written back to the memory element as the status, to manage the cache memory. A write processing unit that executes a write process on a cache block that is a target of the write access request when there is a write access request from the processing unit; and a cache that is a target of the write process by the write processing unit. If the block is a dirty block and the cache flush is not completed before the flushing by the flush unit is interrupted, the data of the cache block is written back to the memory element, and the status of the status corresponding to the cache block is returned. A write back unit to set the flash completion bit F in flushed, further comprising a said flash unit flash is by the write back means
2. The computer according to claim 1, wherein if the cache completion bit F is set to be flushed, writing back to the memory element is not performed. 3. The cache control means stores the updated data of a new cache block in a memory.
Flash complete bit indicating that the element has been written back
Is provided as the status, and the
Manages the Shumemori, there is an access request from said processing unit during execution of the cache flush by the flash unit, when performing the cache allocate to the cache memory, not a block or dirty not valid on the basis of the status If there is no block to be evicted and there is no block to be evicted, if the block to be accessed by the processing unit is other than the flash-completed block, the flash completion bit F
Write-back means to write back cache blocks that are not set to flushed to memory elements.
2. The electronic computer according to claim 1, wherein
Machine. 4. The computer according to claim 1, wherein said memory element is a duplicated computer, wherein said flash means, when performing a cache flush on said first memory element, outputs all write access requests from said processing means. A flush completion bit F is set as flushed, and a cache flush for a second memory element is performed based on the status including the flush completion bit F. Item 3. The electronic computer according to item 3. 5. A processor element comprising: processing means for performing arithmetic processing; cache memory divided into a plurality of cache blocks used by said processing means; and cache control means for controlling said cache memory. In a computer connected via a system bus to a memory element storing instructions and data handled by the means, the cache control means may determine that there is valid data in a cache block as a status for managing the cache memory. And a dirty bit D indicating that the data stored in the cache block has been updated. In response to a predetermined instruction from the processing means, all cache blocks are managed. Said cash stay Checking the status, executing a cache flush for writing the data of the updated cache block back to the memory element, and performing a flush execution notification indicating that the cache flush is being performed. A cache control method comprising: when a processing unit issues an access request, suspending a cache flush and notifying a flush interruption to enable execution of an access process during a cache flush operation by the processing unit. 6. The cache control means for managing the cache memory by further providing a flush completion bit F indicating that the updated data of the cache block is newly written back to the memory element as the status. When a write access request is issued by the processing unit during execution of the cache flush, when the cache block in the cache memory is already a dirty block and the cache flush is completed before the flush is interrupted, The data of the cache block is written back to the memory element, the flush completion bit F of the status corresponding to the cache block is set to flushed, and the cache whose flush completion bit F is set to flushed is set. Cache flash
6. The cache control method according to claim 5 , wherein writing back to the memory element is not performed in the cache. 7. The cache control means stores the updated data of a new cache block in a memory.
Flash complete bit indicating that the element has been written back
Is provided as the status, and the
The cache memory is managed, and when there is an access request from the processing unit during execution of a cache flush and a cache allocation is performed for the cache memory, an invalid block or a dirty block is preferentially determined based on the status. If there is no block to be evicted, and if the block to be accessed by the processing means is other than the flash-completed block, the flash completion bit F
6. The cache control method according to claim 5 , further comprising writing back the cache block that has not been set to be flushed to the memory element. 8. A computer in which said memory elements are duplicated, and when performing a cache flush on a first memory element, flushing is performed for all write access requests from said processing means. 8. The cache according to claim 6, wherein a completion bit F is set to be flushed, and a cache flush for the second memory element is performed based on the status including the flush completion bit F. Control method.