JP3319287B2 - Precoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a precoder,
In particular, the present invention relates to a precoder for encoding data to be recorded or transmitted.

[0002]

2. Description of the Related Art In a magnetic recording medium such as a magnetic tape or a magnetic disk, errors due to an increase in intersymbol interference and a decrease in a signal-to-noise ratio (S / N) of a reproduced signal due to an increase in recording density in recent years. In order to reduce the deterioration of the rate, it has been conventionally known that a digital signal to be recorded is encoded by a precoder using a partial response method and then recorded on a magnetic recording medium.

FIG. 2 is a block diagram showing an example of a conventional precoder. In FIG. 1, digital data to be recorded or transmitted via an input terminal 1 and an original code such as an address ID for code correction are input to an adder 2. Adder 2
Is supplied to the delay circuit 5 via the changeover switch 3, where it is delayed for a predetermined time.

The delay circuit 5 has, for example, a configuration in which two flip-flops are connected in cascade. Each delay circuit is delayed by one sampling period for a total of two sampling periods, and then fed back to the adder 2. The adder 2 outputs the delay signal from the delay circuit 5 and the input digital signal (original code) from the input terminal 1.
And the pre-coded original code (interleaved NRZI signal) is added to the terminal 3a of the changeover switch 3.
To enter.

On the other hand, a synchronization signal Sync is inputted from an input terminal 4 to a terminal 3b of the changeover switch 3. Synchronous signal S
“ync” is a fixed code indicating the head of the block. The changeover switch 3 alternately connects the terminals 3a and 3b, and combines the precoded original code and the non-precoded synchronization signal Sync in time series and outputs the synthesized signal to the output terminal 6. Note that the synchronization signal Sync may be precoded, but the result is the same.

[0006] As shown in FIG. 3, a digital signal output from an output terminal 6 includes a synchronizing signal (Sync) 8 and an ID 9.
And a time-series synthesized signal of the data 10 and this signal is recorded or transmitted. Here, data 10 is input terminal 1
Data such as image, sound, information, etc.
D is an address for code correction, and is usually numbered from 0 in ascending order. Also, a synchronization signal (Sync)
8, ID 9 and data 10 constitute one sync block.

Although there are various types of partial response systems, in any case, the digital signal pre-coded as described above is recorded on, for example, a magnetic recording medium. When reproducing the magnetic recording medium, reproduction equalization is performed on the reproduction signal to obtain a ternary equalized waveform, from which reproduction data is obtained.

[0008]

Since the ID to be pre-coded is generally an address numbered in ascending order from 0, for example, if 16 bits are assigned to the ID, the value of the first ID becomes 16 Bit all is "0". On the other hand, although the number of bits of the synchronization signal Sync varies depending on the system to which it is applied, in the case where the value of the last two bits is set to “00” in any case of the number of bits, the head ID is precoded. When the synchronization signal Sy
a total of 18 consisting of the last 2 bits of nc and 16 bits of ID
The bits are all "0".

However, in the above-mentioned conventional precoder,
If the delay circuit 5 has a configuration in which two flip-flops are connected in cascade, in the above case, the precoded output signal is at least 18 bits all "0",
This is not preferable for a transmission system in which it is difficult to transmit a very low frequency component or a direct current component because the rotary transformer performs electrical coupling with the rotary head. In addition, a code that does not invert for a long time is not preferable for a system that performs self-synchronization.

[0010] The present invention has been made in view of the above points,
Even when the same value continues for more than a predetermined number of bits in the input data, precoding is performed so that the same value does not continue for several bits or more (especially, the same value does not continue to important parts such as ID). It is an object of the present invention to provide a precoder for obtaining the same.

[0011]

In order to achieve the above-mentioned object, the present invention provides a method for sequentially inputting ID information and information data.
An inverter for converting the reverse logic value all, an adder for adding and outputting the outputs of the inverter and the delayed signal, summing
ID information and pre-code after pre-coding
Of the first time-series synthesized signal including the post-load information data
At the beginning, at least the last two bits have the same logical value
The set synchronization signal is synthesized in time series to form a second time series.
Combining means for outputting a combined signal; and
Delays the second time-series synthesized signal by two bits
And a delay circuit to be obtained .

[0012]

In the present invention, the ID to be recorded or transmitted
After converting the information and the information data into the inverse logic value by the inverter, the delay signal and the adder are added and pre-coded.
ID information and a precoded information data
A time-series synthesized signal is obtained, and a small number is added to the first time-series synthesized signal.
Synchronous with at least the last two bits set to the same logical value
A second time-series synthesized signal obtained by synthesizing the signals in a time-series
The delay signal is delayed by two bits by a delay circuit.
ID information output following the synchronization signal
Is the same as the last two bits of the synchronization signal.
Even if it is a logical value (first logical value), the first 2
The bit is the last two bits of the synchronization signal by the inverter.
The inverted logical value (the second logical value) is used as the synchronization signal by the adder.
(Exclusive OR operation) with the last two bits of
And the first two bits of the ID information after precoding are
Last 2 bits of sync signal and reverse logical value (second logical value)
It can be. Also, 3 bits from the beginning of the ID information
The second bit of the fourth bit and the fourth bit is contradicted by the inverter
After being converted to a logical value (second logical value)
The first two bits of the ID information are added by the adder.
Since they have the same logical value (second logical value),
2 bits of the beginning or al 3rd and 4th bits of the ID information after over de, first two opposite logical values of the bits of ID information after precoding, i.e., identical to the last two bits of the sync signal logic Value (a first logical value). Less than,
Similarly, even if the values of all bits of the ID information output following the synchronization signal have the same logical value as the last two bits of the synchronization signal, the ID information after precoding in which only two bits have the same value continues Can be obtained. This is because the adder outputs a first logical value when adding the same logical value, and outputs a second logical value when adding different logical values.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a precoder according to the present invention. 2, the same components as those in FIG. 2 are denoted by the same reference numerals. The embodiment of FIG. 1 is characterized in that an inverter 12 is provided between an input terminal 1 and an input terminal of an adder 2.

In FIG. 1, digital data to be recorded or transmitted via an input terminal 1 and an original code such as an address ID for code correction are converted into a reverse logic value (inverted polarity) by an inverter 12 and then added to an adder 2. Is input to The output signal of the adder 2 is supplied to the delay circuit 5 via the changeover switch 3, where it is delayed for a predetermined time.

The delay circuit 5 has, for example, a configuration in which two flip-flops are connected in cascade. Each delay is delayed by one sampling cycle for a total of two sampling cycles, and then fed back to the adder 2. The adder 2 adds the delayed signal from the delay circuit 5 and the input digital signal (original code) from the inverter 12 to input the precoded original code (interleaved NRZI signal) to the terminal 3a of the changeover switch 3. I do.

The changeover switch 3 alternately switches between a synchronizing signal Sync input from an input terminal 4 to a terminal 3b and a precoded original code from the adder 2 input to a terminal 3a. A code and a synchronizing signal Sync which is not precoded are synthesized in a time-series manner and output terminal 6
Output to

In this embodiment, the digital signal output from the output terminal 6 is a synchronizing signal (S) as shown in FIG.
ync) 8 is a time-series synthesized signal of ID 9 and data 10, and this signal is recorded or transmitted.

Here, when the value of the last two bits of the synchronization signal Sync is set to "00", and when the first ID of all 16 bits "0" is precoded, the last ID of the synchronization signal Sync is It is the same as in the prior art that a total of 18 bits consisting of 2 bits of ID and 16 bits of ID are all “0”, but in this embodiment, the leading value of the ID is set to 16 bits all “1” by the inverter 12. Since it is input to the adder 2 and subjected to an exclusive OR operation, the output terminal 6 outputs the last two-bit value “0” of the synchronization signal Sync.
Following “0”, the changeover switch 3 is switched to the terminal 3 a, so that the first two bits “00” of the ID are exclusive-ORed with the last two bits “00” of the synchronization signal from the delay circuit 5. Are output as “11”, and the next two bits are “00” by the exclusive OR operation of the output “11” of the two bits at this time and “11” of the third and fourth bits of the ID. Is output.

Thereafter, similarly to the above, "110"
A pre-coded 16-bit ID having a value of “0110011001100” is output.
It is assumed that the sampling period is delayed. Since the same 16-bit precoded value has only two consecutive identical values, the precoded signal can be easily transmitted even in a transmission system where transmission of extremely low frequency components and DC components is difficult. .

The portion of the data 10 in FIG. 3 is considered to be a random code, and even if the inverter 12 is provided, the effect of reducing the run length is small. However, shortening the run length only in the ID portion 9 as in the present embodiment has a great effect because the importance of the ID is high.

However, the effect of the provision of the inverter 12 is that the last two bits of the synchronization signal Sync are “0”.
This is effective for a system set to “0” or “11”, but the last two bits of the synchronization signal Sync are “0”.
When it is 1 "or" 10 ", the desired effect cannot be obtained, but there is no adverse effect, and no adverse effect is given.

In the digital signal recording / reproducing VTR, the value of the synchronizing signal Sync is, for example, "** 01 0010 1110 001" when detected on the reproducing side.
1 "(where * is either 0 or 1). For this reason, the values at the time of recording of the synchronization signal Sync that is pre-coded and recorded and detected with the above values are “0001 0111 0010 1001” and “1110 10
00 1101 0110 '', `` 0100 0010 0111 1100 '', `` 101
1 1101 1000 0011 ”, and any value may be recorded. In this case, the last 2
Since the bits have the same value, the desired effect of the present invention can be obtained. In the above-mentioned cases and the last two bits have different values, the desired effect of the present invention can be obtained. No, but no harm.

[0025]

As described above, according to the present invention,
After converting the ID information and the information data to be recorded or transmitted into an inverse logical value by an inverter, the delayed signal and the adder
Add and precode ID information and precoded
Obtaining a first time-series synthesized signal composed of information data;
At least the last two bits are the same
Synchronous signals set to one logical value are synthesized in time series
Delays the second time-series synthesized signal by two bits using a delay circuit.
Then, by using the above-mentioned delay signal,
The values of all bits of the ID information output by
Even if the logical value is the same as the latter two bits, only the two bits are the same.
It is possible to obtain ID information after precoding where one value is not continuous
Because of the very simple structure of adding an inverter, it is possible to easily transmit precoded signals even in transmission systems where transmission of extremely low frequency components and DC components is difficult.
In particular, an ID having a high importance can be reliably transmitted.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional example.

FIG. 3 is a diagram illustrating an example of a format of a precoded output signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data and ID input terminal 2 Adder 3 Changeover switch 4 Synchronous signal input terminal 5 Delay circuit 6 Output terminal of precoded signal 12 Inverter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/14 G11B 20/10 H03M 3/00-11/00 H03M 13/00-13/53 H04L 25 / 00-25/66

Claims (3)

(57) [Claims] 1. ID information and information data sequentially inputted
And an inverter that converts all of the above into inverse logical values, and outputs the sum of the output of the inverter and the delay signal.
An adder and the ID after precoding, taken out of the adder
First information comprising information and the information data after precoding.
At the beginning of the time-series synthesized signal, at least the last 2 bits
Synchronous signals whose values are set to the same logical value are synthesized in time series
To a second time synthesizing means for outputting a sequence synthesized signal, the second time series combined signal output from said synthesizing means
And a delay circuit that obtains the delay signal by delaying the second time-series synthesized signal by two bits.
A precoder characterized in that it is output for output . 2. The synthesizing means takes out from the adder.
One of the first time-series synthesized signal and the synchronization signal
2. The precoder according to claim 1, wherein the precoder is a changeover switch for selecting one of the two. 3. The synchronization signal and the ID after precoding.
The information comprising the information and the pre-coded information data.
When repeatedly recording or transmitting the time series composite signal of 2,
The ID information before the precoding is used for each time-series synthesized signal.
3. The method according to claim 1, wherein the values are set in ascending order.
The described precoder.