JP3313125B2 - CCD type solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a function to <br/> the CCD type imaging element, particularly easy and low can power drive, also a two-dimensional CCD type having a low power consumption and low noise output circuitry The present invention relates to an imaging device.

[0002]

2. Description of the Related Art Conventionally, a CCD solid-state imaging device has been widely used as a solid-state imaging device used in a home video camera or the like. Such a conventional CCD type solid-state imaging device has an element configuration called an inter-line type shown in FIG. 15, is driven under the driving conditions shown in Table 1, and is used in a camera system by the configuration shown in FIG. . In FIG. 15, 1 is a photodiode for performing photoelectric conversion, 2 and 3 are vertical CCDs and horizontal CCDs for transferring signal charges photoelectrically converted by the photodiodes, and 4 is an output gate for dividing a horizontal CCD 3 and an output circuit. -5 and 5 are horizontal CCD3
Reset transistors for resetting the floating diffusion layer to which the signal charges are sent from the horizontal CCD every transfer cycle of the horizontal CCD, respectively, a driver transistor, a load transistor, and a load transistor, which constitute a first stage source follower; These are a driver transistor and a load transistor that constitute the next stage source follower. The partition in the vertical CCD 2 indicates one transfer stage composed of one polysilicon electrode, and the partition in the horizontal CCD indicates one transfer stage composed of a first polysilicon layer and a second polysilicon electrode. Also, horizontal C
Under the second polysilicon electrode constituting the output gate with the CD3, boron ions are implanted to lower the channel voltage. The reset transistor 5 is a depletion type transistor similar to the one below the first layer polysilicon electrode constituting the horizontal CCD.
v1, v2, v3, and v4 are input terminals of four-phase pulses for driving the vertical CCD 2, and h1 and h2 are horizontal CCDs 3.
Og is an output gate DC bias voltage input terminal, RG is a reset pulse input terminal, rd is a reset voltage input terminal of a floating diffusion layer, and vg is a load transistor gate. -Input voltage input terminal, od is the power supply voltage input terminal of the output circuit, sub is the substrate voltage input terminal, well is the well voltage input terminal, vs
s is a well voltage input terminal of the protection circuit, and out is a signal output terminal.

The signal charge photoelectrically converted by the photodiode 1 is applied with a high voltage to the terminal v1 or v3 and is sent to the vertical CCD 2 in a lump. Then, the voltage levels of the medium voltage and the low voltage are applied to the terminals v1 to v4. Are applied and transferred to the horizontal CCD 3 line by line.
Two-phase pulses are applied to the terminals and are sequentially transferred in the horizontal CCD 3. A potential change due to the signal charge transferred from the horizontal CCD 3 to the floating diffusion layer is detected by a first-stage source follower comprising transistors 6 and 8, and a transistor 9
The signal is output to an out terminal by a next-stage source follower composed of 10. Next, a reset pulse is applied to the rg terminal, the reset transistor 5 becomes conductive, and the floating diffusion layer becomes r
It is applied to the d terminal and reset to the reset voltage. The above operation is repeated, and signals are sequentially output. Also, s
Normally, a predetermined DC voltage is applied to the ub terminal to discharge excess charges generated by the photodiode, and a high voltage is applied during scanning to realize an electronic shutter for improving dynamic resolution and preventing flicker. Is done. The CCD type solid-state imaging device having such a configuration and operation is generally driven under the driving conditions shown in Table 1. Table 1 shows an example of a pulse applied to each terminal shown in FIG. 15 and a DC bias voltage. Using the well terminal voltage as a reference voltage, v1
To v4 terminal, the lowest voltage is vertical CC to reduce dark current
A negative CCD scanning pulse of a negative value which is equal to or lower than a voltage at which a p-type inversion layer is formed on the surface of the Dn layer (hereinafter referred to as a pinning voltage) is applied. Is applied with a high voltage.
The output voltage of the timing generator shown in FIG. 16 is directly applied to the terminals h1 and h2. This is to prevent unnecessary power consumption due to the provision of the driver, and to reduce the power consumption of the camera system. Furthermore, horizontal CCD
In order to transfer the charge from the output diffusion layer to the output diffusion layer without delay, a voltage equal to the high voltage of the horizontal CCD transfer pulse applied to the h1 and h2 terminals is applied to the og terminal, and the channel below the output gate is applied to the rd terminal. A voltage sufficiently higher than the voltage is applied. The low voltage at the rg terminal is equal to the low voltage of the horizontal CCD transfer pulse in order to prevent leakage of signal charges from the floating diffusion layer, and the high voltage is sufficiently higher than the high voltage of the horizontal CCD transfer pulse to realize a sufficiently low on-resistance. Apply high voltage. The same voltage as that of the rd terminal is applied to the od terminal so as not to increase the number of voltage values. On the other hand, su
Since the DC voltage for discharging the excess charge applied to the terminal b varies from element to element, the DC voltage is adjusted for each element, and the high voltage for the electronic shutter pulse is set to the upper limit of the variation of the elements.

[0004]

[Table 1]

The above-mentioned CCD type solid-state image pickup device is used in a camera by the configuration shown in FIG. In the figure, reference numeral 161 denotes a CCD solid-state imaging device shown in FIG. 15; 162, a timing generator for driving the CCD solid-state imaging device 161; 163, a driver for setting a voltage value of each pulse to a predetermined value; 164, a correlated double sampling circuit for removing noise from the output of the CCD solid-state imaging device 161;
165 is an automatic gain control circuit for changing the voltage gain according to the signal output level, 166 is an A / D converter, 167 is a digital signal processing circuit, 168 is a D / A converter, and 169 is a camera battery-170 to a camera. This is a DC-DC converter that supplies a necessary voltage to each unit. Timing generator 162, correlated double sampling circuit 164 and automatic gain control circuit 165, digital signal processor 167, A / D
The converter 166 and the D / A converter 168 are each formed of a single-chip integrated circuit that operates on a single power supply. The CCD solid-state imaging device 161 generates a timing by the timing generator 162, and receives a pulse of a predetermined voltage value by the driver 163 supplied with the voltage by the DC-DC converter 169, and the pulse is supplied from the DC-DC converter 169. Driven by a DC voltage, the output signal from the element is subjected to noise removal and gain control by a correlated double sampling circuit 164 and an automatic gain control circuit 165, and then converted to a digital signal by an A / D converter 166, and is processed by a digital signal processor 167. Signal processing is performed, and the signal is again converted into an analog signal by the D / A converter 168 to become a TV signal. In addition, this type of CCD solid-state imaging device is described in, for example, Technical Report of the Institute of Television Engineers of Japan, Vol. 61-72 (198
9.2), Technical Report of the Institute of Television Engineers of Japan, 12, 13
No. pp. 31-36 (1988. 2), a digital signal processor for a camera using a CCD type solid-state image pickup device of this type is also referred to as IS.
She-she-digest of technical
Papers Pages 250 to 251 (1991)
(ISSCDIGEST OF TECHNICAL
PAPERS pp. 250-251 (1987))
Are discussed in

[0006]

The above prior art is based on CC
Driving of the D-type solid-state imaging device does not consider usability improvement and low power consumption, and the usability of the imaging device is poor.
It is difficult to reduce the power consumption of the camera. Further, there is a problem that it is difficult to reduce power consumption and noise of an output circuit in the image sensor. That is, first, as the peripheral circuits become more single-powered, the driving of the CCD type image pickup device shown in FIG. 15 requires a pulse having a multi-level voltage level shown in Table 1 and a DC voltage. The driver 163 that generates these and DC
-A DC converter 169 had to be provided in the camera system. This has made the CCD type image sensor difficult to handle. In addition, as camera adjustments are progressing due to digitization of signal processing circuits, su
The fact that the DC voltage for discharging the excess charge applied to the terminal b must be adjusted for each element has also been another factor that makes the CCD type imaging element difficult to handle. Second, with the aim of reducing the power consumption of the camera, the power supply voltage of the timing generator 162 and the signal processing device 167 is set to the current 5V.
To 3.3V, and further to 1.5V. However, it is difficult to lower the drive voltage of the horizontal CCD 3 that requires high-speed transfer. Therefore, the output voltage of the timing generator 162 is applied to the h1 and h2 terminals to apply the horizontal C
It became difficult to drive the CD3, and it was necessary to provide a driver for driving the horizontal CCD in the camera system. When the driver section is provided outside the image sensor as described above, reactive power for driving a parasitic capacitance such as a wiring capacitance between the driver and the image sensor or a pin capacitance of the image sensor is generated, which is one of the causes of reducing the power consumption of the camera. Had become. further,
The power of the DC-DC converter 169 that generates the multi-level voltage described above cannot be reduced, which has been another factor in reducing the power consumption of the camera. Third, the output voltage of the timing generator 162 from 0 to 5 V is represented by h1, h
Applied to the two terminals to drive the horizontal CCD 3,
The channel voltage of the horizontal CCD is high, and the rd terminal voltage is high. As a result, the od terminal voltage, which is the power supply voltage of the output circuit set to the same voltage as the rd terminal, also increases, and the power consumption generated in the output circuit increases. further,
Since the power supply voltage is high, it is difficult to use a transistor with a short channel length, and there has been a problem that noise is large. Accordingly, a first object of the present invention is to drive to provide an easy user-friendly CCD solid-state imaging element. A second object of the present invention is to reduce power consumption of the camera to provide a CCD type imaging element as possible. Furthermore, another object of the present invention lowers the power supply voltage of the output circuit to provide an output circuitry of the CCD type solid state imaging device with low power consumption and low noise.

[0007]

To achieve the above first and second objects, a CCD type solid-state image pickup device according to the present invention comprises, as shown in FIG. With pulse and two positive and negative power supplies, vertical CC
D, a horizontal CCD, a reset transistor, and at least a voltage generation circuit (11 to 17) for driving an output circuit with a predetermined pulse voltage and a DC voltage by input of a trigger pulse. Alternatively, the positive and negative two power supplies have a positive power supply value (VDD) equal to the power supply voltage value of the output circuit and a negative power supply value (Vss) equal to the lowest voltage value of the transfer pulse of the vertical CCD. I do. Alternatively or additionally, the voltage generation circuit includes a first conductivity type MOS transistor formed in the same manner as the first conductivity type MOS transistor of the output circuit, and a second conductivity type second MOS transistor on the surface of the photoelectric conversion element. MO of the second conductivity type forming the source / drain diffusion layer together with the formation of the impurity layer
A complementary MOS transistor configuration in which S transistors are connected to each other is provided. Here, the voltage generation circuit has a configuration of a complementary MOS transistor, and the voltage generation circuit has a first power supply between the positive power supply and the ground power supply, or between the ground power supply and the negative power supply, or between the positive power supply and the negative power supply.
And a second complementary MOS transistor, wherein the gates of the respective complementary MOS transistors are connected to each other as an input point, and the connection point between the source and drain of each complementary MOS transistor is defined as an output point. Input a trigger pulse to the input point of the complementary MOS transistor of
The output and input points of the first and second complementary MOS transistors are connected to each other, and the output point of the second complementary MOS transistor is used as the output point of these circuits. This is preferable for reducing the power of the voltage generation circuit. Here, in order to generate a negative output pulse in the above-mentioned pulse generation circuit by a positive input trigger pulse,
In the case of a pulse generating circuit supplied with negative power, the input point of the pulse generating circuit may be connected to an external pulse terminal via a capacitor and to a negative power terminal via a clamp diode. Vertical CC as the voltage generation circuit
In the case of the D transfer pulse generation circuit, for example, as shown in FIG. 3, the pulse generation circuit is provided between the ground power supply and the negative power supply, and the output pulse of the negative power supply value is generated by input of a trigger pulse. The output pulse may be applied to the vertical CCD. Alternatively, for a vertical CCD ternary pulse generating circuit that applies a ternary pulse of the negative power supply value, the positive power supply value, and the low voltage value to the vertical CCD, for example, as shown in FIG. A vertical CCD transfer pulse generating circuit which has the above-described pulse generating circuit between a positive power supply and a ground power supply and generates an output pulse of the negative power supply value in response to a trigger pulse input, and generates an output pulse of the positive power supply value A vertical CCD read pulse generating circuit may be provided, and a switch circuit for switching the output of both circuits may be provided to apply the output to the vertical CCD.

As a voltage generating circuit for achieving the second and third objects, a horizontal CCD transfer pulse generating circuit applied to a horizontal CCD, for example, as shown in FIG.
In addition to the above-described pulse generating circuit between the ground power supply and the negative power supply, the output of the circuit has a voltage amplitude limiting means for generating a negative voltage pulse whose voltage amplitude is limited from the negative power supply value pulse by input of a trigger pulse. To be applied to the horizontal CCD. For a reset pulse generation circuit that applies a pulse voltage to the gate of a reset transistor,
For example, as shown in FIG. 6, the above-described pulse generation circuit is provided between the positive power supply and the ground power supply, and a trigger pulse is input to amplify the voltage to generate a pulse voltage, which is applied to the gate. What should I do? In order to achieve the third object by lowering the output voltage, the reset voltage generating circuit includes, for example, as shown in FIG. 7, the above-described pulse generating circuit between the positive power supply and the ground power supply, and boosts the pulse voltage. Means for applying a boost pulse to the drain of the reset transistor upon input of a trigger pulse.

Here, as means for boosting the pulse voltage, one terminal of a capacitor is connected to the output point of the pulse generating circuit between the positive power supply and the ground power supply, and the other terminal of the capacitor is connected to the positive terminal. What is necessary is just to provide a structure in which the diode is connected to the power supply and the other terminal and the output terminal are diode-connected.

In order to achieve the first object, a substrate voltage generating circuit for applying a voltage to a substrate for discharging excess voltage includes the above-described pulse generating circuit between a positive power supply and a negative power supply. Having a DC power supply for the substrate, connecting a capacitor between the output point of the pulse generation circuit and the substrate,
In addition, the configuration may be such that the substrate and the DC power supply for the substrate are connected via a switch including a depletion transistor. The voltage drop can be reduced by using the depletion transistor, and a high voltage can be applied to the substrate at high speed by capacitively coupling between the output point of the pulse generation circuit and the substrate. Here, as the DC power supply for the substrate, for example, a positive power supply is used as it is as shown in FIG. 9, or a circuit that generates a DC voltage to be applied to the substrate by receiving the supply of the positive power supply as shown in FIG. And means for adjusting the DC voltage, and the adjusted DC voltage may be used as an output applied to the substrate. In this case, as a circuit for generating a DC voltage applied to the substrate, a DC voltage to be applied to the substrate is generated by stepping down a voltage obtained by boosting the positive power supply voltage, and a means for adjusting the DC voltage includes a voltage. If the step-down voltage is adjusted based on the voltage of the bias voltage generating circuit provided with the adjusting means, the substrate voltage can be adjusted inside the element, and the usability is improved. As shown in FIG. 10, for example, as shown in FIG. 10, a vertical CCD ternary pulse generating circuit for applying a read voltage equal to or higher than the positive power supply voltage to the vertical CCD has a first and a second power supply between the positive power supply and the ground power supply. And a third and fourth complementary MOs having the same configuration as the pulse generating circuit.
An S transistor is added between the positive power supply and the ground power supply, and an input point connecting the gates of the third complementary transistor is connected to an output point of the second complementary MOS transistor. What is necessary is just to add a configuration in which the output point connecting the source and the drain of the complementary MOS transistor is connected to the vertical CCD via a capacitor.

An output circuit for achieving the third object has a multistage amplifier configuration.
It is assumed that the substrate impurity concentration of the driver transistors in the next and subsequent stages is lower than the substrate impurity concentration of the first stage driver transistor.

In the CCD solid-state imaging device according to the present invention for achieving the first and second objects, the device which operates by receiving a single trigger pulse and two positive and negative power supplies from the outside is: For example, as shown in FIG. 14, a timing generator for generating a plurality of trigger pulses at desired timing from the basic clock using the single external trigger pulse as a basic clock, and driving a built-in voltage generating circuit by the trigger pulse. Built-in. Then, the built-in timing generator may provide a trigger pulse to the above-described voltage generation circuit.

[0013]

According to the present invention, a trigger pulse from the outside and positive and negative 2
If a voltage generating circuit for generating a pulse of a predetermined voltage level or a predetermined DC voltage after receiving power supply is incorporated in the CCD type imaging device, power supplies of various voltage levels have conventionally been required as an external power supply. However, the number of types of power supplies can be reduced. In this case, the present invention focuses on the following points regarding the two power supply values and the formation of the built-in circuit. That is, the power supply voltage of the output circuit has the highest positive voltage value among the power supply voltages that require a large current driving capability for driving the CCD image sensor,
The lowest voltage of the transfer pulse of the vertical CCD has the lowest negative voltage value. Since the booster circuit of an integrated circuit usually has a small current driving capability, by setting such a highest positive voltage value or the lowest negative voltage value as a positive or negative power supply value and by obtaining a trigger pulse from the outside, A pulse of a predetermined voltage and a DC voltage for driving the CCD can be generated with low power consumption. Further, in order to reduce power consumption as a built-in integrated circuit, it is desirable to form a circuit with complementary MOS transistors.
A first conductivity type MOS transistor of the complementary MOS transistor is formed along with the formation of the S transistor, and a second conductivity type second transistor of the complementary MOS transistor is formed along with formation of a second impurity type second impurity layer on the surface of the photoelectric conversion element. M
By forming the source / drain diffusion layer of the OS transistor, the complementary MOS transistor can be formed without changing the manufacturing process for forming the CCD type imaging device. By adopting such a power supply value and circuit formation based on the viewpoint, a low power consumption voltage generating circuit that drives a vertical CCD, a horizontal CCD, a reset transistor, and an output circuit with a predetermined pulse voltage and a DC voltage is used as a CCD solid-state imaging device. It is possible to easily incorporate the device by forming it together with the element. As described above, according to the present invention, it is not necessary to provide a conventionally required driver 163 as shown in FIG. 16 outside the element, and the DC-DC converter 169 is provided with two positive and negative signals.
Only the voltage needs to be supplied to the image sensor. As a result, usability of the CCD solid-state imaging device is improved. In addition, since the number of voltage values supplied by the DC-DC converter is reduced, the power consumption of the camera can be reduced.

Further, a circuit for generating a DC voltage applied to the substrate by an external power supply is provided in the CCD image pickup device, and a means for adjusting the DC voltage is provided. No adjustment is required when creating the system. As a result, usability of the CCD solid-state imaging device is improved. The horizontal CCD transfer pulse generation circuit generates a pulse of a predetermined voltage level by using a pulse from the timing generator as a trigger, as shown by h1 and h1 in FIG.
Apply to terminal h2. As a result, even if the power supply voltage of the timing generator drops, it is not necessary to provide a driver outside the element. Therefore, there is no generation of reactive power in the driver, the power supply voltage of the timing generator 162 and the signal processing device 167 in FIG. 16 can be reduced, and the power consumption of the camera can be reduced. Alternatively, by making at least the low voltage of the horizontal buffer circuit negative, the channel voltage below the horizontal CCD becomes low, and the rd terminal voltage in FIG. 15 can be lowered. Further, by generating the rd terminal voltage from the od terminal voltage by the booster circuit, the od terminal voltage can be lowered further without increasing the number of power supplies supplied from outside the device. Usually, in order for the first stage driver transistor to perform a saturation operation and the output circuit to operate in a linear range, the od terminal voltage needs to be higher than a value obtained by subtracting the threshold voltage of the first stage driver transistor from the rd terminal voltage. Therefore, the threshold voltage of the first-stage driver transistor may be set to a high value in order to lower the odd terminal voltage. However, in the case where the next-stage driver has the same structure as the first-stage driver as described in FIG. 15, if the threshold voltage of the transistor is too high, the next-stage driver transistor does not conduct sufficiently and the operation of the next stage becomes difficult. Become. Therefore, in the present invention, the substrate impurity concentration of the driver transistor of the subsequent stage is made lower than the substrate impurity concentration of the driver transistor of the first stage, the threshold voltage of the first stage driver transistor is increased, and the od terminal voltage is reduced. The threshold voltage of the transistor was lowered so that the next stage operates in the linear operation range. As a result, the voltage of the od terminal, which is the power source of the output circuit, can be reduced, and power consumption can be reduced. In addition, a reduction in the power supply voltage enables the use of a short-channel transistor, thereby reducing noise.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is an overall configuration diagram of the first embodiment, FIG. 2A is a cross-sectional view taken along the line AA ′ of FIG. 1 of the first embodiment, and FIG.
FIG. 3C is a sectional view of a portion corresponding to a P-channel transistor, FIG. 3 is a vertical CCD transfer pulse generating circuit of the first embodiment, and FIG. 4 is a sectional view of the first embodiment. Vertical CCD ternary pulse generation circuit, FIG. 5 is a horizontal CCD transfer pulse generation circuit of the first embodiment, FIG. 6 is a reset pulse generation circuit of the first embodiment, FIG. 7 is a reset drain voltage generation of the first embodiment 8 is a circuit for generating a bias voltage of a load transistor of the output circuit according to the first embodiment, and FIG.
11 is a substrate voltage generation circuit according to the embodiment.

In FIG. 1, 1 to 10 are the same as in FIG. However, the reset transistor 5 is a depletion-type transistor which is ion-implanted in the same manner as under the second-layer polysilicon electrode constituting the horizontal CCD.
Reference numeral 11 denotes a substrate voltage generation circuit shown in FIG. 9, 12 denotes a vertical CCD transfer pulse generation circuit shown in FIG. 3, 13 denotes a vertical CCD ternary pulse generation circuit shown in FIG. 4, and 14 denotes a horizontal CC shown in FIG.
D transfer pulse generation circuit, 15 is a reset pulse generation circuit shown in FIG. 6, 16 is a reset voltage generation path shown in FIG.
Reference numeral 7 denotes a bias voltage generation circuit for the output circuit load transistor shown in FIG. V1, V2, V3, V4 are vertical CC
D2 transfer pulse trigger-input terminal, V1R, V3R
Is a trigger-input terminal for a read pulse of the vertical CCD 2;
H1 and H2 are transfer pulse trigger input terminals of the horizontal CCD 3, RG is a reset pulse trigger input terminal, SU
B is an electronic shutter pulse trigger input terminal, WEL
L is a well voltage input terminal, VDD is a positive power supply voltage input terminal, Vss is a negative power supply voltage input terminal, and OUT is a signal output terminal. A trigger pulse of the timing generator, a pulse having a predetermined voltage from two power supplies, positive and negative, and a DC voltage are generated inside the element, and the same operation as described in FIG. 15 is performed.

Generally, a booster circuit used in an integrated circuit has a low current driving capability. Therefore, the positive power supply needs to be higher than the highest voltage that requires a large current driving capability, and the negative power supply needs to be lower than the lowest voltage that requires a large current driving capability. In the case of a two-dimensional CCD image pickup device, a large current driving capability is required for the high and low voltages of the transfer pulses of the vertical CCD 2 and the horizontal CCD 3 and the power supply voltage of the output circuit. As a result, the positive power supply voltage value may be higher than the power supply voltage value of the output circuit. In the present embodiment, the positive power supply value was set equal to the power supply voltage value of the output circuit in order to prevent unnecessary power consumption since a through current always flows through the power supply of the output circuit. The negative power supply value may be lower than the lowest voltage value of the transfer pulse of the vertical CCD. In this embodiment, the negative power supply value is set equal to the minimum voltage value of the transfer pulse of the vertical CCD so that an unnecessary step-down device may not be provided. That is, in the present embodiment, the positive power supply value is equal to the power supply voltage value of the output circuit, and the negative power supply value is equal to the lowest voltage value of the transfer pulse of the vertical CCD. It is possible to easily generate a pulse having a predetermined voltage and a DC voltage from the two power supplies inside the element. In order to reduce power consumption in the built-in circuits 11 to 17, it is desirable to configure the circuit with complementary MOS transistors. In the present embodiment, such a complementary transistor is realized without any change in a manufacturing process for forming a CCD image sensor. This point will be described with reference to FIG. FIG. 1A is a cross-sectional view of a portion corresponding to the AA 'part of FIG. In the figure, 20 is an n-type substrate, 21 is a p-type well, 22
Denotes a p-type double well for preventing unnecessary charges such as smear charges from entering the CCD n layer 23; 24, a polysilicon electrode of the CCD; 25, a low voltage for discharging excess charges from the photodiode n layer 26 to the substrate. The reference numeral 27 denotes a p + layer provided on the surface of the photodiode for suppressing dark current, and 28 denotes a second layer aluminum for light shielding. FIG. 2B is a cross-sectional view of the n-channel transistor taken along the line BB ′ in FIG. In the figure, 20, 21, 2
Reference numerals 2 and 24 are the same as those in FIG.
Layer 30 is an n-type source drain diffusion layer of the n-channel MOS transistor. An n-channel MOS transistor for realizing the built-in circuits 11 to 17 has a structure similar to that shown in FIG. FIG. 4C shows a newly provided p-channel MOS for realizing the built-in circuits 11 to 17.
1 shows a cross-sectional structure diagram of a transistor. 20, 24, 25,
27 is the same as FIG. (A), and 29 is the same as FIG. (B). The contact between the p + layer 27 and the wiring layer 29 is performed simultaneously with the contact between the p-type well 21 and the wiring layer 29 in the conventional example. In this embodiment, the source drain diffusion layer of the p-channel transistor is also used as the p + layer provided on the surface of the photodiode, thereby complementing the manufacturing process for forming the CCD type imaging device without any change. Type transistor. If the threshold voltage of the p-channel transistor is to be lowered, n
The mold well 25 need not be provided below the p-channel transistor. Alternatively, ion implantation of boron, which is typically made of boron for adjusting a channel voltage, which is implanted below the second-layer polysilicon electrode of the horizontal CCD, may be implanted below the polysilicon electrode 24. Conversely, if it is desired to increase the threshold voltage, the photodiode n layer 26 may be provided below the transistor. Further, when it is desired to reduce the threshold voltage of the n-channel transistor, the p-type double well 22 need not be provided below the n-channel transistor. In addition, p of this embodiment
When a channel transistor is used, the voltage applied to the n-type substrate is higher than the positive power supply so that the source drain diffusion layer 27 is not biased forward with respect to the n-type substrate 20.

(1) Vertical CCD transfer pulse generation circuit In order to generate a transfer pulse of a vertical CCD having a low negative voltage by a positive external trigger pulse, it is necessary to perform a level shift and amplify the voltage. FIG. 3 shows a vertical CCD transfer pulse generation circuit according to the first embodiment. In the figure, 31 is a coupling capacitance, 32 is a clamp diode, 33 is an n-channel MOS transistor constituting a first inverting circuit, 34
Is a p-channel MOS transistor forming a first inverting circuit, and 35 is an n-channel MOS transistor forming a second inverting circuit.
The S transistor 36 is a p-channel MOS transistor constituting a second inverting circuit. An external positive pulse is transmitted by a diode 32 to the input point A clamped to the negative power supply Vss via the coupling capacitor 31 with a voltage shift. Next, after the voltage is amplified by the first inverting circuit, the current is amplified by the second inverting circuit to be a vertical CCD transfer pulse. Since the voltage amplitude of the external pulse is smaller than the voltage amplitude of the vertical CCD transfer pulse, a through current flows through the first inversion circuit when the voltage of the external pulse is high. In order to reduce the through current and reduce the power consumption, the current driving capability of the first inverting circuit must be reduced, and a large capacity vertical CC is required.
D electrode cannot be driven. Therefore, in the present embodiment, a second inverting circuit is provided so that the first inverting circuit does not need to have a high current driving capability. That is, according to the present embodiment, the input point is coupled to the external pulse by the capacitance, and
Level shift and voltage amplification are performed by providing a first inverting circuit clamped to a negative power supply, and a vertical CCD transfer with low power consumption is provided by providing a second inverting circuit that receives the output of the first inverting circuit as an input. A pulse generator has been realized.
Note that the diode 32 can be easily realized by providing an n-type diffusion layer in the p-type well 21 of FIG. further,
The clamping may be performed by a diode-connected MOS transistor.

(2) Vertical CCD tri-level pulse generation circuit In this embodiment, a negative power supply circuit for generating a vertical CCD transfer pulse and a positive power supply circuit for generating a readout pulse are provided, and the outputs of these two circuits are switched by switches. A vertical CCD ternary pulse is generated. FIG. 4 shows a vertical CCD ternary pulse generating circuit according to the first embodiment. In the figure, 4
1 is a coupling capacity, 42 is a clamp diode, 43, 37
Are n-channel MOS transistors forming a first inverting circuit, 44 and 38 are p-channel MOS transistors forming a first inverting circuit, 45 and 39 are n-channel MOS transistors forming a second inverting circuit, Numeral 40 denotes a p-channel MOS transistor constituting a second inverting circuit, and a circuit composed of 41 to 46 or a circuit composed of 37 to 40 is the same as that of FIG. 47 is a vertical CCD transfer pulse generating circuit and a vertical CCD.
An n-channel MOS transistor 48 serving as a switch between the electrodes, and a p-channel MOS transistor 48 serving as a switch between the read pulse generating circuit and the vertical CCD electrodes. The well of the n-channel MOS transistor 47 is connected to the output of the second inverting circuit to prevent an increase in threshold voltage due to the body effect. Generates a negative vertical transfer pulse
The generated transfer pulse generation circuit is installed between the negative power supply and the ground power supply.
MOS transistor constituting the transfer pulse generation circuit
The voltage between the terminals of the stars 43 to 46 is equal to or lower than Vss.
A read pulse for generating a positive read pulse
The generator is provided between the positive power supply and the ground power supply,
From the MOS transistor 37 constituting the pulse generation circuit
The voltage between the terminals 40 becomes VDD or less. Vertical CCD2
When a low voltage is applied to the input terminals V1R and V3R, the voltage of the node B is VD.
The voltage of D and node C is 0V. As a result, n
The channel MOS transistor 47 is turned on, and the transfer pulse of the vertical CCD is applied to the node D connected to the vertical CCD electrode. On the other hand, since 0 V or the negative power supply voltage Vss is applied to the source drain of the p-channel MOS transistor 48 which is grounded, no conduction occurs. Then, trigger when the transfer pulse becomes 0V.
When a high voltage is applied to the input terminals V1R and V3R, the node B
Becomes 0 V, and the n-channel MOS transistor 47 is turned off. On the other hand, node C becomes VDD and p channel M
The OS transistor 48 conducts, and VDD is applied to the node D connected to the vertical CCD electrode. That is, the node
B voltage becomes VDD and n-channel MOS transistor
When 47 is conducting, a transfer pulse from 0 to Vss
The voltage applied to node D connected to the vertical CCD electrode is
The voltage of the node C which is the output of the output pulse generation circuit is 0 V
It has become. As a result, the p-channel MOS transistor
The source-drain voltage of the transistor 48 is Vss at the maximum.
You. Further, the node C becomes VDD and the p-channel MOS transistor
The transistor 48 is turned on and connected to the vertical CCD electrode.
When VDD is applied to the node D, the vertical CCD transfer
The output of the negative power supply circuit that generates the looseness is 0V.
As a result, the source of n-channel MOS transistor 47
-The drain-to-drain voltage is at most VDD. As described above, according to the present embodiment, the negative power supply circuit for generating the vertical CCD transfer pulse and the positive power supply circuit for generating the readout pulse are provided for the vertical CCD ternary pulse, and the outputs of these two circuits are switched by the switch. As a result, the source-drain voltage of each MOS transistor is set to VDD or Vs
A ternary pulse can be generated with a low value of s. The MOS transistor 47 is an n-channel MOS transistor.
The S transistor 48 is constituted by a p-channel, and each MOS transistor
The gate voltage when the transistor is off is set to the ground voltage
Accordingly, the following operation and effect can be obtained. That is, the node
B voltage becomes VDD and n-channel MOS transistor
When 47 is conducting, a transfer pulse from 0 to Vss
The voltage is applied to a node D connected to the vertical CCD electrode. This
, The output of the node C, which is the output of the read pulse generation circuit,
The voltage is 0V. As a result, 0V is applied to the gate.
In addition, the p-channel MOS transistor 48
Can be made nonconductive, and its gate-source voltage
Is 0V and the gate-drain voltage is Vss at the maximum.
Wear. Also, the node which is the output of the read pulse generation circuit
The voltage of the gate C becomes VDD and the p-channel MOS transistor
When the data 48 is turned on, the node connected to the vertical CCD electrode is turned off.
VDD is applied to the node D. At this time, the vertical CCD transfer path
The output of the negative power supply circuit that generates the looseness is 0V.
As a result, by setting the gate voltage to 0 V, the n-ch
It is possible to make the channel MOS transistor 47 non-conductive.
The gate-source voltage is 0V and the gate-drain
The inter-electrode voltage can be at most VDD. But
The gate of each switch MOS transistor when off
Set the drain-to-drain voltage and the gate-to-source voltage to VDD or
Is to generate a ternary pulse with a low value as Vss
Can be.

(3) Horizontal CCD transfer pulse generation circuit The horizontal CCD transfer pulse of this embodiment has a negative minimum voltage in order to lower the reset voltage of the output circuit and the power supply voltage. Further, the minimum voltage is set to a value higher than the pinning voltage below the second-layer polysilicon electrode of the horizontal CCD which has been ion-implanted to lower the channel voltage so as not to generate an invalid voltage region. As a result, the horizontal CCD
The transfer pulse minimum voltage has a negative value higher than the minimum voltage of the vertical CCD transfer pulse. On the other hand, the voltage amplitude is usually smaller than the vertical CCD transfer pulse to reduce power consumption. Therefore, in this embodiment, the transfer pulse of the horizontal CCD is generated by limiting the voltage amplitude of the negative power supply circuit after level shifting a positive trigger pulse from the outside. FIG. 5 shows the first
5 shows a horizontal CCD transfer pulse generation circuit according to the embodiment. In the figure, 51 is a coupling capacitance, 52 is a clamp diode, 53
Is an n-channel MOS transistor constituting the first inverting circuit, and 54 is a p-channel MOS transistor constituting the first inverting circuit.
S transistor, 55 is an n-channel MOS transistor forming a second inverting circuit, 56 is a p-channel MOS transistor forming a second inverting circuit, 51 to 56
Is a circuit similar to that of FIG. Also, 5
7 is a p-channel MO for limiting the negative voltage of the pulse.
S transistors 58 and 59 are p-channel MOS transistors for applying a bias voltage to the gate of the p-channel MOS transistor 57, and 60, 61 and 62 are n-channel MOS transistors constituting a bias voltage generating circuit. The n-channel MOS transistors 60, 61,
Wells 62 are connected to the respective sources, and the threshold voltage of each transistor is equal. The pulse generated by the trigger pulse applied to the H1 and H2 terminals is
The negative voltage is limited by the p-channel MOS transistor 57 and becomes a horizontal CCD transfer pulse. When the output of the second inverting circuit is 0 V, the node E is higher than the bias voltage of the bias voltage generating circuit by the threshold voltage of the p-channel MOS transistor 59. When the output of the second inverting circuit becomes Vss, the voltage of the node E decreases due to the capacitive coupling between the drain of the transistor 57 or the source and the gate. Thereafter, when the voltage of the node E falls below a certain voltage, the transistor 58 is turned on, and the node E is clamped to a value lower than the bias voltage of the bias voltage generating circuit by the threshold voltage of the p-channel MOS transistor 58. .
As a result, the output of the second inverting circuit is higher than the node E by the threshold voltage of the p-channel MOS transistor 57,
That is, the value is limited to a value equal to the bias voltage of the bias voltage generation circuit. According to the present embodiment, the transfer pulse of the horizontal CCD can be generated by limiting the voltage amplitude of the negative power supply circuit after level shifting the external positive trigger pulse.

In order to limit the high voltage of the pulse, transistors 57 to 59 may be n-channel MOS transistors and a desired bias voltage may be applied. In addition, a voltage limiter may be applied to the power supply voltage in order to limit the voltage of the pulse.

(4) Reset pulse generation circuit In this embodiment, the DC bias voltage of the output gate is set to 0 V which is the high voltage of the horizontal CCD transfer pulse. The reset transistor 5 is a depletion type transistor similar to that under the second-layer polysilicon electrode constituting the output gate. As a result, in order to prevent signal charges from leaking from the floating diffusion layer, the low voltage of the reset pulse may be 0 V or less. Therefore, in the present embodiment, a reset pulse is generated by a circuit that uses two power supplies of positive power and 0 V. FIG. 6 shows a reset pulse generation circuit according to the first embodiment. In the figure, 63 is an n-channel MOS transistor forming a first inversion circuit, 64 is a p-channel MOS transistor forming a first inversion circuit, 65 is an n-channel MOS transistor forming a second inversion circuit, and 66 is P-channel MOS forming second inverting circuit
The circuit composed of transistors 63 to 66 is shown in FIG.
Is a circuit similar to. According to this embodiment, the reset pulse can be generated by voltage-amplifying a positive trigger pulse from the outside.

(5) Reset voltage generation circuit In this embodiment, in order to reduce the power supply voltage of the output circuit, the reset voltage is separated from the power supply voltage of the output circuit, and the reset voltage is generated by boosting the power supply voltage of the output circuit.

FIG. 7 shows a reset voltage generating circuit according to the first embodiment. In the figure, 63 to 66 are the same as in FIG.
Reference numeral 1 denotes a charge pump capacitor; and 72 and 73, diode-connected n-channel MOS transistors. In addition,
The well of n-channel MOS transistor 72 has power supply VD
D to prevent an increase in threshold voltage due to the substrate effect. Due to the charge pump by the trigger pulse, the reset voltage is about twice the DC voltage lower than the positive power supply voltage VDD by the threshold voltage of the n-channel MOS transistor. According to the present embodiment, the reset voltage is generated by boosting the reset voltage from the power supply voltage of the output circuit, so that the power supply voltage of the output circuit can be made lower than the reset voltage without increasing the number of power supplies supplied from outside. it can. When an n-channel MOS transistor having a low threshold voltage is required to obtain a high reset voltage, a transistor having the structure shown in FIG. 2B and having no double p-well may be used.

(6) Load Transistor Bias Voltage Generation Circuit FIG. 8 shows a load transistor bias voltage generation circuit.
In the figure, 81, 82 and 83 are n-channel MOS transistors constituting a bias voltage generating circuit. The wells of the n-channel MOS transistors 81, 82 and 83 are connected to their respective sources, and the threshold voltages of the transistors are equal. The power supply voltage is divided into one third by a diode-connected transistor to become a load bias voltage. It is needless to say that the bias voltage can be freely set as required. (7) Substrate Voltage Generating Circuit It is necessary to apply a DC voltage for discharging excess voltage to the n-type substrate 20 at all times, and to apply a high positive voltage during the operation of the electronic shutter. In this embodiment, this high voltage is applied to an external trigger.
Pulses amplified by the voltage are applied to the substrate by capacitive coupling to generate the pulses. FIG. 9 shows a substrate voltage generating circuit according to the first embodiment. In the figure, 91 is a coupling capacitance, 92 is a clamp diode, 93 is an n-channel MOS transistor constituting a first inverting circuit, 94 is a p-channel MOS transistor constituting a first inverting circuit, and 95 is a second inverting circuit. An n-channel MOS transistor constituting the inverting circuit, 96 is a p-channel MOS transistor constituting the second inverting circuit, and a circuit composed of 91 to 96 is a circuit similar to FIG. Reference numeral 97 denotes a coupling capacitance between the second inverting circuit and the substrate, 99 denotes a substrate capacitance, and 98 denotes a switch between the DC voltage VDD applied to the substrate and the substrate. The switch 9
Numeral 8 is an n-channel depletion MOS transistor similar to that constituting the CCD. When the voltage applied to the SUB terminal is low, the voltage of the node F becomes VDD, the switch 98 is turned on, and the substrate voltage becomes VDD.
On the other hand, the node G is at Vss. When the voltage applied to the SUB terminal increases, first, the node F becomes Vss, and the switch 98 is closed. Thereafter, the node G becomes Vss.
To VDD, and the substrate voltage increases by a value obtained by dividing the voltage of (VDD−Vss) by the capacitance 97 and the substrate capacitance 99. In this embodiment, as described above, a high voltage can be applied to the substrate at a high speed by boosting by capacitive coupling. Further, by using an n-channel depletion MOS transistor constituting a CCD as a switch, it is possible to apply VDD to the substrate without voltage drop and to increase the voltage. When it is desired to increase the coupling capacitance in order to increase the amplitude of the shutter pulse, the coupling capacitance may be provided outside the element. When it is not necessary to increase the amplitude of the shutter pulse, the low-voltage power supply V
ss may be set to 0V. Further, when a high voltage applied between the gate and drain when the switch 98 is turned off becomes a problem, a voltage limiter similar to that described with reference to FIG. As a result, the gate of the switch 98 is
The low voltage applied to the gate can be the minimum voltage at which the switch becomes non-conductive when the source voltage is VDD, and the gate-drain voltage can be reduced.

According to the above-described embodiment, the two-dimensional CCD can be driven by a single-level external pulse and two positive and negative power supplies, is easy to use, and can reduce the power consumption of the camera.
Type solid-state imaging device can be provided. In addition, the power supply voltage of the output circuit can be reduced by incorporating a circuit for generating a negative horizontal CCD drive pulse from an external pulse and a booster circuit for generating a reset voltage from the power supply voltage of the output circuit, thereby reducing power consumption and noise. Output circuit can be realized.

Second Embodiment In the vertical CCD ternary pulse generating circuit of the first embodiment, the voltage of the read pulse is VDD and the voltage value may be insufficient. In this embodiment, a read voltage higher than the positive power supply voltage is realized by applying the positive power supply voltage VDD to the drive electrode of the vertical CCD and then boosting the voltage by capacitive coupling. FIG. 10 shows a vertical CCD ternary pulse generating circuit according to the second embodiment. In the figure, 41 to 47, 48, 37 to 40
Is similar to FIG. 104, an n-channel MOS transistor forming a third inverting circuit; 105, a p-channel MOS transistor forming a third inverting circuit;
Is an n-channel MOS transistor forming a fourth inverting circuit, and 107 is a p-channel MOS transistor forming a fourth inverting circuit.
An OS transistor 103 is a diode-connected n-channel MOS transistor for boosting, and 102 is a gate-grounded p-channel MO for transmitting a boosting pulse.
S transistor, 101 is a fourth inversion circuit and a vertical CCD
This is the coupling capacity with the electrode. When a low voltage is applied to the trigger input terminals V1R and V3R of the readout pulse of the vertical CCD, the voltage of the node B is VDD and the voltages of the nodes C and I are 0V. As a result, the n-channel MOS transistor 47 is turned on, and the transfer pulse of the vertical CCD is applied to the node D connected to the vertical CCD electrode. on the other hand,
Since 0 V or the negative power supply voltage Vss is applied to the source drain of the p-channel MOS transistor 48 which is gate-grounded, it does not conduct. Further, the drain of the p-channel MOS transistor 102 is also at 0 V and does not conduct, the source thereof is floating, and the coupling capacitance 101 does not become a load of the transfer pulse. Then, trigger when the transfer pulse becomes 0V.
When a high voltage is applied to the input terminals V1R and V3R, the node B becomes 0V and the n-channel MOS transistor 47
Becomes non-conductive. On the other hand, the node C becomes VDD, the p-channel MOS transistor 48 is turned on, and the node D connected to the vertical CCD electrode is applied with a voltage lower than VDD by the threshold voltage of the transistor 103. After this,
The node I changes from 0 V to VDD, the p-channel MOS transistor 102 conducts, and this voltage change further increases the voltage of the node D via the coupling capacitor 101. As described above, according to the present embodiment, a read voltage higher than the positive power supply voltage can be realized by applying the positive power supply voltage VDD to the drive electrodes of the vertical CCDs and then boosting the voltage by capacitive coupling. When it is desired to increase the coupling capacitance in order to increase the amplitude of the read pulse, the coupling capacitance may be provided outside the element.

Third Embodiment Normally, in order for the first stage driver transistor to perform a saturation operation and the output circuit to operate in a linear range, the output circuit power supply voltage is obtained by subtracting the threshold voltage of the first stage driver transistor from the reset voltage. Need to be high. Therefore, to lower the output circuit power supply voltage, the threshold voltage of the first-stage driver transistor 6 may be set to a large value. However, in the case of the conventional example in which the next-stage driver 9 has the same structure as the first-stage driver 6 as described in FIG. 15, if the threshold voltage of the transistor is too high, the next-stage driver transistor does not conduct sufficiently and the next-stage driver transistor does not conduct. Operation becomes difficult. Therefore, in the present embodiment, the substrate impurity concentration of the driver transistor of the next and subsequent stages is made lower than the substrate impurity concentration of the driver transistor of the first stage, the threshold voltage of the driver transistor of the next and subsequent stages is lowered, and It works. FIG. 11 shows an output circuit configuration diagram of the third embodiment. In the figure, 111, 112
Is a driver transistor constituting a first stage source follower, a load transistor, 113 and 114 are driver transistors constituting a next stage source follower, load transistors, 115 and 116 are driver transistors constituting a last stage source follower, Load transistor, 117
Is a bias voltage generation circuit of the load transistor described in FIG. 8, and 119 is n which is the same as the photoelectric conversion unit described in FIG.
A formation region of the p-well 21 and the double p-well 22 formed on the mold substrate 20, and 118 is a formation region of a third p-well having the same depth as the p-well 21 and having a slightly higher concentration. 2
The heavy p-well layer is set at a high concentration for suppressing smear. The output voltage of the first-stage source follower becomes a low voltage due to a voltage drop due to a large threshold voltage of the first-stage driver transistor 111. On the other hand, the threshold voltages of the driver transistors 113 and 115 of the next and final stages are small values close to 0 V, the voltage drop due to the threshold voltage is small, and the input voltage and output voltage of each stage are almost equal. Does not become difficult. According to the present embodiment, the substrate impurity concentration of the driver transistors 113 and 115 of the subsequent stage is made lower than the substrate impurity concentration of the driver transistor 111 of the first stage, so that the operating range of the subsequent stage is high without making the operating range of the subsequent stage difficult. Realizes a large voltage drop due to the threshold voltage, lowers the power supply voltage, lowers power consumption, and
A low-noise output circuit can be realized. In this embodiment, the source follower is used for the purpose of improving the frequency characteristics of the output circuit.
Has been described as a three-stage configuration, but the effect of the present invention can be similarly obtained if the number of stages is two or more. Also, an electronic shutter
Although the third p-well 118 is made slightly higher in concentration at the same depth as the p-well 21 in order to prevent malfunction at the time of the operation, when the malfunction does not become a problem, the third p-well 118 is replaced with the p-well 21.
The structure may be the same as described above. Further, load transistor 1
12, 114 and 116 may be formed in a well having the same structure as 119. Also, the driver transistor 113,
By forming 115 in an isolated well and connecting the well to the output of each source follower to eliminate the body effect, the threshold voltage of each transistor can be made closer to 0V.

Fourth Embodiment In the first embodiment, the DC voltage for discharging the excess voltage applied to the substrate is the positive power supply VDD. However, as described in the conventional example, the DC voltage needs to be adjusted for variation for each element. Therefore, in this embodiment, a DC voltage applied to the substrate is generated by stepping down from a voltage stepped up from VDD,
This step-down device is provided with a means for adjusting the voltage. A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 12 is an overall configuration diagram of the fourth embodiment, and FIG. 13 is a substrate voltage generation circuit of the fourth embodiment. 12, reference numerals 1 to 10 and 12 to 17 are the same as those in FIG. 12
Reference numeral 1 denotes a substrate voltage generation circuit shown in FIG. Also, V
1, V2, V3, V4, V1R, V3R, H1, H2,
RG, SUB, WELL, VDD, Vss, and OUT are the same as those in FIG. A trigger pulse of the timing generator, a pulse having a predetermined voltage from two power supplies, positive and negative, and a DC voltage are generated inside the device, and the same operation as described in FIG. 17 is performed. In FIG. 13, 91 to 99 are the same as in FIG. 9, 139 is the DC booster circuit similar to FIG. 7, 131 to 134 are n-channel MOS transistors for generating the bias voltage, and 135 is the fuse for adjusting the bias voltage. −
Reference numeral 137 denotes an n-channel depletion MOS transistor similar to that constituting a CCD for generating a DC substrate voltage by lowering the boosted voltage according to a bias voltage.
Reference numeral 38 denotes a load transistor for supplying a slight bias current to the transistor 137, and reference numeral 136 denotes a circuit for supplying a bias voltage to the load transistor 138, as in FIG. The output voltage of the booster circuit 139 drops to a voltage higher than the bias voltage generated by 131 to 134 by an absolute value of the threshold voltage of the n-channel depletion MOS transistor 137, and becomes a substrate DC voltage. The bias current supplied from the load 138 prevents a malfunction when a high voltage is generated on the substrate. Further, even if a bias voltage equal to or lower than the power supply voltage VDD is applied by performing the voltage drop with the n-channel depletion MOS transistor, the voltage VDD may be reduced.
The above-described substrate voltage can be generated. Also, the switch 98 connects its well to the output of the substrate voltage generating circuit to transmit a voltage higher than VDD, thereby preventing a threshold voltage increase due to the substrate effect. Other operations of this circuit are the same as those in FIG. Adjust the substrate voltage as necessary.
This is made possible by cutting the hole 135. By cutting the fuse, the voltage at node J rises and the substrate voltage rises. According to the present embodiment, the DC voltage applied to the substrate is generated by stepping down the voltage from the voltage boosted from VDD, and by adding a means for adjusting the voltage to this step-down device, the substrate voltage can be adjusted inside the device, and the CCD type imaging can be performed. The usability of the element is improved.

Fifth Embodiment In the first embodiment, a trigger pulse must be externally applied to each terminal. To construct a camera system, a timing generator and a two-dimensional CCD type element are wired. There must be. The present embodiment is an example in which a timing generator is incorporated to avoid such complication. FIG. 14 shows a configuration diagram of the fifth embodiment. In the figure, 1 to 17 are the same as those in FIG. 1, and 141 is a step-down circuit for generating the power of the timing generator 142 from an external positive power supply VDD. A timing pulse of each pulse is generated from an external basic clock by the timing generator 142, and this pulse and a pulse of a predetermined voltage level and a DC voltage are generated from the positive and negative power supplies as in FIG. Is performed. According to the present embodiment, a two-dimensional CCD type solid-state imaging device which can be driven by a single external pulse, two positive and negative power supplies and an earth, and is easy to use can be provided.

In the above embodiment, an inter-line CCD is used.
Although the example of the type imaging device has been described, the present invention is not limited to the specific configuration of the CCD type imaging device, and may be a frame inter-line type,
C such as frame transfer type and charge sweep type
The same can be applied to a CD-type image sensor. Further, the present invention has the same effect regardless of the specific configuration of the vertical CCD and the horizontal CCD, for example, in a CCD type image pickup device in which two horizontal CCDs are provided in parallel. As a result, the first embodiment is driven under the driving conditions shown in Table 2, and FIG.
7 is used in the camera system.
The fifth embodiment is driven under the driving conditions shown in Table 3, and is used in a camera system with the configuration shown in FIG. In each case, it can be seen that the types of power supply voltages are much smaller than those shown in Table 1 of the related art.

[0032]

[Table 2]

[0033]

[Table 3]

[0034]

According to the present invention, a CCD type image pickup device is provided.
Since an external driver is not required, the number of power supplies supplied by the external DC-DC converter is reduced, and it is not necessary to adjust the DC voltage applied to the substrate when creating a camera system, so that the usability is improved. Further, the number of power supplies supplied from the DC-DC converter is reduced, and even if the power supply voltage of the timing generator is reduced, it is not necessary to provide a driver for driving the horizontal CCD outside the element outside the element. Electricity can be achieved. Further, since the reset voltage of the output circuit can be reduced, and the power supply voltage of the output circuit can be reduced from the reset voltage, power consumption and noise of the output circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a portion corresponding to AA ′ and BB ′ in FIG. 1 and a cross-sectional structure of a p-channel MOS transistor.

FIG. 3 is a circuit diagram showing a vertical CCD transfer pulse generation circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a vertical CCD ternary pulse generating circuit of FIG. 1;

FIG. 5 is a circuit diagram showing a horizontal CCD transfer pulse generation circuit of FIG. 1;

FIG. 6 is a circuit diagram showing a reset pulse generation circuit of FIG. 1;

FIG. 7 is a circuit diagram showing a reset voltage generating circuit of FIG. 1;

FIG. 8 is a circuit diagram showing a bias voltage generation circuit of the output circuit load transistor of FIG. 1;

FIG. 9 is a circuit diagram showing a substrate voltage generation circuit of FIG. 1;

FIG. 10 is a circuit diagram showing a vertical CCD ternary pulse generating circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating an output circuit configuration according to a third embodiment of the present invention.

FIG. 12 is a diagram showing an overall configuration of a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating the substrate voltage generation circuit of FIG. 12;

FIG. 14 is a diagram showing an overall configuration of a fifth embodiment of the present invention.

FIG. 15 is a diagram showing an overall configuration of a conventional CCD solid-state imaging device.

FIG. 16 is a block diagram of a conventional CCD camera.

FIG. 17 shows the CC of the CCD solid-state imaging device according to the first embodiment;
It is a D camera block diagram.

FIG. 18 shows a CC of a CCD solid-state imaging device according to a fifth embodiment;
It is a D camera block diagram.

[Explanation of symbols]

1. Photo diode, 2. Vertical CCD, 3.
... Horizontal CCD, 4 ... Output gate, 5 ... Reset gate, 6, 111 ... First stage source follower driver transistor, 8, 112 ... First stage source follower load transistor, 9, 113 ... Next stage source follower -Driver transistor, 10, 114 ... next stage source follower load transistor, 11, 121 ... substrate voltage generation circuit, 12 ... vertical CC
D transfer pulse generation circuit, 13 vertical CCD tri-level pulse generation circuit, 14 horizontal transfer pulse generation circuit, 15 reset pulse generation circuit, 16 reset voltage generation circuit, 17 load gate bias generation circuit, 20 n-type Substrate, 21 ... p-type well, 22 ... p-type double well,
23: vertical CCD n-layer, 24: polysilicon electrode, 25: n-well, 26
... Photodiode n layer, 27. Surface p + layer, 28. Light shielding second layer aluminum, 29. First wiring aluminum layer, 30. n-type diffusion layer, 31, 41, 51, 71, 91, 97, 101: coupling capacitance, 32, 42, 52, 92: clamp diode, 33, 43, 37, 53, 63, 93: first inverting circuit n
Channel transistor, 34, 44, 38, 54, 64, 94 ... first inverting circuit p
Channel transistor, 35, 45, 39, 55, 65, 95 ... second inverting circuit n
Channel transistor, 36, 46, 40, 56, 66, 96... Second inversion circuit p
Channel transistor, 47 ... n-channel transistor switch, 48, 102 ... p-channel transistor switch, 57 ... p-channel transistor voltage limiter, 58, 59 ... p-channel transistor for voltage limit, 60, 61, 62, 81, 82, 83, 131, 13
2, 133, 134: bias voltage generating circuit n-channel transistor, 72, 73, 103: boost circuit n-channel transistor, 98: n-channel depletion transistor switch, 99: substrate capacitance, 104: third inverting circuit n-channel transistor, 105 ... 3rd inversion circuit p-channel transistor, 106 ... 4th inversion circuit n-channel transistor, 107 ... 4th inversion circuit p-channel transistor, 115 ... final stage source follower driver transistor, 116 ... final stage source follower load transistor 117, 136... Bias voltage generation circuit, 118
... Third p-well, 119, formation region of p-well 21 and p-type double well 22, 135, fuse, 137, n-channel depletion transistor voltage limiter, 138, load n-channel transistor, 139
... booster circuit, 141 ... step-down circuit, 142 ... timing generation circuit, V1, V2, V3, V4 ... vertical CCD transfer trigger-pulse input terminal, V1R, V3R ... vertical CCD readout trigger-pulse input terminal, H1, H2 ... horizontal CCD transfer trigger-pulse input terminal, RG ... reset trigger-pulse input terminal, SUB ... electronic shutter trigger-pulse input terminal, VD
D: Positive power supply input terminal, Vss: Negative power supply input terminal, OUT: Signal output terminal, WELL: Well voltage input terminal, 161, 171, 181: CCD image sensor, 162: Timing generator, 163: Driver, 164 ... Correlation double sampling circuit, 165 automatic gain control circuit, 166 A / D converter, 167 digital signal processing circuit, 168 D / A converter, 169 DC-DC converter, 170 battery of camera.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Haruhiko Tanaka 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory, Inc. Central Research Laboratory (72) Inventor Akira Sato 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Central Research Laboratory, Hitachi, Ltd.

Claims (2)

(57) [Claims] A first conductivity type semiconductor substrate; a second conductivity type well formed on the semiconductor substrate; and a plurality of first conductivity type regions formed in the well. In a CCD solid-state imaging device comprising a photodiode for converting light into signal charge and storing the signal charge in the well and the first conductivity type region, a DC for discharging excess charge to the semiconductor substrate is provided on the semiconductor substrate. A DC voltage generating circuit for applying a voltage; and a pulse applying unit for applying a pulse to the semiconductor substrate, wherein the pulse applying unit applies the pulse to the semiconductor substrate.
When a pulse is applied, the output of the DC voltage generation circuit
Means for disconnecting the semiconductor substrate from the semiconductor substrate.
A coupling capacitance provided on or outside the semiconductor substrate.
Wherein the DC voltage generation circuit is provided with output voltage adjusting means, and the DC voltage is adjusted by the output voltage adjusting means. . 2. The CCD type solid-state imaging device according to claim 1, wherein said output voltage adjusting means has a fuse which can be cut.