JP3309932B2 - Control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device, in which a plurality of slots are provided in a base unit and connected to each other by signal lines, and a main control unit and a controlled unit controlled thereby are mounted in those slots. And a control device connected to the control device.

[0002]

2. Description of the Related Art Conventionally, this type of control device is, for example, shown in FIG.
, A plurality of slots 1, 3, 5, 7,... Connected to each other by signal lines (not shown) are provided in the base unit 9, and a box-shaped power supply unit 11, a CPU unit 13, and each output A plurality of input / output units 15, 17...
There is known a device configured to be connected so as to be attached to. In such a control device, the power supply unit 11 supplies power to the other units 13 to 17.
From the PU unit 13 to the input / output units 15, 17, ...
, For example, the CPU unit 13 determines or calculates an operation procedure or an operation amount based on the measured temperature input from the input / output units 15, 17,...
7 output these operation procedures and operation amounts to a control target (not shown) to control the temperature of the control target by sequence control or program control.

[0003] Reference numerals 19a, 19b, 19c, 1 in FIG.
.. 9d are connection terminals of the slots 1, 3, 5, 7,. That is, each of the slots 1, 3, 5, 7,...
The unit 13, the input / output units 15, 17,... Have connection terminals 19a, 1 of the respective slots 1, 3, 5, 7,.
There are connection terminals inserted and connected to 9b, 19c, 19d,..., But they are hidden and invisible. The input / output signal forms include analog signals and digital signals as well as a plurality of analog signals. Each of the input / output units 15, 17,.
.. Have a configuration corresponding to these input / output signal forms.
3 need to specify the input / output units 15, 17,... By address calling and perform the desired input / output control.

Therefore, each of the input / output units 15, 17,...
, For each of the slots 1, 3,
.., Or after mounting, it is necessary to assign a unique input / output address. Therefore, conventionally, address assignment terminals and dip switches (both not shown) are arranged on a circuit board or the like inside each of the input / output units 15, 17,... And the type of each of the input / output units 15, 17,. Then, the terminals are short-circuited by an address jumper wire or a dip switch is operated to set the addresses of the input / output units 15, 17,.... For example, the digital input / output unit does not have an address number such as "1" to "5" and the analog input / output unit has a number such as "6" to "9". The user was careful in setting the type and function group so as not to make a mistake.

[0005]

However, in the conventional control device described above, the user sets the address number of each of the input / output units 15, 17,... By short-circuiting the address jumper wire or operating the dip switch. The address setting operation is not only troublesome,
If the user mistakenly sets the same address number to the plurality of input / output units 15, 17,..., The device does not operate as intended. In addition, recently, with the increase in the number of functions of the CPU unit 13 or the complexity of the functions, it has become necessary to distribute functions that can be distributed to other units, and other units including the input / output units 15, 17,... There is a tendency to mount a CPU.

Therefore, input / output units 15, 17,...
Memory used by the CPU mounted on the CPU unit 1
3 need to be shared, and the CPU unit 13
Must be specified by specifying an address number or the like for the memories in the input / output units 15, 17,..., And in addition to the above-described address number settings for the input / output units 15, 17,. There has been a demand for a configuration that can increase the number of these setting operations easily. The present invention has been made under such a situation, and an object of the present invention is to provide a control device that does not require address setting for a controlled unit controlled by a main control unit. Another object of the present invention is to provide a control device capable of automatically specifying a plurality of circuits forming a controlled unit.

[0007]

According to the present invention, a plurality of slots connected by signal lines are provided.
Provided in the base unit, and the main control unit
Connected to the controlled unit controlled by this
Slot to output the identification signal of each slot.
The identification unit is connected to at least those controlled units.
And the controlled unit has
Slot specified from the main control unit of the
Address signal and the identification signal from the slot identification unit.
Are matched, the plurality of units forming the controlled unit
A decoder that outputs a signal specifying an operation circuit;
You.

In the present invention, the slot is formed by a connection connector, and the slot identification portion is formed by a connection terminal which is a part of the connection terminal forming the connection connector and outputs an identification signal thereof. It is preferable to form the slot identification portion from a connection terminal to which a high or low level voltage is connected.

[0009]

According to the present invention having such means, a specific slot is designated from the main control unit via a signal line while the main control unit and the controlled unit are connected to individual slots of the base unit. When the address signal is output, the decoder of the controlled unit compares the address signal with the identification signal from the slot identification unit, and outputs a signal specifying a plurality of operation circuits forming the controlled unit when the contents match each other. Therefore, the plurality of operation circuits that form the unit together with the controlled unit, and the operation circuit specified by the specific signal can be operated.

In the configuration in which the slot identification portion is formed by a part of the connection terminals of the connection connector, the identification signal is automatically taken into the controlled unit only by connecting the controlled unit to the slot. Further, in the configuration in which the connection terminal connected to the high or low level voltage forms the slot identification portion, the output of various identification signals is performed by connecting the connection terminal of the slot identification portion to the power supply or the ground line on the base unit side. It becomes possible.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Before giving a detailed description of the present invention, its outline will be described for convenience. FIG. 1 is a schematic block diagram showing a control device according to the present invention. The present invention generally includes a plurality of slots 21, 23, 25, connected by signal lines (not shown).
27 are arranged in a base unit 29, of which a CPU unit 31 as a main control unit is connected to the slot 21, and other slots 23, 25, 27,.
The input / output unit 3 as a controlled unit
3, 35, 37 ... are connected. In addition,
The actual connection states of the CPU unit 31 and the input / output units 33, 35, 37,... To the slots 21, 23, 25, 27,. Slot 2
, 3, 25, 27,... Are formed with slot identification sections 39, 41, 43,... For outputting identification signals for specifying individual slots, and input / output connected to the slots 23, 25, 27,. The units 33, 35, 37,... Can input the identification signals.

Each input / output unit 33, 35, 37 ...
Are the slots 23, 25, 27 ... of the base unit 29.
When the address signals designating the slots 23, 25, 27,... Input from the CPU unit 31 via the... Control operation. In FIG.
.. Are the base unit 2
9, three input / output units 33, 3
5, 37 are connected, but the number of input / output units is arbitrary. Further, the illustration of the power supply unit and the slot to which the power supply unit is connected is omitted in FIG. The same applies to the following description and drawings.

Next, the details of such a control device of the present invention will be described with reference to FIGS. FIG. 2 is a view showing the slots 21, 23, 25, and 27 arranged in the base unit 29 in the control device described above. 2, as shown in FIG. 4, a plurality of slots 21, 23, 25, and 27 made of a connector having a plurality of connection terminals are arranged in a base unit 29, and at least an input / output unit 33 is provided. , 35, and 37 to be connected have the same configuration. In FIG. 2, the input / output units 33, 35, 37 are not shown. It is to be noted that three or more or less slots can be arranged and configured as in FIG. Connection terminals 45a to 45c, 47a to 47c, 49a to 49c at the same positions in the slots 21, 23, 25, 27;
Address signal lines S1, data signal lines S2, and control signal lines S3 are connected in parallel to 51a to 51c. Of course, other signal lines are connected as necessary, but are not shown.

The four connection terminals 47d-47g, 49d-49g and 51d-5 in the slots 23, 25, 27 to which the input / output units 33, 35, 37,.
1g forms slot identification sections 39, 41, 43 for assigning and specifying addresses to the input / output units 33, 35, 37. That is, all the connection terminals 47 d to 47 g of the slot 23 are grounded in the base unit 29, and 49 out of the connection terminals 49 d to 49 g of the slot 25.
d to 49f are grounded, and the remaining connection terminals 49g are connected to a power supply line (simply indicated by a power supply) V in the base unit 29.
Among the 1d to 51g, 51d, 51e, and 51g are grounded, and the connection terminal 51f is connected to the power supply line V. For example, the slot identification unit 3 that specifies the slot 23 of the address 1, the slot 25 of the address 2, and the slot 27 of the address 3
9, 41 and 43 are formed.

Therefore, if the allocated addresses 0 to 2 are represented by 4-bit data, the slot identification units 3
The identification signals from 9, 41 and 43 are “0000”, “00”
01 "and" 0010 ".
By using d to 47 g, 49 d to 49 g, and 51 d to 51 g, 16 types of identification signals from address 0 to address F can be output. Slot identification units 39, 41, 4
By increasing the number of connection terminals of No. 3, the number of identifiable slots (number of addresses) can also be increased. The power supply line V and the ground line in the base unit 29 extend from, for example, a power supply unit (not shown).

FIG. 3 is a specific block diagram showing the relationship between the slots 21, 23, 25, 27 arranged in such a base unit 29, the CPU unit 31, and the input / output units 33, 35, 37. For convenience, only the slots 21 and 27, the CPU unit 31 and the input / output unit 37 are shown, and the illustration of the other slots 23 and 25 and the input / output units 33 and 35 is omitted. 3, the CPU unit 31 connected to the slot 21 of the base unit 29 includes a control unit 53 and an address buffer 5 for the address signal s1 output from the control unit 53 to the slot 21.
5, a data buffer s2 for the data signal s2 output from the control unit 53 to the slot 21 and a data signal s2 fetched from the slot 21 to the control unit 53, and a control buffer 59 for the control signal s3 output from the control unit 53. (See FIG. 4 for the external shape). Each buffer 55
59 are for timing adjustment.

The control unit 53 includes a CPU, a ROM containing a program for executing input / output control of each address signal s1, data signal s2 and control signal s3 and the like by the CPU, and a RAM for storing these signals. Etc. are included, but illustration is omitted. The CPU unit 31 outputs the address signal s1 output via the address buffer 55.
(For example, the signal “0000”, “0001” or “001”
0 ") to specify one of the slots 23 to 27, and an address signal s1 to which a signal specifying an identification code section 63 and the like described later is added.
Specify etc. Further, the CPU unit 31 sends the control signal s3 via the control buffer 59 to the input / output unit 37.
To execute a function corresponding to the control signal s3,
For example, the data signal s2 is output from the control unit 53 to the input / output unit 37 via the data buffer 57, and the data signal s2 from the input / output unit 37 is taken into the control unit 53 via the data buffer 57 for processing. It has a function and a judgment calculation function as a control device.

The input / output unit 37 connected to the slot 27 of the base unit 29 includes a decoder 61, an identification code section 63, an I / O 65, a shared memory 67, a CPU 69,
It is formed in a box shape having an address signal line S1, a data signal line S2, and a control signal line S3 (the outer shape is shown in FIG.
reference). When the decoder 61 detects that the identification signal from the slot identification section 43 of the input / output unit 37 matches the address signal s1 input from the CPU unit 31 via the slot 27 and the address signal line S1, It has a function of putting the output unit 37 into an operating state. That is, when the address signal s1 “0010” input from the CPU unit 31 matches the identification signal “0010” from the slot identification unit 43, the input / output unit 37 is activated.

Further, the decoder 61 has an address signal s1 to which an identification code section 63 forming the input / output unit 37, an I / O 65 and a signal designating the shared memory 67 are added.
Is input, if the signal portion designating the slot 27 matches the identification signal from the slot identification section 43, the identification code section 63, the I / O 65, or the shared memory 67 is specified to enable the operation. It has a function of outputting a signal. However, the address signal s1 output from the CPU unit 31 is, for example, “002”, “102”,
The lower two digits of the address signal indicate, for example, the address (number of addresses) of the slot described above, and the upper digit is a circuit forming the input / output units 33 to 37, for example, the slot identification unit 63. The decoder 61 decodes the meaning of the address signal s1 and compares it with the identification signal from the slot identification unit.
If they match, an ON signal is output to the identification code section 63 and the like. Therefore, the input / output unit 35 to be connected to the slot 25 of the address 1 is attached to the slot 27 of the address 2 in FIG. 25, the input / output unit 37 does not operate even if the CPU unit 31 designates the slot 27 at address 2, and the input / output unit 35 mounted in the slot 27 at address 2 operates. That is, when the input / output unit 35 is attached to the slot 27 of the address 2, the CPU unit 31 substantially automatically sets the address 2 of the slot 27.

In the identification code section 63, a code indicating the function of the input / output unit 37 is set in advance, and when the read control signal s3 is output from the CPU unit 31 with the ON signal input from the decoder 61. And outputs the code indicating the input / output unit 37 to the data signal line S2 as a data signal s2. The code set in the identification code section 63 is a code such as “1” if the input / output unit 37 is a temperature input / output unit, and “2” if the input / output unit 37 is a sequencer unit.
After confirming this code, the U unit 31 executes control of the input / output unit 37.

The I / O 65 has a function of exchanging data with an external device. In addition, when the ON signal is input from the decoder 61 and the read control signal s3 is input from the CPU unit 31, the data signal line S2 Data s
2 is provided. Also, I / O 65 is
When a write control signal s3 is input from the CPU unit 31, the CPU has a function of reading the data signal s2 from the CPU unit 31 from the data signal line S2. The shared memory 67 is a storage unit that shares data with a CPU (not shown) forming the control unit 53 of the CPU unit 31 and is formed of a dual-port RAM.
The CPU 69 of the input / output unit 37 is also a common storage unit.

When the read control signal s3 is input from the CPU unit 31 to the shared memory 67 to which the ON signal is input from the decoder 61, the shared memory 6
7 outputs a data signal s2 to a data signal line S2,
When the write control signal s3 is input, the CPU unit 3
1 has a function of reading the data signal s2 from the data signal line S2. The CPU 69 is the CPU unit 31
It has a function different from the function of, for example, I / O6
5 functions as a control unit when exchanging data with an external device, or calculates an operation amount based on, for example, the acquired measured temperature data, and shares this operation amount as display data to be transmitted to the CPU unit 31. It has a function of storing in the memory 67 and other functions.

Next, the operation of the control device of the present invention will be briefly described. As shown in FIG. 3, while the CPU unit 31 is connected to the slots 21 arranged in the base unit 29 and the input / output unit 37 is connected to the slot 27 of the address 2, the slot identification unit of the slot 27 of the address 2 From 43, the identification signal “0010” is input to the decoder 61 of the input / output unit 37. In this state CP
When the address signal s1 specifying the address 2 is input from the U unit 31 to the decoder 61, the decoder 61 decodes the address signal “002”, “102” or “202”, and the identification signal “0010” and the address signal s1. Is detected, the address signal “002”,
The identification code part 63 according to “102” or “202”,
An ON signal is output to the I / O 65 or the shared memory 67.

Therefore, the input / output unit 37 is automatically assigned to the address 2, and the identification code section 63, the I / O 65, or the shared memory 67 forming the input / output unit 37 automatically becomes operable. The same applies to the other input / output units 33 and 35. And C
When the PU unit 31 receives, for example, the code “1” from the identification code unit 63 of the input / output unit 37 and confirms it,
The input / output unit 37 can be controlled under the control of the U unit 31, and the CPU unit 31 outputs the address signal s1 to the input / output unit 37 to control the identification code unit 63, the I / O 65, or the shared memory 67. For example, data read / write and data exchange with an external device are performed.

On the other hand, the slot 27 of the base unit 29
Even if another address signal, for example, an address signal "1" is input from the CPU unit 31 to the decoder 61 to the input / output unit 37 connected to the decoder 61, the decoder 61 outputs the identification signal "0010" and the contents of the address signal s1. Are not detected as matching, the identification code section 63, I /
O65, no ON signal is output to the shared memory 67, and the input / output unit 37 does not enter an operable state. Thus, the control device of the present invention includes the input / output units 33, 3
Slots 23, 25, 27 to which the slots 5, 37 are connected are arranged in the base unit 29, and slot identification sections 39, 4 for outputting identification signals identifying the slots 23, 25, 27.
1 and 43, and an address signal s for designating any of the slots 23, 25 and 27 from the CPU unit 31.
1 and the input / output units 33, 35 and 37 are formed so as to operate when the identification signals from the slot identification sections 39, 41 and 43 coincide with each other.
By simply connecting the input / output units 33, 35, 37 to 5, 27, the input / output units 33, 35, 37 are activated.

Therefore, unlike the related art, the user does not need to short-circuit the individual input / output units 33, 35, and 37 with the address jumper lines or operate the dip switches to set the address. The trouble of setting can be omitted, the address setting is accurate, and the number of settings for the input / output units 33, 35, 37 is not increased. In addition, the slots 23, 2
Slot identification sections 39, 41, 43 provided in 5, 27,
As shown in FIG.
47g, 49d to 49g, and 51d to 51g, so that slots 23, 25,
If the slot identification portions 39, 41, 43 are formed when arranging the slots 27, not only the setting error can be prevented and the configuration is simple, but also the input / output units 33, 35, Since it can be brought into the operating state only by connecting the 37, a special address setting operation by the user is not required.

Further, the slot identification sections 39, 41, 43
Are connection terminals 47d to 47g, 49d to 49g, 51d
Since the power supply line V or the ground line, that is, the high or low potential of the base unit 29 is connected to the base unit 29 to 51 g, various identification signals can be output only by changing the potential connection, and the manufacturing is possible. Assembly and configuration are simple. Moreover, the above-mentioned input / output units 33, 35, 37
Outputs an ON signal that specifies a plurality of operation circuits forming the input / output units 33, 35, and 37 when the identification signals from the slot identification sections 39, 41, and 43 match the address signals from the CPU unit 31. Decoder 6
1 , the operation circuits that form the input / output units 33, 35, and 37 as well as the input / output units 33, 35, and 37 themselves are automatically specified, and the conventional address allocation is simplified. Operability is further improved.

In the above-described embodiment, an example in which the CPU unit 31 is used as the control unit and the input / output units 33, 35, and 37 are used as controlled units, but in the present invention, another unit is used as the control unit and the controlled unit. Can be connected, and a slot identification section can be formed in a slot to which the control unit is connected. In short, the present invention can be implemented in a control device having a configuration in which a control unit and a controlled unit controlled by the control unit are connected to a slot, and a slot identification unit may be formed at least in a slot to which the controlled unit is connected. In the control device of the present invention, the address setting has a broad meaning of specifying a slot, a controlled unit, and an operation circuit constituting the unit.

[0029]

As described above, according to the control apparatus of the present invention, a slot identification for outputting an identification signal for identifying this slot to at least a slot to which a controlled unit is connected among a plurality of slots arranged in a base unit. A controlled unit is formed when an address signal of a slot designated by the main control unit matches an identification signal from the slot identification unit.
A decoder for outputting a signal specifying a plurality of operation circuits is received.
Formed in control unit. Therefore , if the controlled unit is not connected to the slot designated by the main control unit , the controlled unit does not operate, and the controlled unit is substantially automatically addressed by the main control unit, and the address setting is performed. And erroneous address setting can be prevented. Further, by outputting an address signal designating a specific slot from the main control unit, the controlled unit and a specific operation circuit forming the controlled unit can be made operable, so that the operation is further simplified. is there. In the configuration in which the slot identification part is formed by a part of the connection terminal connected to the controlled unit, the identification signal is automatically taken into the controlled unit simply by connecting the controlled unit to the slot, and the operation is performed. Can be enabled. Further, in a configuration in which the connection terminal connected to the high or low level voltage forms the slot identification portion,
Various identification signals can be output by connecting the connection terminal of the slot identification section to a power supply or a ground line on the base unit side.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an outline of a control device according to the present invention.

FIG. 2 is a diagram showing a base unit and a slot in one embodiment of the control device of the present invention.

FIG. 3 is a block diagram showing a base unit, a slot, a main control unit, and a controlled unit in one embodiment of the control device of the present invention.

FIG. 4 is a schematic perspective view showing a relationship between slots arranged in a base unit and each unit in a control device according to the present invention in a state where they are separated from each other.

[Explanation of symbols]

1, 3, 5, 7, 21, 23, 25, 27 Slot 9, 29 Base unit 11 Power supply unit 13, 31 CPU unit (Main control unit) 15, 17, 33, 35, 37 Input / output unit (Controlled unit ) 19a, 19b, 19c, 19d, 45a to 45c, 4
7a-47c, 49a-49c, 51a-51c Connection terminals 39, 41, 43 Slot identification unit 53 Control unit 55 Address buffer 57 Data buffer 59 Control buffer 61 Decoder 63 Identification code unit 65 I / O 67 Shared memory 69 CPU

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-337805 (JP, A) JP-A-56-11506 (JP, A) JP-A-60-193011 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) G05B 19/05 G06F 13/14 320

Claims (3)

(57) [Claims] A plurality of slots connected by signal lines;
The main control unit is installed in each of the slots.
Unit and the controlled unit controlled by it.
In the control device, a slot connected to at least the controlled unit is provided.
Slot that outputs an identification number identifying this slot to the
The identification unit is provided, and the controlled unit includes the main control unit
An address signal of the slot specified through a signal line
And the identification signal from the slot identification section,
When the address signal and the identification signal match, the controlled unit
Outputs signals that identify multiple operation circuits that form the unit
A control device, comprising: 2. The slot is formed from a connector.
Wherein the slot identification part forms the connection connector
A connection that is a part of the connection terminals and outputs the identification signal.
The control device according to claim 1, comprising a terminal. 3. A high-level or low-level slot identifying section.
Claims formed from connected terminals of a bell voltage
Item 3. The control device according to Item 2.